Mercurial > mplayer.hg
annotate cpudetect.c @ 2284:0c5fea3a0b91
amd...?
author | pontscho |
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date | Fri, 19 Oct 2001 13:28:59 +0000 |
parents | baea37ed31f9 |
children | dac462a0ac8c |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
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3 |
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4 #ifdef ARCH_X86 |
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5 |
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6 #include <stdio.h> |
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7 |
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8 #ifdef __FreeBSD__ |
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9 #include <sys/types.h> |
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10 #include <sys/sysctl.h> |
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11 #endif |
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12 |
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13 #ifdef __linux__ |
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14 #include <signal.h> |
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15 #endif |
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16 |
2272 | 17 //#define X86_FXSR_MAGIC |
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18 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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19 * help understanding how to use it. Thanks to the Mesa |
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20 * team for SSE support detection and more cpu detect code. |
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21 */ |
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22 |
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23 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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24 |
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25 CpuCaps gCpuCaps; |
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26 static void check_os_katmai_support( void ); |
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27 |
2272 | 28 #if 1 |
29 // return TRUE if cpuid supported | |
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30 static int has_cpuid() |
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31 { |
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32 int a, c; |
2272 | 33 |
34 // code from libavcodec: | |
35 __asm__ __volatile__ ( | |
36 /* See if CPUID instruction is supported ... */ | |
37 /* ... Get copies of EFLAGS into eax and ecx */ | |
38 "pushf\n\t" | |
39 "popl %0\n\t" | |
40 "movl %0, %1\n\t" | |
41 | |
42 /* ... Toggle the ID bit in one copy and store */ | |
43 /* to the EFLAGS reg */ | |
44 "xorl $0x200000, %0\n\t" | |
45 "push %0\n\t" | |
46 "popf\n\t" | |
47 | |
48 /* ... Get the (hopefully modified) EFLAGS */ | |
49 "pushf\n\t" | |
50 "popl %0\n\t" | |
51 : "=a" (a), "=c" (c) | |
52 : | |
53 : "cc" | |
54 ); | |
55 | |
56 return (a!=c); | |
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57 } |
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58 #endif |
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59 |
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60 static void |
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61 do_cpuid(unsigned int ax, unsigned int *p) |
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62 { |
2272 | 63 #if 0 |
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64 __asm __volatile( |
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65 "cpuid;" |
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66 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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67 : "0" (ax) |
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68 ); |
2272 | 69 #else |
70 // code from libavcodec: | |
71 __asm __volatile | |
72 ("movl %%ebx, %%esi\n\t" | |
73 "cpuid\n\t" | |
74 "xchgl %%ebx, %%esi" | |
75 : "=a" (p[0]), "=S" (p[1]), | |
76 "=c" (p[2]), "=d" (p[3]) | |
77 : "0" (ax)); | |
78 #endif | |
79 | |
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80 } |
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81 |
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82 |
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83 void GetCpuCaps( CpuCaps *caps) |
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84 { |
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85 unsigned int regs[4]; |
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86 unsigned int regs2[4]; |
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87 |
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88 bzero(caps, sizeof(*caps)); |
2272 | 89 printf("CPUid available: %s\n",has_cpuid()?"yes":"no"); |
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90 /*if (!has_cpuid()) |
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91 return;*/ |
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92 do_cpuid(0x00000000, regs); |
2281 | 93 printf("CPU vendor name: %.4s%.4s%.4s cpuid level: %d\n",®s[1],®s[3],®s[2],regs[0]); |
94 if (regs[0]>0x00000001) | |
2280 | 95 { |
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96 do_cpuid(0x00000001, regs2); |
2272 | 97 printf("CPU family: %d\n",(regs2[0] >> 8)&0xf); |
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98 switch ((regs2[0] >> 8)&0xf) { |
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99 case 3: |
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100 caps->cpuType=CPUTYPE_I386; |
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101 break; |
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102 case 4: |
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103 caps->cpuType=CPUTYPE_I486; |
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104 break; |
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105 case 5: |
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106 caps->cpuType=CPUTYPE_I586; |
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107 break; |
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108 case 6: |
2280 | 109 caps->cpuType=CPUTYPE_I686; |
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110 break; |
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111 default: |
2281 | 112 caps->cpuType=CPUTYPE_I386; |
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113 printf("Unknown cpu type, default to i386\n"); |
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114 break; |
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115 } |
2272 | 116 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
117 | |
118 // FIXME: is this ok for non-intel CPUs too? (cyrix,amd) | |
119 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
120 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
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121 /* FIXME: Does SSE2 need more OS support, too? */ |
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122 #if defined(__linux__) || defined(__FreeBSD__) |
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123 if (caps->hasSSE) |
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124 check_os_katmai_support(); |
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125 if (!caps->hasSSE) |
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126 caps->hasSSE2 = 0; |
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127 #else |
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128 caps->hasSSE=0; |
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129 caps->hasSSE2 = 0; |
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130 #endif |
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131 /* FIXME: Are MMX2 ops on the same set of processors as SSE? Do they need OS support?*/ |
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132 caps->hasMMX2 = caps->hasSSE; |
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133 } |
2272 | 134 if (regs[1] == 0x68747541 && // AuthenticAMD |
135 regs[3] == 0x69746e65 && | |
136 regs[2] == 0x444d4163) { | |
2284 | 137 do_cpuid(0x00000001, regs2); |
138 printf("CPU family: %d\n",(regs2[0] >> 8)&0xf); | |
139 switch ((regs2[0] >> 8)&0xf) { | |
140 case 3: | |
141 caps->cpuType=CPUTYPE_I386; | |
142 break; | |
143 case 4: | |
144 caps->cpuType=CPUTYPE_I486; | |
145 break; | |
146 case 5: | |
147 caps->cpuType=CPUTYPE_I586; | |
148 break; | |
149 case 6: | |
150 caps->cpuType=CPUTYPE_I686; | |
151 break; | |
152 default: | |
153 caps->cpuType=CPUTYPE_I386; | |
154 printf("Unknown cpu type, default to i386\n"); | |
155 break; | |
156 } | |
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157 do_cpuid(0x80000000, regs); |
2282 | 158 printf("AMD cpuid-level: 0x%X\n",regs[0]); |
2272 | 159 if (regs[0]>=0x80000001) { |
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160 do_cpuid(0x80000001, regs2); |
2281 | 161 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
162 caps->hasMMX2 = (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2272 | 163 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
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164 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; |
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165 } |
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166 } |
2272 | 167 #if 0 |
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168 printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
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169 gCpuCaps.hasMMX, |
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170 gCpuCaps.hasMMX2, |
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171 gCpuCaps.hasSSE, |
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172 gCpuCaps.hasSSE2, |
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173 gCpuCaps.has3DNow, |
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174 gCpuCaps.has3DNowExt ); |
2272 | 175 #endif |
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176 |
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177 } |
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178 |
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179 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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180 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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181 { |
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182 printf( "SIGILL, " ); |
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183 |
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184 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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185 * instructions are 3 bytes long. We must increment the instruction |
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186 * pointer manually to avoid repeated execution of the offending |
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187 * instruction. |
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188 * |
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189 * If the SIGILL is caused by a divide-by-zero when unmasked |
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190 * exceptions aren't supported, the SIMD FPU status and control |
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191 * word will be restored at the end of the test, so we don't need |
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192 * to worry about doing it here. Besides, we may not be able to... |
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193 */ |
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194 sc.eip += 3; |
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195 |
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196 gCpuCaps.hasSSE=0; |
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197 } |
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198 |
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199 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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200 { |
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201 printf( "SIGFPE, " ); |
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202 |
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203 if ( sc.fpstate->magic != 0xffff ) { |
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204 /* Our signal context has the extended FPU state, so reset the |
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205 * divide-by-zero exception mask and clear the divide-by-zero |
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206 * exception bit. |
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207 */ |
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208 sc.fpstate->mxcsr |= 0x00000200; |
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209 sc.fpstate->mxcsr &= 0xfffffffb; |
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210 } else { |
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211 /* If we ever get here, we're completely hosed. |
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212 */ |
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213 printf( "\n\n" ); |
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214 printf( "SSE enabling test failed badly!" ); |
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215 } |
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216 } |
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217 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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218 |
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219 /* If we're running on a processor that can do SSE, let's see if we |
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220 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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221 * haven't been configured for a Pentium III but are running on one, |
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222 * and RedHat patched 2.2 kernels that have broken exception handling |
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223 * support for user space apps that do SSE. |
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224 */ |
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225 static void check_os_katmai_support( void ) |
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226 { |
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227 #if defined(__FreeBSD__) |
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228 int has_sse=0, ret; |
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229 size_t len=sizeof(has_sse); |
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230 |
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231 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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232 if (ret || !has_sse) |
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233 gCpuCaps.hasSSE=0; |
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234 |
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235 #elif defined(__linux__) |
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236 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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237 struct sigaction saved_sigill; |
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238 struct sigaction saved_sigfpe; |
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239 |
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240 /* Save the original signal handlers. |
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241 */ |
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242 sigaction( SIGILL, NULL, &saved_sigill ); |
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243 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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244 |
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245 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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246 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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247 |
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248 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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249 * supports the extended FPU save and restore required for SSE. If |
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250 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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251 * doesn't support Streaming SIMD Exceptions, even if the processor |
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252 * does. |
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253 */ |
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254 if ( gCpuCaps.hasSSE ) { |
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255 printf( "Testing OS support for SSE... " ); |
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256 |
2272 | 257 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
258 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
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259 |
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260 if ( gCpuCaps.hasSSE ) { |
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261 printf( "yes.\n" ); |
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262 } else { |
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263 printf( "no!\n" ); |
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264 } |
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265 } |
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266 |
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267 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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268 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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269 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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270 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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271 * as expected, we're okay but we need to clean up after it. |
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272 * |
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273 * Are we being too stringent in our requirement that the OS support |
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274 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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275 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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276 * doesn't even support them. We at least know the user-space SSE |
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277 * support is good in kernels that do support unmasked exceptions, |
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278 * and therefore to be safe I'm going to leave this test in here. |
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279 */ |
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280 if ( gCpuCaps.hasSSE ) { |
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281 printf( "Testing OS support for SSE unmasked exceptions... " ); |
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282 |
2272 | 283 // test_os_katmai_exception_support(); |
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284 |
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285 if ( gCpuCaps.hasSSE ) { |
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286 printf( "yes.\n" ); |
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287 } else { |
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288 printf( "no!\n" ); |
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289 } |
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290 } |
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291 |
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292 /* Restore the original signal handlers. |
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293 */ |
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294 sigaction( SIGILL, &saved_sigill, NULL ); |
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295 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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296 |
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297 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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298 * safe to go ahead and hook out the SSE code throughout Mesa. |
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299 */ |
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300 if ( gCpuCaps.hasSSE ) { |
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301 printf( "Tests of OS support for SSE passed.\n" ); |
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302 } else { |
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303 printf( "Tests of OS support for SSE failed!\n" ); |
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304 } |
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305 #else |
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306 /* We can't use POSIX signal handling to test the availability of |
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307 * SSE, so we disable it by default. |
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308 */ |
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309 printf( "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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310 gCpuCaps.hasSSE=0; |
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311 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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312 #else |
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313 /* Do nothing on other platforms for now. |
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314 */ |
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315 message( "Not testing OS support for SSE, leaving disabled.\n" ); |
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316 gCpuCaps.hasSSE=0; |
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317 #endif /* __linux__ */ |
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318 } |
2280 | 319 #endif /* ARCH_X86 */ |