Mercurial > mplayer.hg
annotate vidix/drivers/mach64_vid.c @ 4760:34573271ffb2
meaning of some bits figured out
author | michael |
---|---|
date | Tue, 19 Feb 2002 20:54:58 +0000 |
parents | d681c1b1c193 |
children | bc69f5fc18fe |
rev | line source |
---|---|
4691 | 1 /* |
2 mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips | |
3 Copyrights 2002 Nick Kurshev. This file is based on sources from | |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
4721 | 6 WARNING: THIS DRIVER IS IN BETTA STAGE AND DOESN'T WORK WITH PLANAR FOURCCS! |
4691 | 7 */ |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
13 #include <inttypes.h> | |
14 #include <fcntl.h> | |
15 | |
16 #include "../vidix.h" | |
17 #include "../fourcc.h" | |
18 #include "../../libdha/libdha.h" | |
19 #include "../../libdha/pci_ids.h" | |
20 #include "../../libdha/pci_names.h" | |
21 | |
22 #include "mach64.h" | |
23 | |
24 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ | |
25 | |
26 static void *mach64_mmio_base = 0; | |
27 static void *mach64_mem_base = 0; | |
4721 | 28 static int32_t mach64_overlay_offset = 0; |
4691 | 29 static uint32_t mach64_ram_size = 0; |
30 | |
31 pciinfo_t pci_info; | |
32 static int probed = 0; | |
33 static int __verbose = 0; | |
4721 | 34 |
4758 | 35 #define VERBOSE_LEVEL 1 |
36 | |
4721 | 37 typedef struct bes_registers_s |
38 { | |
39 /* base address of yuv framebuffer */ | |
40 uint32_t yuv_base; | |
41 uint32_t fourcc; | |
42 /* YUV BES registers */ | |
43 uint32_t reg_load_cntl; | |
44 uint32_t scale_inc; | |
45 uint32_t y_x_start; | |
46 uint32_t y_x_end; | |
47 uint32_t vid_buf_pitch; | |
48 uint32_t height_width; | |
49 uint32_t vid_buf0_base_adrs; | |
50 uint32_t vid_buf1_base_adrs; | |
51 uint32_t vid_buf2_base_adrs; | |
52 uint32_t vid_buf3_base_adrs; | |
53 uint32_t vid_buf4_base_adrs; | |
54 uint32_t vid_buf5_base_adrs; | |
55 | |
56 uint32_t scale_cntl; | |
57 uint32_t exclusive_horz; | |
58 uint32_t auto_flip_cntl; | |
59 uint32_t filter_cntl; | |
60 uint32_t key_cntl; | |
61 uint32_t test; | |
62 /* Configurable stuff */ | |
63 int double_buff; | |
64 | |
65 int brightness; | |
66 int saturation; | |
67 | |
68 int ckey_on; | |
69 uint32_t graphics_key_clr; | |
70 uint32_t graphics_key_msk; | |
71 | |
72 int deinterlace_on; | |
73 uint32_t deinterlace_pattern; | |
74 | |
75 } bes_registers_t; | |
76 | |
77 static bes_registers_t besr; | |
78 | |
79 typedef struct video_registers_s | |
80 { | |
81 const char * sname; | |
82 uint32_t name; | |
83 uint32_t value; | |
84 }video_registers_t; | |
85 | |
86 static bes_registers_t besr; | |
87 #define DECLARE_VREG(name) { #name, name, 0 } | |
88 static video_registers_t vregs[] = | |
89 { | |
90 DECLARE_VREG(OVERLAY_SCALE_INC), | |
91 DECLARE_VREG(OVERLAY_Y_X_START), | |
92 DECLARE_VREG(OVERLAY_Y_X_END), | |
93 DECLARE_VREG(OVERLAY_SCALE_CNTL), | |
94 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), | |
95 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), | |
96 DECLARE_VREG(OVERLAY_TEST), | |
97 DECLARE_VREG(SCALER_BUF_PITCH), | |
98 DECLARE_VREG(SCALER_HEIGHT_WIDTH), | |
99 DECLARE_VREG(SCALER_BUF0_OFFSET), | |
100 DECLARE_VREG(SCALER_BUF0_OFFSET_U), | |
101 DECLARE_VREG(SCALER_BUF0_OFFSET_V), | |
102 DECLARE_VREG(SCALER_BUF1_OFFSET), | |
103 DECLARE_VREG(SCALER_BUF1_OFFSET_U), | |
104 DECLARE_VREG(SCALER_BUF1_OFFSET_V), | |
105 DECLARE_VREG(SCALER_H_COEFF0), | |
106 DECLARE_VREG(SCALER_H_COEFF1), | |
107 DECLARE_VREG(SCALER_H_COEFF2), | |
108 DECLARE_VREG(SCALER_H_COEFF3), | |
109 DECLARE_VREG(SCALER_H_COEFF4), | |
110 DECLARE_VREG(SCALER_COLOUR_CNTL), | |
111 DECLARE_VREG(SCALER_THRESHOLD), | |
112 DECLARE_VREG(VIDEO_FORMAT), | |
113 DECLARE_VREG(VIDEO_CONFIG), | |
114 DECLARE_VREG(VIDEO_SYNC_TEST), | |
115 DECLARE_VREG(VIDEO_SYNC_TEST_B) | |
116 }; | |
117 | |
4691 | 118 /* VIDIX exports */ |
119 | |
120 /* MMIO space*/ | |
121 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
122 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
123 | |
4721 | 124 #define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) |
125 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) | |
126 #define INREG(addr) GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) | |
127 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) | |
4691 | 128 |
129 #define OUTREGP(addr,val,mask) \ | |
130 do { \ | |
131 unsigned int _tmp = INREG(addr); \ | |
132 _tmp &= (mask); \ | |
133 _tmp |= (val); \ | |
134 OUTREG(addr, _tmp); \ | |
135 } while (0) | |
136 | |
137 static __inline__ uint32_t INPLL(uint32_t addr) | |
138 { | |
4721 | 139 uint32_t res; |
140 | |
141 /* write addr byte */ | |
142 OUTREG8(CLOCK_CNTL + 1, (addr << 2)); | |
143 /* read the register value */ | |
144 res = INREG(CLOCK_CNTL + 2); | |
145 return res; | |
4691 | 146 } |
147 | |
4721 | 148 static __inline__ void OUTPLL(uint32_t addr,uint32_t val) |
149 { | |
150 /* write addr byte */ | |
151 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); | |
152 /* write the register value */ | |
153 OUTREG(CLOCK_CNTL + 2, val); | |
154 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); | |
155 } | |
156 | |
4691 | 157 #define OUTPLLP(addr,val,mask) \ |
158 do { \ | |
159 unsigned int _tmp = INPLL(addr); \ | |
160 _tmp &= (mask); \ | |
161 _tmp |= (val); \ | |
162 OUTPLL(addr, _tmp); \ | |
163 } while (0) | |
164 | |
4721 | 165 static void mach64_fifo_wait(unsigned n) |
166 { | |
167 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); | |
168 } | |
169 | |
170 static void mach64_wait_for_idle( void ) | |
171 { | |
172 mach64_fifo_wait(16); | |
173 while ((INREG(GUI_STAT) & 1)!= 0); | |
174 } | |
175 | |
4691 | 176 static vidix_capability_t mach64_cap = |
177 { | |
178 "BES driver for Mach64/3DRage cards", | |
179 "Nick Kurshev", | |
180 TYPE_OUTPUT, | |
181 { 0, 0, 0, 0 }, | |
182 2048, | |
183 2048, | |
184 4, | |
185 4, | |
186 -1, | |
187 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
188 VENDOR_ATI, | |
189 -1, | |
190 { 0, 0, 0, 0 } | |
191 }; | |
192 | |
4721 | 193 static uint32_t mach64_vid_get_dbpp( void ) |
194 { | |
195 uint32_t dbpp,retval; | |
196 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; | |
197 switch(dbpp) | |
198 { | |
199 case 1: retval = 4; break; | |
200 case 2: retval = 8; break; | |
201 case 3: retval = 15; break; | |
202 case 4: retval = 16; break; | |
203 case 5: retval = 24; break; | |
204 default: retval=32; break; | |
205 } | |
206 return retval; | |
207 } | |
208 | |
209 static int mach64_is_dbl_scan( void ) | |
210 { | |
211 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; | |
212 } | |
213 | |
214 static int mach64_is_interlace( void ) | |
215 { | |
216 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; | |
217 } | |
218 | |
219 static uint32_t mach64_get_xres( void ) | |
220 { | |
221 /* FIXME: currently we extract that from CRTC!!!*/ | |
222 uint32_t xres,h_total; | |
223 h_total = INREG(CRTC_H_TOTAL_DISP); | |
224 xres = (h_total >> 16) & 0xffff; | |
225 return (xres + 1)*8; | |
226 } | |
227 | |
228 static uint32_t mach64_get_yres( void ) | |
229 { | |
230 /* FIXME: currently we extract that from CRTC!!!*/ | |
231 uint32_t yres,v_total; | |
232 v_total = INREG(CRTC_V_TOTAL_DISP); | |
233 yres = (v_total >> 16) & 0xffff; | |
234 return yres + 1; | |
235 } | |
236 | |
237 static void mach64_vid_make_default() | |
238 { | |
239 mach64_fifo_wait(2); | |
240 OUTREG(SCALER_COLOUR_CNTL,0x0010103f); | |
241 } | |
242 | |
243 static void mach64_vid_dump_regs( void ) | |
244 { | |
245 size_t i; | |
246 printf("[mach64] *** Begin of DRIVER variables dump ***\n"); | |
247 printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); | |
248 printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); | |
249 printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); | |
250 printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); | |
251 printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); | |
252 printf("[mach64] *** Begin of OV0 registers dump ***\n"); | |
253 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
254 { | |
255 mach64_wait_for_idle(); | |
256 printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
257 } | |
258 printf("[mach64] *** End of OV0 registers dump ***\n"); | |
259 } | |
260 | |
261 | |
4691 | 262 unsigned int vixGetVersion(void) |
263 { | |
264 return(VIDIX_VERSION); | |
265 } | |
266 | |
267 static unsigned short ati_card_ids[] = | |
268 { | |
269 DEVICE_ATI_215CT_MACH64_CT, | |
270 DEVICE_ATI_210888CX_MACH64_CX, | |
271 DEVICE_ATI_210888ET_MACH64_ET, | |
272 DEVICE_ATI_MACH64_VT, | |
273 DEVICE_ATI_210888GX_MACH64_GX, | |
274 DEVICE_ATI_264LT_MACH64_LT, | |
275 DEVICE_ATI_264VT_MACH64_VT, | |
276 DEVICE_ATI_264VT3_MACH64_VT3, | |
277 DEVICE_ATI_264VT4_MACH64_VT4, | |
278 /**/ | |
279 DEVICE_ATI_3D_RAGE_PRO, | |
280 DEVICE_ATI_3D_RAGE_PRO2, | |
281 DEVICE_ATI_3D_RAGE_PRO3, | |
282 DEVICE_ATI_3D_RAGE_PRO4, | |
283 DEVICE_ATI_RAGE_XC, | |
284 DEVICE_ATI_RAGE_XL_AGP, | |
285 DEVICE_ATI_RAGE_XC_AGP, | |
286 DEVICE_ATI_RAGE_XL, | |
287 DEVICE_ATI_3D_RAGE_PRO5, | |
288 DEVICE_ATI_3D_RAGE_PRO6, | |
289 DEVICE_ATI_RAGE_XL2, | |
290 DEVICE_ATI_RAGE_XC2, | |
291 DEVICE_ATI_3D_RAGE_I_II, | |
292 DEVICE_ATI_3D_RAGE_II, | |
293 DEVICE_ATI_3D_RAGE_IIC, | |
294 DEVICE_ATI_3D_RAGE_IIC2, | |
295 DEVICE_ATI_3D_RAGE_IIC3, | |
296 DEVICE_ATI_3D_RAGE_IIC4, | |
297 DEVICE_ATI_3D_RAGE_LT, | |
298 DEVICE_ATI_3D_RAGE_LT2, | |
299 DEVICE_ATI_RAGE_MOBILITY_M3, | |
300 DEVICE_ATI_RAGE_MOBILITY_M32, | |
301 DEVICE_ATI_3D_RAGE_LT_G, | |
302 DEVICE_ATI_3D_RAGE_LT3, | |
303 DEVICE_ATI_RAGE_MOBILITY_P_M, | |
304 DEVICE_ATI_RAGE_MOBILITY_L, | |
305 DEVICE_ATI_3D_RAGE_LT4, | |
306 DEVICE_ATI_3D_RAGE_LT5, | |
307 DEVICE_ATI_RAGE_MOBILITY_P_M2, | |
308 DEVICE_ATI_RAGE_MOBILITY_L2 | |
309 }; | |
310 | |
311 static int find_chip(unsigned chip_id) | |
312 { | |
313 unsigned i; | |
314 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) | |
315 { | |
316 if(chip_id == ati_card_ids[i]) return i; | |
317 } | |
318 return -1; | |
319 } | |
320 | |
321 int vixProbe(int verbose,int force) | |
322 { | |
323 pciinfo_t lst[MAX_PCI_DEVICES]; | |
324 unsigned i,num_pci; | |
325 int err; | |
326 __verbose = verbose; | |
327 err = pci_scan(lst,&num_pci); | |
328 if(err) | |
329 { | |
330 printf("[mach64] Error occured during pci scan: %s\n",strerror(err)); | |
331 return err; | |
332 } | |
333 else | |
334 { | |
335 err = ENXIO; | |
336 for(i=0;i<num_pci;i++) | |
337 { | |
338 if(lst[i].vendor == VENDOR_ATI) | |
339 { | |
340 int idx; | |
341 const char *dname; | |
342 idx = find_chip(lst[i].device); | |
343 if(idx == -1 && force == PROBE_NORMAL) continue; | |
344 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
345 dname = dname ? dname : "Unknown chip"; | |
346 printf("[mach64] Found chip: %s\n",dname); | |
347 if(force > PROBE_NORMAL) | |
348 { | |
349 printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
350 if(idx == -1) | |
351 printf("[mach64] Assuming it as Mach64\n"); | |
352 } | |
353 mach64_cap.device_id = lst[i].device; | |
354 err = 0; | |
355 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
356 probed=1; | |
357 break; | |
358 } | |
359 } | |
360 } | |
361 if(err && verbose) printf("[mach64] Can't find chip\n"); | |
362 return err; | |
363 } | |
364 | |
4721 | 365 static void reset_regs( void ) |
366 { | |
367 size_t i; | |
368 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
369 { | |
370 mach64_fifo_wait(2); | |
4758 | 371 OUTREG(vregs[i].name,0); |
4721 | 372 } |
373 } | |
374 | |
375 | |
4691 | 376 int vixInit(void) |
377 { | |
378 int err; | |
379 if(!probed) | |
380 { | |
381 printf("[mach64] Driver was not probed but is being initializing\n"); | |
382 return EINTR; | |
383 } | |
4721 | 384 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; |
385 mach64_wait_for_idle(); | |
4691 | 386 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; |
387 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; | |
388 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; | |
389 else mach64_ram_size = (mach64_ram_size - 7) * 2048; | |
390 mach64_ram_size *= 0x400; /* KB -> bytes */ | |
391 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; | |
4758 | 392 memset(&besr,0,sizeof(bes_registers_t)); |
4721 | 393 mach64_vid_make_default(); |
4691 | 394 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); |
395 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); | |
396 if(!err) printf("[mach64] Set write-combining type of video memory\n"); | |
4721 | 397 reset_regs(); |
4758 | 398 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4691 | 399 return 0; |
400 } | |
401 | |
402 void vixDestroy(void) | |
403 { | |
404 unmap_phys_mem(mach64_mem_base,mach64_ram_size); | |
4721 | 405 unmap_phys_mem(mach64_mmio_base,0x4000); |
4691 | 406 } |
407 | |
408 int vixGetCapability(vidix_capability_t *to) | |
409 { | |
410 memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); | |
411 return 0; | |
412 } | |
413 | |
4721 | 414 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
415 { | |
416 unsigned pitch,spy,spv,spu; | |
417 spy = spv = spu = 0; | |
418 switch(spitch->y) | |
419 { | |
420 case 16: | |
421 case 32: | |
422 case 64: | |
423 case 128: | |
424 case 256: spy = spitch->y; break; | |
425 default: break; | |
426 } | |
427 switch(spitch->u) | |
428 { | |
429 case 16: | |
430 case 32: | |
431 case 64: | |
432 case 128: | |
433 case 256: spu = spitch->u; break; | |
434 default: break; | |
435 } | |
436 switch(spitch->v) | |
437 { | |
438 case 16: | |
439 case 32: | |
440 case 64: | |
441 case 128: | |
442 case 256: spv = spitch->v; break; | |
443 default: break; | |
444 } | |
445 switch(fourcc) | |
446 { | |
447 /* 4:2:0 */ | |
448 case IMGFMT_IYUV: | |
449 case IMGFMT_YV12: | |
450 case IMGFMT_I420: | |
451 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
452 else pitch = 32; | |
453 break; | |
454 default: | |
4722
39f3bfae472c
Direct rendering with dshow codecs support. (Was untested but should work)
nick
parents:
4721
diff
changeset
|
455 if(spy >= 16) pitch = spy; |
39f3bfae472c
Direct rendering with dshow codecs support. (Was untested but should work)
nick
parents:
4721
diff
changeset
|
456 else pitch = 16; |
4721 | 457 break; |
458 } | |
459 return pitch; | |
460 } | |
461 | |
462 static void mach64_compute_framesize(vidix_playback_t *info) | |
463 { | |
464 unsigned pitch,awidth; | |
465 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); | |
466 switch(info->fourcc) | |
467 { | |
468 case IMGFMT_I420: | |
469 case IMGFMT_YV12: | |
470 case IMGFMT_IYUV: | |
471 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
472 info->frame_size = awidth*(info->src.h+info->src.h/2); | |
473 break; | |
474 case IMGFMT_RGB32: | |
475 case IMGFMT_BGR32: | |
476 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); | |
477 info->frame_size = (awidth*info->src.h); | |
478 break; | |
479 /* YUY2 YVYU, RGB15, RGB16 */ | |
480 default: | |
481 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
482 info->frame_size = (awidth*info->src.h); | |
483 break; | |
484 } | |
485 } | |
486 | |
487 static void mach64_vid_stop_video( void ) | |
488 { | |
489 mach64_fifo_wait(14); | |
490 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); | |
491 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); | |
492 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); | |
493 OUTREG(SCALER_H_COEFF0, 0x00002000); | |
494 OUTREG(SCALER_H_COEFF1, 0x0D06200D); | |
495 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); | |
496 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); | |
497 OUTREG(SCALER_H_COEFF4, 0x0C14140C); | |
498 OUTREG(VIDEO_FORMAT, 0xB000B); | |
499 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, 0); | |
500 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, 0); | |
501 OUTREG(OVERLAY_KEY_CNTL, 0x50); | |
502 OUTREG(OVERLAY_TEST, 0x0); | |
503 } | |
504 | |
505 static void mach64_vid_display_video( void ) | |
506 { | |
507 uint32_t vf; | |
508 mach64_fifo_wait(14); | |
509 | |
510 OUTREG(OVERLAY_Y_X_START, besr.y_x_start); | |
511 OUTREG(OVERLAY_Y_X_END, besr.y_x_end); | |
512 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); | |
513 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); | |
514 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); | |
515 OUTREG(SCALER_BUF0_OFFSET, besr.vid_buf0_base_adrs); | |
516 OUTREG(SCALER_BUF0_OFFSET_U, besr.vid_buf1_base_adrs); | |
517 OUTREG(SCALER_BUF0_OFFSET_V, besr.vid_buf2_base_adrs); | |
518 OUTREG(SCALER_BUF1_OFFSET, besr.vid_buf3_base_adrs); | |
519 OUTREG(SCALER_BUF1_OFFSET_U, besr.vid_buf4_base_adrs); | |
520 OUTREG(SCALER_BUF1_OFFSET_V, besr.vid_buf5_base_adrs); | |
4758 | 521 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); |
4760 | 522 // OVERLAY_SCALE_CNTL bits & what they seem to affect |
523 // bit 0 no effect | |
524 // bit 1 yuv2rgb coeff related | |
525 // bit 2 horizontal interpolation if 0 | |
526 // bit 3 vertical interpolation if 0 | |
527 // bit 4 chroma related | |
528 // bit 5-6 gamma correction | |
529 // bit 7 nothing visible if set | |
530 // bit 8-27 no effect | |
531 // bit 28-31 nothing interresting just crashed my system when i played with them :( | |
532 | |
4721 | 533 mach64_wait_for_idle(); |
534 vf = INREG(VIDEO_FORMAT); | |
4751 | 535 |
536 // Bits 16-19 seem to select the format | |
4760 | 537 // Bit 28 seems to toggle something affects luma & chroma |
4751 | 538 // the remaining bits seem to have no effect |
539 | |
4721 | 540 switch(besr.fourcc) |
541 { | |
542 /* 4:2:0 */ | |
543 case IMGFMT_IYUV: | |
544 case IMGFMT_I420: | |
4751 | 545 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xA0000); break; |
4721 | 546 /* 4:2:2 */ |
547 case IMGFMT_YVYU: | |
4758 | 548 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xC0000); break; |
4721 | 549 case IMGFMT_YUY2: |
4751 | 550 default: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xB0000); break; |
4721 | 551 } |
4758 | 552 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 553 } |
554 | |
555 static int mach64_vid_init_video( vidix_playback_t *config ) | |
556 { | |
4758 | 557 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; |
4721 | 558 int is_420,best_pitch,mpitch; |
559 mach64_vid_stop_video(); | |
560 left = config->src.x << 16; | |
561 top = config->src.y << 16; | |
562 src_h = config->src.h; | |
563 src_w = config->src.w; | |
564 is_420 = 0; | |
565 if(config->fourcc == IMGFMT_YV12 || | |
566 config->fourcc == IMGFMT_I420 || | |
567 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
568 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); | |
569 mpitch = best_pitch-1; | |
570 switch(config->fourcc) | |
571 { | |
572 /* 4:2:0 */ | |
573 case IMGFMT_IYUV: | |
574 case IMGFMT_YV12: | |
575 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; | |
576 config->dest.pitch.y = | |
577 config->dest.pitch.u = | |
578 config->dest.pitch.v = best_pitch; | |
579 break; | |
580 /* RGB 4:4:4:4 */ | |
581 case IMGFMT_RGB32: | |
582 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
583 config->dest.pitch.y = | |
584 config->dest.pitch.u = | |
585 config->dest.pitch.v = best_pitch; | |
586 break; | |
587 /* 4:2:2 */ | |
588 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ | |
589 pitch = ((src_w*2) + mpitch) & ~mpitch; | |
590 config->dest.pitch.y = | |
591 config->dest.pitch.u = | |
592 config->dest.pitch.v = best_pitch; | |
593 break; | |
594 } | |
595 dest_w = config->dest.w; | |
596 dest_h = config->dest.h; | |
597 besr.fourcc = config->fourcc; | |
598 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; | |
599 v_inc = (src_h << (12 | |
600 +(mach64_is_interlace()?1:0) | |
601 -(mach64_is_dbl_scan()?1:0) | |
4759 | 602 // +(is_420?1:0) |
4721 | 603 )) / dest_h; |
604 h_inc = (src_w << (12+ecp)) / dest_w; | |
605 /* keep everything in 16.16 */ | |
606 config->offsets[0] = 0; | |
607 config->offsets[1] = config->frame_size; | |
608 if(is_420) | |
609 { | |
610 uint32_t d1line,d2line,d3line; | |
611 d1line = top*pitch; | |
612 d2line = src_h*pitch+(d1line>>2); | |
613 d3line = d2line+((src_h*pitch)>>2); | |
614 d1line += (left >> 16) & ~15; | |
615 d2line += (left >> 17) & ~15; | |
616 d3line += (left >> 17) & ~15; | |
617 config->offset.y = d1line & ~15; | |
618 config->offset.v = d2line & ~15; | |
619 config->offset.u = d3line & ~15; | |
620 besr.vid_buf0_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.y)&~15); | |
621 besr.vid_buf1_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.v)&~15); | |
622 besr.vid_buf2_base_adrs=((mach64_overlay_offset+config->offsets[0]+config->offset.u)&~15); | |
623 besr.vid_buf3_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.y)&~15); | |
624 besr.vid_buf4_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.v)&~15); | |
625 besr.vid_buf5_base_adrs=((mach64_overlay_offset+config->offsets[1]+config->offset.u)&~15); | |
626 config->offset.y = ((besr.vid_buf0_base_adrs)&~15) - mach64_overlay_offset; | |
627 config->offset.v = ((besr.vid_buf1_base_adrs)&~15) - mach64_overlay_offset; | |
628 config->offset.u = ((besr.vid_buf2_base_adrs)&~15) - mach64_overlay_offset; | |
629 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
630 { | |
631 uint32_t tmp; | |
632 tmp = config->offset.u; | |
633 config->offset.u = config->offset.v; | |
634 config->offset.v = tmp; | |
635 } | |
636 } | |
637 else | |
638 { | |
639 besr.vid_buf0_base_adrs = mach64_overlay_offset; | |
640 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&~15; | |
641 besr.vid_buf0_base_adrs += config->offset.y; | |
642 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; | |
643 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; | |
644 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
645 besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
646 besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; | |
647 } | |
648 | |
649 leftUV = (left >> 17) & 15; | |
650 left = (left >> 16) & 15; | |
651 besr.scale_inc = ( h_inc << 16 ) | v_inc; | |
4758 | 652 y_pos = config->dest.y; |
653 if(mach64_is_dbl_scan()) y_pos*=2; | |
654 else | |
655 if(mach64_is_interlace()) y_pos/=2; | |
656 besr.y_x_start = y_pos | (config->dest.x << 16); | |
657 y_pos =config->dest.y + dest_h; | |
658 if(mach64_is_dbl_scan()) y_pos*=2; | |
659 else | |
660 if(mach64_is_interlace()) y_pos/=2; | |
661 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); | |
4721 | 662 besr.height_width = ((src_w - left)<<16) | (src_h - top); |
4759 | 663 besr.vid_buf_pitch = is_420 ? pitch : pitch/2; |
4721 | 664 return 0; |
665 } | |
666 | |
667 | |
668 uint32_t supported_fourcc[] = | |
669 { | |
670 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, | |
671 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU | |
672 }; | |
673 | |
674 __inline__ static int is_supported_fourcc(uint32_t fourcc) | |
675 { | |
676 unsigned i; | |
677 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) | |
678 { | |
679 if(fourcc==supported_fourcc[i]) return 1; | |
680 } | |
681 return 0; | |
682 } | |
683 | |
4691 | 684 int vixQueryFourcc(vidix_fourcc_t *to) |
685 { | |
4721 | 686 if(is_supported_fourcc(to->fourcc)) |
687 { | |
688 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
689 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
690 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
691 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
692 VID_DEPTH_32BPP; | |
693 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK; | |
694 return 0; | |
695 } | |
696 else to->depth = to->flags = 0; | |
4691 | 697 return ENOSYS; |
698 } | |
699 | |
700 int vixConfigPlayback(vidix_playback_t *info) | |
701 { | |
4721 | 702 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
703 if(info->num_frames>2) info->num_frames=2; | |
704 if(info->num_frames==1) besr.double_buff=0; | |
705 else besr.double_buff=1; | |
706 mach64_compute_framesize(info); | |
707 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; | |
708 mach64_overlay_offset &= 0xffff0000; | |
709 if(mach64_overlay_offset < 0) return EINVAL; | |
710 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; | |
711 mach64_vid_init_video(info); | |
712 return 0; | |
4691 | 713 } |
714 | |
715 int vixPlaybackOn(void) | |
716 { | |
4721 | 717 mach64_vid_display_video(); |
718 return 0; | |
4691 | 719 } |
720 | |
721 int vixPlaybackOff(void) | |
722 { | |
4721 | 723 mach64_vid_stop_video(); |
724 return 0; | |
725 } | |
726 | |
727 static void mach64_wait_vsync( void ) | |
728 { | |
729 #warning MACH64 VSYNC WAS NOT IMPLEMENTED!!! | |
4691 | 730 } |
731 | |
732 int vixPlaybackFrameSelect(unsigned int frame) | |
733 { | |
4721 | 734 uint32_t off[6]; |
735 /* | |
736 buf3-5 always should point onto second buffer for better | |
737 deinterlacing and TV-in | |
738 */ | |
739 if(!besr.double_buff) return 0; | |
740 if((frame%2)) | |
741 { | |
742 off[0] = besr.vid_buf3_base_adrs; | |
743 off[1] = besr.vid_buf4_base_adrs; | |
744 off[2] = besr.vid_buf5_base_adrs; | |
745 off[3] = besr.vid_buf0_base_adrs; | |
746 off[4] = besr.vid_buf1_base_adrs; | |
747 off[5] = besr.vid_buf2_base_adrs; | |
748 } | |
749 else | |
750 { | |
751 off[0] = besr.vid_buf0_base_adrs; | |
752 off[1] = besr.vid_buf1_base_adrs; | |
753 off[2] = besr.vid_buf2_base_adrs; | |
754 off[3] = besr.vid_buf3_base_adrs; | |
755 off[4] = besr.vid_buf4_base_adrs; | |
756 off[5] = besr.vid_buf5_base_adrs; | |
757 } | |
758 | |
759 mach64_wait_vsync(); | |
760 mach64_wait_for_idle(); | |
761 mach64_fifo_wait(7); | |
762 OUTREG(SCALER_BUF0_OFFSET, off[0]); | |
763 OUTREG(SCALER_BUF0_OFFSET_U, off[1]); | |
764 OUTREG(SCALER_BUF0_OFFSET_V, off[2]); | |
765 OUTREG(SCALER_BUF1_OFFSET, off[3]); | |
766 OUTREG(SCALER_BUF1_OFFSET_U, off[4]); | |
767 OUTREG(SCALER_BUF1_OFFSET_V, off[5]); | |
4758 | 768 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 769 return 0; |
4691 | 770 } |
4721 | 771 |
772 vidix_video_eq_t equal = | |
773 { | |
774 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | |
775 , | |
776 0, 0, 0, 0, 0, 0, 0, 0 }; | |
777 | |
778 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
779 { | |
780 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
781 return 0; | |
782 } | |
783 | |
784 int vixPlaybackSetEq( const vidix_video_eq_t * eq) | |
785 { | |
786 int br,sat; | |
787 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; | |
788 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; | |
789 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; | |
790 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; | |
791 if(eq->cap & VEQ_CAP_RGB_INTENSITY) | |
792 { | |
793 equal.red_intensity = eq->red_intensity; | |
794 equal.green_intensity = eq->green_intensity; | |
795 equal.blue_intensity = eq->blue_intensity; | |
796 } | |
797 equal.flags = eq->flags; | |
798 br = equal.brightness * 64 / 1000; | |
799 if(br < -64) br = -64; if(br > 63) br = 63; | |
800 sat = (equal.saturation + 1000) * 16 / 1000; | |
801 if(sat < 0) sat = 0; if(sat > 31) sat = 31; | |
802 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
803 return 0; | |
804 } |