1911
|
1 /*
|
|
2 * drivers/video/radeonfb.c
|
|
3 * framebuffer driver for ATI Radeon chipset video boards
|
|
4 *
|
|
5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
|
|
6 *
|
|
7 *
|
|
8 * ChangeLog:
|
|
9 * 2000-08-03 initial version 0.0.1
|
|
10 * 2000-09-10 more bug fixes, public release 0.0.5
|
|
11 * 2001-02-19 mode bug fixes, 0.0.7
|
|
12 * 2001-07-05 fixed scrolling issues, engine initialization,
|
|
13 * and minor mode tweaking, 0.0.9
|
|
14 *
|
1912
|
15 * 2001-09-07 Radeon VE support
|
1913
|
16 * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
|
|
17 * (limitations: on dualhead Radeons (VE, M6, M7)
|
|
18 * driver works only on second head (DVI port).
|
|
19 * TVout is not supported too. M6 & M7 chips
|
|
20 * currently are not supported. Driver has a lot
|
|
21 * of other bugs. Probably they can be solved by
|
|
22 * importing XFree86 code, which has ATI's support).,
|
|
23 * 0.0.11
|
1914
|
24 * 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
|
|
25 * console switching fixes, blanking fixes,
|
|
26 * 0.1.0-ve.0
|
1915
|
27 * 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>),
|
|
28 * Fixed bug of rom bios detection on VE (by NK),
|
|
29 * Minor code cleanup (by NK),
|
|
30 * Enable CRT port on VE (by NK),
|
|
31 * Disable SURFACE_CNTL because mplayer doesn't work
|
|
32 * propertly (by NK)
|
|
33 * 0.1.0-ve.1
|
1911
|
34 *
|
|
35 * Special thanks to ATI DevRel team for their hardware donations.
|
|
36 *
|
1915
|
37 * LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in
|
1916
|
38 * dual monitor configuration. TVout is not supported too.
|
|
39 * Probably these problems can be solved by importing XFree86 code, which
|
|
40 * has ATI's support.
|
1915
|
41 *
|
|
42 * Mini-HOWTO: This driver doesn't accept any options. It only switches your
|
|
43 * video card to graphics mode. Standard way to change video modes and other
|
|
44 * video attributes is using 'fbset' utility.
|
|
45 * Sample:
|
|
46 *
|
|
47 * #!/bin/sh
|
|
48 * fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767
|
|
49 *
|
|
50 */
|
1911
|
51
|
1915
|
52 #define RADEON_VERSION "0.1.0-ve.1"
|
1911
|
53
|
|
54 #include <linux/config.h>
|
|
55 #include <linux/module.h>
|
|
56 #include <linux/kernel.h>
|
|
57 #include <linux/errno.h>
|
|
58 #include <linux/string.h>
|
|
59 #include <linux/mm.h>
|
|
60 #include <linux/tty.h>
|
|
61 #include <linux/malloc.h>
|
|
62 #include <linux/delay.h>
|
|
63 #include <linux/fb.h>
|
|
64 #include <linux/console.h>
|
|
65 #include <linux/selection.h>
|
|
66 #include <linux/ioport.h>
|
|
67 #include <linux/init.h>
|
|
68 #include <linux/pci.h>
|
|
69
|
|
70 #include <asm/io.h>
|
|
71
|
|
72 #include <video/fbcon.h>
|
|
73 #include <video/fbcon-cfb8.h>
|
|
74 #include <video/fbcon-cfb16.h>
|
|
75 #include <video/fbcon-cfb24.h>
|
|
76 #include <video/fbcon-cfb32.h>
|
|
77
|
|
78 #include "radeon.h"
|
|
79
|
|
80
|
|
81 #define DEBUG 0
|
|
82
|
|
83 #if DEBUG
|
|
84 #define RTRACE printk
|
|
85 #else
|
|
86 #define RTRACE if(0) printk
|
|
87 #endif
|
|
88
|
|
89
|
|
90
|
|
91 enum radeon_chips {
|
|
92 RADEON_QD,
|
|
93 RADEON_QE,
|
|
94 RADEON_QF,
|
1912
|
95 RADEON_QG,
|
1913
|
96 RADEON_QY,
|
1915
|
97 RADEON_QZ,
|
|
98 RADEON_LY,
|
|
99 RADEON_LZ,
|
|
100 RADEON_LW
|
|
101 };
|
|
102
|
|
103 enum radeon_montype
|
|
104 {
|
|
105 MT_NONE,
|
|
106 MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
|
|
107 MT_LCD, /* Liquid Crystal Display */
|
|
108 MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
|
|
109 MT_CTV, /* Composite TV out (not in VE) */
|
|
110 MT_STV /* S-Video TV out (probably in VE only) */
|
1911
|
111 };
|
|
112
|
1915
|
113 enum radeon_ddctype
|
|
114 {
|
|
115 DDC_NONE_DETECTED,
|
|
116 DDC_MONID,
|
|
117 DDC_DVI,
|
|
118 DDC_VGA,
|
|
119 DDC_CRT2
|
|
120 };
|
|
121
|
|
122 enum radeon_connectortype
|
|
123 {
|
|
124 CONNECTOR_NONE,
|
|
125 CONNECTOR_PROPRIETARY,
|
|
126 CONNECTOR_CRT,
|
|
127 CONNECTOR_DVI_I,
|
|
128 CONNECTOR_DVI_D
|
|
129 };
|
1911
|
130
|
|
131 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
|
|
132 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
|
|
133 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
|
|
134 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
|
|
135 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
|
1913
|
136 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
|
|
137 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
|
1915
|
138 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
|
|
139 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
|
|
140 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
|
1911
|
141 { 0, }
|
|
142 };
|
|
143 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
|
|
144
|
|
145
|
|
146 typedef struct {
|
|
147 u16 reg;
|
|
148 u32 val;
|
|
149 } reg_val;
|
|
150
|
|
151
|
|
152 /* these common regs are cleared before mode setting so they do not
|
|
153 * interfere with anything
|
|
154 */
|
|
155 reg_val common_regs[] = {
|
|
156 { OVR_CLR, 0 },
|
|
157 { OVR_WID_LEFT_RIGHT, 0 },
|
|
158 { OVR_WID_TOP_BOTTOM, 0 },
|
|
159 { OV0_SCALE_CNTL, 0 },
|
|
160 { SUBPIC_CNTL, 0 },
|
|
161 { VIPH_CONTROL, 0 },
|
|
162 { I2C_CNTL_1, 0 },
|
|
163 { GEN_INT_CNTL, 0 },
|
|
164 { CAP0_TRIG_CNTL, 0 },
|
|
165 };
|
|
166
|
|
167 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
|
|
168
|
|
169 typedef struct {
|
|
170 u8 clock_chip_type;
|
|
171 u8 struct_size;
|
|
172 u8 accelerator_entry;
|
|
173 u8 VGA_entry;
|
|
174 u16 VGA_table_offset;
|
|
175 u16 POST_table_offset;
|
|
176 u16 XCLK;
|
|
177 u16 MCLK;
|
|
178 u8 num_PLL_blocks;
|
|
179 u8 size_PLL_blocks;
|
|
180 u16 PCLK_ref_freq;
|
|
181 u16 PCLK_ref_divider;
|
|
182 u32 PCLK_min_freq;
|
|
183 u32 PCLK_max_freq;
|
|
184 u16 MCLK_ref_freq;
|
|
185 u16 MCLK_ref_divider;
|
|
186 u32 MCLK_min_freq;
|
|
187 u32 MCLK_max_freq;
|
|
188 u16 XCLK_ref_freq;
|
|
189 u16 XCLK_ref_divider;
|
|
190 u32 XCLK_min_freq;
|
|
191 u32 XCLK_max_freq;
|
|
192 } __attribute__ ((packed)) PLL_BLOCK;
|
|
193
|
|
194
|
|
195 struct pll_info {
|
|
196 int ppll_max;
|
|
197 int ppll_min;
|
|
198 int xclk;
|
|
199 int ref_div;
|
|
200 int ref_clk;
|
|
201 };
|
|
202
|
|
203
|
|
204 struct ram_info {
|
|
205 int ml;
|
|
206 int mb;
|
|
207 int trcd;
|
|
208 int trp;
|
|
209 int twr;
|
|
210 int cl;
|
|
211 int tr2w;
|
|
212 int loop_latency;
|
|
213 int rloop;
|
|
214 };
|
|
215
|
|
216
|
|
217 struct radeon_regs {
|
|
218 u32 crtc_h_total_disp;
|
|
219 u32 crtc_h_sync_strt_wid;
|
|
220 u32 crtc_v_total_disp;
|
|
221 u32 crtc_v_sync_strt_wid;
|
|
222 u32 crtc_pitch;
|
|
223 u32 flags;
|
|
224 u32 pix_clock;
|
|
225 int xres, yres;
|
|
226 int bpp;
|
|
227 u32 crtc_gen_cntl;
|
|
228 u32 crtc_ext_cntl;
|
1915
|
229 #if defined(__BIG_ENDIAN)
|
1914
|
230 u32 surface_cntl;
|
1915
|
231 #endif
|
1911
|
232 u32 dac_cntl;
|
|
233 u32 dda_config;
|
|
234 u32 dda_on_off;
|
|
235 u32 ppll_div_3;
|
|
236 u32 ppll_ref_div;
|
|
237 };
|
|
238
|
|
239
|
|
240 struct radeonfb_info {
|
|
241 struct fb_info info;
|
|
242
|
|
243 struct radeon_regs state;
|
|
244 struct radeon_regs init_state;
|
|
245
|
1913
|
246 char name[14];
|
1911
|
247 char ram_type[12];
|
|
248
|
1915
|
249 int hasCRTC2;
|
|
250 int crtDispType;
|
|
251 int dviDispType;
|
|
252 int hasTVout;
|
|
253 int isM7;
|
|
254
|
1911
|
255 u32 mmio_base_phys;
|
|
256 u32 fb_base_phys;
|
|
257
|
|
258 u32 mmio_base;
|
|
259 u32 fb_base;
|
|
260
|
|
261 struct pci_dev *pdev;
|
|
262
|
|
263 struct display disp;
|
|
264 int currcon;
|
|
265 struct display *currcon_display;
|
|
266
|
|
267 struct { u8 red, green, blue, pad; } palette[256];
|
|
268
|
|
269 int chipset;
|
|
270 int video_ram;
|
|
271 u8 rev;
|
|
272 int pitch, bpp, depth;
|
|
273 int xres, yres, pixclock;
|
|
274
|
|
275 u32 dp_gui_master_cntl;
|
|
276
|
|
277 struct pll_info pll;
|
|
278 int pll_output_freq, post_div, fb_div;
|
|
279
|
|
280 struct ram_info ram;
|
|
281
|
1914
|
282 u32 hack_crtc_ext_cntl;
|
|
283 u32 hack_crtc_v_sync_strt_wid;
|
|
284
|
1911
|
285 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
286 union {
|
|
287 #if defined(FBCON_HAS_CFB16)
|
|
288 u_int16_t cfb16[16];
|
|
289 #endif
|
1914
|
290 #if defined(FBCON_HAS_CFB24)
|
|
291 u_int32_t cfb24[16];
|
|
292 #endif
|
1911
|
293 #if defined(FBCON_HAS_CFB32)
|
|
294 u_int32_t cfb32[16];
|
|
295 #endif
|
|
296 } con_cmap;
|
|
297 #endif
|
|
298 };
|
|
299
|
|
300
|
|
301 static struct fb_var_screeninfo radeonfb_default_var = {
|
|
302 640, 480, 640, 480, 0, 0, 8, 0,
|
|
303 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
|
|
304 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
|
|
305 0, FB_VMODE_NONINTERLACED
|
|
306 };
|
|
307
|
|
308
|
|
309 /*
|
|
310 * IO macros
|
|
311 */
|
|
312
|
|
313 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
|
|
314 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
|
|
315 #define INREG(addr) readl((rinfo->mmio_base)+addr)
|
|
316 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
|
|
317
|
|
318 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
|
|
319 OUTREG(CLOCK_CNTL_DATA, val)
|
|
320 #define OUTPLLP(addr,val,mask) \
|
|
321 do { \
|
|
322 unsigned int _tmp = INPLL(addr); \
|
|
323 _tmp &= (mask); \
|
|
324 _tmp |= (val); \
|
|
325 OUTPLL(addr, _tmp); \
|
|
326 } while (0)
|
|
327
|
|
328 #define OUTREGP(addr,val,mask) \
|
|
329 do { \
|
|
330 unsigned int _tmp = INREG(addr); \
|
|
331 _tmp &= (mask); \
|
|
332 _tmp |= (val); \
|
|
333 OUTREG(addr, _tmp); \
|
|
334 } while (0)
|
|
335
|
|
336
|
|
337 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
|
|
338 {
|
|
339 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
|
|
340 return (INREG(CLOCK_CNTL_DATA));
|
|
341 }
|
|
342
|
|
343 #define INPLL(addr) _INPLL(rinfo, addr)
|
|
344
|
|
345
|
|
346 /*
|
|
347 * 2D engine routines
|
|
348 */
|
|
349
|
|
350 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
|
|
351 {
|
|
352 int i;
|
|
353
|
|
354 /* initiate flush */
|
|
355 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
|
|
356 ~RB2D_DC_FLUSH_ALL);
|
|
357
|
|
358 for (i=0; i < 2000000; i++) {
|
|
359 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
|
|
360 break;
|
|
361 }
|
|
362 }
|
|
363
|
|
364
|
|
365 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
|
|
366 {
|
|
367 int i;
|
|
368
|
|
369 for (i=0; i<2000000; i++)
|
|
370 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
|
|
371 return;
|
|
372 }
|
|
373
|
|
374
|
|
375 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
|
|
376 {
|
|
377 int i;
|
|
378
|
|
379 /* ensure FIFO is empty before waiting for idle */
|
|
380 _radeon_fifo_wait (rinfo, 64);
|
|
381
|
|
382 for (i=0; i<2000000; i++) {
|
|
383 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
|
|
384 radeon_engine_flush (rinfo);
|
|
385 return;
|
|
386 }
|
|
387 }
|
|
388 }
|
|
389
|
|
390
|
|
391 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
|
|
392 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
|
|
393
|
|
394
|
|
395
|
|
396 /*
|
|
397 * helper routines
|
|
398 */
|
|
399
|
|
400 static __inline__ u32 radeon_get_dstbpp(u16 depth)
|
|
401 {
|
|
402 switch (depth) {
|
|
403 case 8:
|
|
404 return DST_8BPP;
|
|
405 case 15:
|
|
406 return DST_15BPP;
|
|
407 case 16:
|
|
408 return DST_16BPP;
|
1914
|
409 case 24:
|
|
410 return DST_24BPP;
|
1911
|
411 case 32:
|
|
412 return DST_32BPP;
|
|
413 default:
|
|
414 return 0;
|
|
415 }
|
|
416 }
|
|
417
|
|
418
|
|
419 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
|
|
420 {
|
|
421 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
|
|
422
|
|
423 radeon_engine_flush (rinfo);
|
|
424
|
|
425 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
|
426 mclk_cntl = INPLL(MCLK_CNTL);
|
|
427
|
|
428 OUTPLL(MCLK_CNTL, (mclk_cntl |
|
|
429 FORCEON_MCLKA |
|
|
430 FORCEON_MCLKB |
|
|
431 FORCEON_YCLKA |
|
|
432 FORCEON_YCLKB |
|
|
433 FORCEON_MC |
|
|
434 FORCEON_AIC));
|
|
435 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
|
|
436
|
|
437 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
|
|
438 SOFT_RESET_CP |
|
|
439 SOFT_RESET_HI |
|
|
440 SOFT_RESET_SE |
|
|
441 SOFT_RESET_RE |
|
|
442 SOFT_RESET_PP |
|
|
443 SOFT_RESET_E2 |
|
|
444 SOFT_RESET_RB |
|
|
445 SOFT_RESET_HDP);
|
|
446 INREG(RBBM_SOFT_RESET);
|
|
447 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
|
|
448 ~(SOFT_RESET_CP |
|
|
449 SOFT_RESET_HI |
|
|
450 SOFT_RESET_SE |
|
|
451 SOFT_RESET_RE |
|
|
452 SOFT_RESET_PP |
|
|
453 SOFT_RESET_E2 |
|
|
454 SOFT_RESET_RB |
|
|
455 SOFT_RESET_HDP));
|
|
456 INREG(RBBM_SOFT_RESET);
|
|
457
|
|
458 OUTPLL(MCLK_CNTL, mclk_cntl);
|
|
459 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
|
|
460 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
|
|
461
|
|
462 return;
|
|
463 }
|
|
464
|
|
465 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
|
|
466
|
|
467
|
|
468 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
|
|
469 {
|
|
470 switch (post_div) {
|
|
471 case 1:
|
|
472 return 0x00;
|
|
473 case 2:
|
|
474 return 0x01;
|
|
475 case 3:
|
|
476 return 0x04;
|
|
477 case 4:
|
|
478 return 0x02;
|
|
479 case 6:
|
|
480 return 0x06;
|
|
481 case 8:
|
|
482 return 0x03;
|
|
483 case 12:
|
|
484 return 0x07;
|
|
485 default:
|
|
486 return 0x02;
|
|
487 }
|
|
488 }
|
|
489
|
|
490
|
|
491
|
|
492 static __inline__ int round_div(int num, int den)
|
|
493 {
|
|
494 return (num + (den / 2)) / den;
|
|
495 }
|
|
496
|
|
497
|
|
498
|
|
499 static __inline__ int min_bits_req(int val)
|
|
500 {
|
|
501 int bits_req = 0;
|
|
502
|
|
503 if (val == 0)
|
|
504 bits_req = 1;
|
|
505
|
|
506 while (val) {
|
|
507 val >>= 1;
|
|
508 bits_req++;
|
|
509 }
|
|
510
|
|
511 return (bits_req);
|
|
512 }
|
|
513
|
|
514
|
|
515 static __inline__ int _max(int val1, int val2)
|
|
516 {
|
|
517 if (val1 >= val2)
|
|
518 return val1;
|
|
519 else
|
|
520 return val2;
|
|
521 }
|
|
522
|
|
523
|
|
524
|
|
525 /*
|
|
526 * globals
|
|
527 */
|
|
528
|
|
529 static char fontname[40] __initdata;
|
|
530 static char *mode_option __initdata;
|
|
531 static char noaccel __initdata = 0;
|
|
532
|
1914
|
533 #if 0
|
1911
|
534 #ifdef FBCON_HAS_CFB8
|
|
535 static struct display_switch fbcon_radeon8;
|
|
536 #endif
|
1914
|
537 #endif
|
1911
|
538
|
|
539 /*
|
|
540 * prototypes
|
|
541 */
|
|
542
|
|
543 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
544 struct fb_info *info);
|
|
545 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
546 struct fb_info *info);
|
|
547 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
548 struct fb_info *info);
|
|
549 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
550 struct fb_info *info);
|
|
551 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
552 struct fb_info *info);
|
|
553 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
554 struct fb_info *info);
|
|
555 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
556 unsigned long arg, int con, struct fb_info *info);
|
|
557 static int radeonfb_switch (int con, struct fb_info *info);
|
|
558 static int radeonfb_updatevar (int con, struct fb_info *info);
|
|
559 static void radeonfb_blank (int blank, struct fb_info *info);
|
|
560 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
|
|
561 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
562 unsigned *blue, unsigned *transp,
|
|
563 struct fb_info *info);
|
|
564 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
565 unsigned blue, unsigned transp, struct fb_info *info);
|
1914
|
566 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
|
1911
|
567 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
568 struct radeon_regs *save);
|
|
569 static void radeon_engine_init (struct radeonfb_info *rinfo);
|
|
570 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
571 struct fb_var_screeninfo *mode);
|
|
572 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
573 struct radeon_regs *mode);
|
|
574 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
|
|
575 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
|
|
576 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
|
|
577 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
578 const struct pci_device_id *ent);
|
|
579 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
|
|
580 static char *radeon_find_rom(struct radeonfb_info *rinfo);
|
|
581 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
|
1914
|
582 static void do_install_cmap(int con, struct fb_info *info);
|
|
583 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
584 struct fb_var_screeninfo *var,
|
|
585 struct fb_var_screeninfo *v,
|
|
586 int nom, int den);
|
1911
|
587
|
|
588 static struct fb_ops radeon_fb_ops = {
|
|
589 fb_get_fix: radeonfb_get_fix,
|
|
590 fb_get_var: radeonfb_get_var,
|
|
591 fb_set_var: radeonfb_set_var,
|
|
592 fb_get_cmap: radeonfb_get_cmap,
|
|
593 fb_set_cmap: radeonfb_set_cmap,
|
|
594 fb_pan_display: radeonfb_pan_display,
|
|
595 fb_ioctl: radeonfb_ioctl,
|
|
596 };
|
|
597
|
|
598
|
|
599 static struct pci_driver radeonfb_driver = {
|
|
600 name: "radeonfb",
|
|
601 id_table: radeonfb_pci_table,
|
|
602 probe: radeonfb_pci_register,
|
|
603 remove: radeonfb_pci_unregister,
|
|
604 };
|
|
605
|
|
606
|
|
607 int __init radeonfb_init (void)
|
|
608 {
|
|
609 return pci_module_init (&radeonfb_driver);
|
|
610 }
|
|
611
|
|
612
|
|
613 void __exit radeonfb_exit (void)
|
|
614 {
|
|
615 pci_unregister_driver (&radeonfb_driver);
|
|
616 }
|
|
617
|
|
618
|
|
619 int __init radeonfb_setup (char *options)
|
|
620 {
|
|
621 char *this_opt;
|
|
622
|
|
623 if (!options || !*options)
|
|
624 return 0;
|
|
625
|
|
626 for (this_opt = strtok (options, ","); this_opt;
|
|
627 this_opt = strtok (NULL, ",")) {
|
|
628 if (!strncmp (this_opt, "font:", 5)) {
|
|
629 char *p;
|
|
630 int i;
|
|
631
|
|
632 p = this_opt + 5;
|
|
633 for (i=0; i<sizeof (fontname) - 1; i++)
|
|
634 if (!*p || *p == ' ' || *p == ',')
|
|
635 break;
|
|
636 memcpy(fontname, this_opt + 5, i);
|
|
637 } else if (!strncmp(this_opt, "noaccel", 7)) {
|
|
638 noaccel = 1;
|
|
639 }
|
|
640 else mode_option = this_opt;
|
|
641 }
|
|
642
|
|
643 return 0;
|
|
644 }
|
|
645
|
|
646 #ifdef MODULE
|
|
647 module_init(radeonfb_init);
|
|
648 module_exit(radeonfb_exit);
|
|
649 #endif
|
|
650
|
|
651
|
1915
|
652 MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)");
|
|
653 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION);
|
1911
|
654
|
1915
|
655 static char * GET_MON_NAME(int type)
|
|
656 {
|
|
657 char *pret;
|
|
658 switch(type)
|
|
659 {
|
|
660 case MT_NONE: pret = "no"; break;
|
|
661 case MT_CRT: pret = "CRT"; break;
|
|
662 case MT_DFP: pret = "DFP"; break;
|
|
663 case MT_LCD: pret = "LCD"; break;
|
|
664 case MT_CTV: pret = "CTV"; break;
|
|
665 case MT_STV: pret = "STV"; break;
|
|
666 default: pret = "Unknown";
|
|
667 }
|
|
668 return pret;
|
|
669 }
|
1911
|
670
|
|
671
|
|
672 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
673 const struct pci_device_id *ent)
|
|
674 {
|
|
675 struct radeonfb_info *rinfo;
|
|
676 u32 tmp;
|
|
677 int i, j;
|
|
678 char *bios_seg = NULL;
|
|
679
|
|
680 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
|
|
681 if (!rinfo) {
|
|
682 printk ("radeonfb: could not allocate memory\n");
|
|
683 return -ENODEV;
|
|
684 }
|
|
685
|
|
686 memset (rinfo, 0, sizeof (struct radeonfb_info));
|
|
687
|
|
688 /* enable device */
|
|
689 {
|
|
690 int err;
|
|
691
|
|
692 if ((err = pci_enable_device(pdev))) {
|
|
693 printk("radeonfb: cannot enable device\n");
|
|
694 kfree (rinfo);
|
|
695 return -ENODEV;
|
|
696 }
|
|
697 }
|
|
698
|
|
699 /* set base addrs */
|
|
700 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
|
|
701 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
|
|
702
|
|
703 /* request the mem regions */
|
|
704 if (!request_mem_region (rinfo->fb_base_phys,
|
|
705 pci_resource_len(pdev, 0), "radeonfb")) {
|
|
706 printk ("radeonfb: cannot reserve FB region\n");
|
|
707 kfree (rinfo);
|
|
708 return -ENODEV;
|
|
709 }
|
|
710
|
|
711 if (!request_mem_region (rinfo->mmio_base_phys,
|
|
712 pci_resource_len(pdev, 2), "radeonfb")) {
|
|
713 printk ("radeonfb: cannot reserve MMIO region\n");
|
|
714 release_mem_region (rinfo->fb_base_phys,
|
|
715 pci_resource_len(pdev, 0));
|
|
716 kfree (rinfo);
|
|
717 return -ENODEV;
|
|
718 }
|
|
719
|
|
720 /* map the regions */
|
|
721 rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
|
|
722 RADEON_REGSIZE);
|
|
723 if (!rinfo->mmio_base) {
|
|
724 printk ("radeonfb: cannot map MMIO\n");
|
|
725 release_mem_region (rinfo->mmio_base_phys,
|
|
726 pci_resource_len(pdev, 2));
|
|
727 release_mem_region (rinfo->fb_base_phys,
|
|
728 pci_resource_len(pdev, 0));
|
|
729 kfree (rinfo);
|
|
730 return -ENODEV;
|
|
731 }
|
|
732
|
|
733 /* chipset */
|
|
734 switch (pdev->device) {
|
|
735 case PCI_DEVICE_ID_RADEON_QD:
|
|
736 strcpy(rinfo->name, "Radeon QD ");
|
|
737 break;
|
|
738 case PCI_DEVICE_ID_RADEON_QE:
|
|
739 strcpy(rinfo->name, "Radeon QE ");
|
|
740 break;
|
|
741 case PCI_DEVICE_ID_RADEON_QF:
|
|
742 strcpy(rinfo->name, "Radeon QF ");
|
|
743 break;
|
|
744 case PCI_DEVICE_ID_RADEON_QG:
|
|
745 strcpy(rinfo->name, "Radeon QG ");
|
|
746 break;
|
1913
|
747 case PCI_DEVICE_ID_RADEON_QY:
|
1915
|
748 rinfo->hasCRTC2 = 1;
|
|
749 strcpy(rinfo->name, "Radeon VE QY ");
|
1913
|
750 break;
|
|
751 case PCI_DEVICE_ID_RADEON_QZ:
|
1915
|
752 rinfo->hasCRTC2 = 1;
|
|
753 strcpy(rinfo->name, "Radeon VE QZ ");
|
|
754 break;
|
|
755 case PCI_DEVICE_ID_RADEON_LY:
|
|
756 rinfo->hasCRTC2 = 1;
|
|
757 strcpy(rinfo->name, "Radeon M6 LY ");
|
|
758 break;
|
|
759 case PCI_DEVICE_ID_RADEON_LZ:
|
|
760 rinfo->hasCRTC2 = 1;
|
|
761 strcpy(rinfo->name, "Radeon M6 LZ ");
|
|
762 break;
|
|
763 case PCI_DEVICE_ID_RADEON_LW:
|
|
764 /* Note: Only difference between VE,M6 and M7 is initialization CRTC2
|
|
765 registers in dual monitor configuration!!! */
|
|
766 rinfo->hasCRTC2 = 1;
|
|
767 rinfo->isM7 = 1;
|
|
768 strcpy(rinfo->name, "Radeon M7 LW ");
|
1912
|
769 break;
|
1911
|
770 default:
|
1915
|
771 release_mem_region (rinfo->mmio_base_phys,
|
|
772 pci_resource_len(pdev, 2));
|
|
773 release_mem_region (rinfo->fb_base_phys,
|
|
774 pci_resource_len(pdev, 0));
|
|
775 kfree (rinfo);
|
1911
|
776 return -ENODEV;
|
|
777 }
|
|
778
|
|
779 /* framebuffer size */
|
|
780 tmp = INREG(CONFIG_MEMSIZE);
|
|
781
|
|
782 /* mem size is bits [28:0], mask off the rest */
|
|
783 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
|
784
|
|
785 /* ram type */
|
|
786 tmp = INREG(MEM_SDRAM_MODE_REG);
|
|
787 switch ((MEM_CFG_TYPE & tmp) >> 30) {
|
|
788 case 0:
|
|
789 /* SDR SGRAM (2:1) */
|
|
790 strcpy(rinfo->ram_type, "SDR SGRAM");
|
|
791 rinfo->ram.ml = 4;
|
|
792 rinfo->ram.mb = 4;
|
|
793 rinfo->ram.trcd = 1;
|
|
794 rinfo->ram.trp = 2;
|
|
795 rinfo->ram.twr = 1;
|
|
796 rinfo->ram.cl = 2;
|
|
797 rinfo->ram.loop_latency = 16;
|
|
798 rinfo->ram.rloop = 16;
|
|
799
|
|
800 break;
|
|
801 case 1:
|
|
802 /* DDR SGRAM */
|
|
803 strcpy(rinfo->ram_type, "DDR SGRAM");
|
|
804 rinfo->ram.ml = 4;
|
|
805 rinfo->ram.mb = 4;
|
|
806 rinfo->ram.trcd = 3;
|
|
807 rinfo->ram.trp = 3;
|
|
808 rinfo->ram.twr = 2;
|
|
809 rinfo->ram.cl = 3;
|
|
810 rinfo->ram.tr2w = 1;
|
|
811 rinfo->ram.loop_latency = 16;
|
|
812 rinfo->ram.rloop = 16;
|
|
813
|
|
814 break;
|
|
815 default:
|
|
816 /* 64-bit SDR SGRAM */
|
|
817 strcpy(rinfo->ram_type, "SDR SGRAM 64");
|
|
818 rinfo->ram.ml = 4;
|
|
819 rinfo->ram.mb = 8;
|
|
820 rinfo->ram.trcd = 3;
|
|
821 rinfo->ram.trp = 3;
|
|
822 rinfo->ram.twr = 1;
|
|
823 rinfo->ram.cl = 3;
|
|
824 rinfo->ram.tr2w = 1;
|
|
825 rinfo->ram.loop_latency = 17;
|
|
826 rinfo->ram.rloop = 17;
|
|
827
|
|
828 break;
|
|
829 }
|
|
830
|
|
831 bios_seg = radeon_find_rom(rinfo);
|
|
832 radeon_get_pllinfo(rinfo, bios_seg);
|
|
833
|
|
834 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
|
|
835 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
|
|
836
|
|
837 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
|
838
|
1915
|
839 /*****
|
|
840 VE and M6 have both DVI and CRT ports (for M6 DVI port can be switch to
|
|
841 DFP port). The DVI port can also be conneted to a CRT with an adapter.
|
|
842 Here is the definition of ports for this driver---
|
|
843 (1) If both port are connected, DVI port will be treated as the Primary
|
|
844 port (uses CRTC1) and CRT port will be treated as the Secondary port
|
|
845 (uses CRTC2)
|
|
846 (2) If only one port is connected, it will treated as the Primary port
|
|
847 (??? uses CRTC1 ???)
|
|
848 *****/
|
|
849 if(rinfo->hasCRTC2) {
|
|
850 /* Using BIOS scratch registers works with for VE/M6,
|
|
851 no such registers in regular RADEON!!!*/
|
|
852 tmp = INREG(RADEON_BIOS_4_SCRATCH);
|
|
853 /*check Primary (DVI/DFP port)*/
|
|
854 if(tmp & 0x08) rinfo->dviDispType = MT_DFP;
|
|
855 else if(tmp & 0x04) rinfo->dviDispType = MT_LCD;
|
|
856 else if(tmp & 0x0200) rinfo->dviDispType = MT_CRT;
|
|
857 else if(tmp & 0x10) rinfo->dviDispType = MT_CTV;
|
|
858 else if(tmp & 0x20) rinfo->dviDispType = MT_STV;
|
|
859 /*check Secondary (CRT port).*/
|
|
860 if(tmp & 0x02) rinfo->crtDispType = MT_CRT;
|
|
861 else if(tmp & 0x800) rinfo->crtDispType = MT_DFP;
|
|
862 else if(tmp & 0x400) rinfo->crtDispType = MT_LCD;
|
|
863 else if(tmp & 0x1000) rinfo->crtDispType = MT_CTV;
|
|
864 else if(tmp & 0x2000) rinfo->crtDispType = MT_STV;
|
|
865 if(rinfo->dviDispType == MT_NONE &&
|
|
866 rinfo->crtDispType == MT_NONE) {
|
|
867 printk("radeonfb: No monitor detected!!!\n");
|
|
868 release_mem_region (rinfo->mmio_base_phys,
|
|
869 pci_resource_len(pdev, 2));
|
|
870 release_mem_region (rinfo->fb_base_phys,
|
|
871 pci_resource_len(pdev, 0));
|
|
872 kfree (rinfo);
|
|
873 return -ENODEV;
|
|
874 }
|
|
875 }
|
|
876 else {
|
|
877 /*Regular Radeon ASIC, only one CRTC, but it could be
|
|
878 used for DFP with a DVI output, like AIW board*/
|
|
879 rinfo->dviDispType = MT_NONE;
|
|
880 tmp = INREG(FP_GEN_CNTL);
|
|
881 if(tmp & FP_EN_TMDS) rinfo->crtDispType = MT_DFP;
|
|
882 else rinfo->crtDispType = MT_CRT;
|
|
883 }
|
|
884
|
|
885 if(bios_seg) {
|
|
886 /*
|
|
887 FIXME!!! TVout support currently is incomplete
|
|
888 On Radeon VE TVout is recognized as STV monitor on DVI port.
|
|
889 */
|
|
890 char * bios_ptr = bios_seg + 0x48L;
|
|
891 rinfo->hasTVout = readw(bios_ptr+0x32);
|
|
892 }
|
|
893
|
1911
|
894 rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
|
895 rinfo->video_ram);
|
|
896 if (!rinfo->fb_base) {
|
|
897 printk ("radeonfb: cannot map FB\n");
|
|
898 iounmap ((void*)rinfo->mmio_base);
|
|
899 release_mem_region (rinfo->mmio_base_phys,
|
|
900 pci_resource_len(pdev, 2));
|
|
901 release_mem_region (rinfo->fb_base_phys,
|
|
902 pci_resource_len(pdev, 0));
|
|
903 kfree (rinfo);
|
|
904 return -ENODEV;
|
|
905 }
|
|
906
|
|
907 /* XXX turn off accel for now, blts aren't working right */
|
|
908 noaccel = 1;
|
|
909
|
|
910 /* set all the vital stuff */
|
|
911 radeon_set_fbinfo (rinfo);
|
|
912
|
|
913 /* save current mode regs before we switch into the new one
|
|
914 * so we can restore this upon __exit
|
|
915 */
|
|
916 radeon_save_state (rinfo, &rinfo->init_state);
|
|
917
|
|
918 /* init palette */
|
|
919 for (i=0; i<16; i++) {
|
|
920 j = color_table[i];
|
|
921 rinfo->palette[i].red = default_red[j];
|
|
922 rinfo->palette[i].green = default_grn[j];
|
|
923 rinfo->palette[i].blue = default_blu[j];
|
|
924 }
|
|
925
|
|
926 pdev->driver_data = rinfo;
|
|
927
|
|
928 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
|
|
929 printk ("radeonfb: could not register framebuffer\n");
|
|
930 iounmap ((void*)rinfo->fb_base);
|
|
931 iounmap ((void*)rinfo->mmio_base);
|
|
932 release_mem_region (rinfo->mmio_base_phys,
|
|
933 pci_resource_len(pdev, 2));
|
|
934 release_mem_region (rinfo->fb_base_phys,
|
|
935 pci_resource_len(pdev, 0));
|
|
936 kfree (rinfo);
|
|
937 return -ENODEV;
|
|
938 }
|
|
939
|
|
940 if (!noaccel) {
|
|
941 /* initialize the engine */
|
|
942 radeon_engine_init (rinfo);
|
|
943 }
|
|
944
|
1915
|
945 printk ("radeonfb: ATI %s %s %d MB\n",rinfo->name,rinfo->ram_type,
|
1911
|
946 (rinfo->video_ram/(1024*1024)));
|
1915
|
947 if(rinfo->hasCRTC2) {
|
|
948 printk("radeonfb: DVI port has %s monitor connected\n",GET_MON_NAME(rinfo->dviDispType));
|
|
949 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
950 }
|
|
951 else
|
|
952 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
953 printk("radeonfb: This card has %sTVout\n",rinfo->hasTVout ? "" : "no ");
|
1911
|
954
|
|
955 return 0;
|
|
956 }
|
|
957
|
|
958
|
|
959
|
|
960 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
|
|
961 {
|
|
962 struct radeonfb_info *rinfo = pdev->driver_data;
|
|
963
|
|
964 if (!rinfo)
|
|
965 return;
|
|
966
|
|
967 /* restore original state */
|
|
968 radeon_write_mode (rinfo, &rinfo->init_state);
|
|
969
|
|
970 unregister_framebuffer ((struct fb_info *) rinfo);
|
|
971
|
|
972 iounmap ((void*)rinfo->mmio_base);
|
|
973 iounmap ((void*)rinfo->fb_base);
|
|
974
|
|
975 release_mem_region (rinfo->mmio_base_phys,
|
|
976 pci_resource_len(pdev, 2));
|
|
977 release_mem_region (rinfo->fb_base_phys,
|
|
978 pci_resource_len(pdev, 0));
|
|
979
|
|
980 kfree (rinfo);
|
|
981 }
|
|
982
|
|
983
|
|
984
|
|
985 static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
|
986 {
|
1914
|
987 #if defined(__i386__)
|
1911
|
988 u32 segstart;
|
|
989 char *rom_base;
|
|
990 char *rom;
|
|
991 int stage;
|
1915
|
992 int i,j;
|
1911
|
993 char aty_rom_sig[] = "761295520";
|
1915
|
994 char *radeon_sig[] = {
|
|
995 "RG6",
|
|
996 "RADEON"
|
|
997 };
|
1911
|
998
|
|
999 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
|
1000 stage = 1;
|
|
1001
|
|
1002 rom_base = (char *)ioremap(segstart, 0x1000);
|
|
1003
|
|
1004 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
|
|
1005 stage = 2;
|
|
1006
|
|
1007
|
|
1008 if (stage != 2) {
|
|
1009 iounmap(rom_base);
|
|
1010 continue;
|
|
1011 }
|
|
1012
|
|
1013 rom = rom_base;
|
|
1014
|
|
1015 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
|
|
1016 if (aty_rom_sig[0] == *rom)
|
|
1017 if (strncmp(aty_rom_sig, rom,
|
|
1018 strlen(aty_rom_sig)) == 0)
|
|
1019 stage = 3;
|
|
1020 rom++;
|
|
1021 }
|
|
1022 if (stage != 3) {
|
|
1023 iounmap(rom_base);
|
|
1024 continue;
|
|
1025 }
|
|
1026 rom = rom_base;
|
|
1027
|
|
1028 for (i = 0; (i < 512) && (stage != 4); i++) {
|
1915
|
1029 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
|
|
1030 if (radeon_sig[j][0] == *rom)
|
|
1031 if (strncmp(radeon_sig[j], rom,
|
|
1032 strlen(radeon_sig[j])) == 0) {
|
|
1033 stage = 4;
|
|
1034 break;
|
|
1035 }
|
|
1036 }
|
1911
|
1037 rom++;
|
|
1038 }
|
|
1039 if (stage != 4) {
|
|
1040 iounmap(rom_base);
|
|
1041 continue;
|
|
1042 }
|
|
1043
|
|
1044 return rom_base;
|
|
1045 }
|
|
1046 #endif
|
|
1047 return NULL;
|
|
1048 }
|
|
1049
|
|
1050
|
|
1051
|
|
1052 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
|
|
1053 {
|
|
1054 void *bios_header;
|
|
1055 void *header_ptr;
|
|
1056 u16 bios_header_offset, pll_info_offset;
|
|
1057 PLL_BLOCK pll;
|
|
1058
|
|
1059 if (bios_seg) {
|
|
1060 bios_header = bios_seg + 0x48L;
|
|
1061 header_ptr = bios_header;
|
|
1062
|
|
1063 bios_header_offset = readw(header_ptr);
|
|
1064 bios_header = bios_seg + bios_header_offset;
|
|
1065 bios_header += 0x30;
|
|
1066
|
|
1067 header_ptr = bios_header;
|
|
1068 pll_info_offset = readw(header_ptr);
|
|
1069 header_ptr = bios_seg + pll_info_offset;
|
|
1070
|
|
1071 memcpy_fromio(&pll, header_ptr, 50);
|
|
1072
|
|
1073 rinfo->pll.xclk = (u32)pll.XCLK;
|
|
1074 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
|
|
1075 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
|
|
1076 rinfo->pll.ppll_min = pll.PCLK_min_freq;
|
|
1077 rinfo->pll.ppll_max = pll.PCLK_max_freq;
|
|
1078 } else {
|
|
1079 /* no BIOS or BIOS not found, use defaults */
|
|
1080
|
|
1081 rinfo->pll.ppll_max = 35000;
|
|
1082 rinfo->pll.ppll_min = 12000;
|
|
1083 rinfo->pll.xclk = 16600;
|
|
1084 rinfo->pll.ref_div = 67;
|
|
1085 rinfo->pll.ref_clk = 2700;
|
|
1086 }
|
|
1087 }
|
|
1088
|
|
1089 static void radeon_engine_init (struct radeonfb_info *rinfo)
|
|
1090 {
|
|
1091 u32 temp;
|
|
1092
|
|
1093 /* disable 3D engine */
|
|
1094 OUTREG(RB3D_CNTL, 0);
|
|
1095
|
|
1096 radeon_engine_reset ();
|
|
1097
|
|
1098 radeon_fifo_wait (1);
|
|
1099 OUTREG(DSTCACHE_MODE, 0);
|
|
1100
|
|
1101 /* XXX */
|
|
1102 rinfo->pitch = ((rinfo->xres * (rinfo->depth / 8) + 0x3f)) >> 6;
|
|
1103
|
|
1104 radeon_fifo_wait (1);
|
|
1105 temp = INREG(DEFAULT_PITCH_OFFSET);
|
|
1106 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
|
|
1107 (rinfo->pitch << 0x16)));
|
|
1108
|
|
1109 radeon_fifo_wait (1);
|
|
1110 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
1111
|
|
1112 radeon_fifo_wait (1);
|
|
1113 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
|
|
1114 DEFAULT_SC_BOTTOM_MAX));
|
|
1115
|
|
1116 temp = radeon_get_dstbpp(rinfo->depth);
|
|
1117 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
|
|
1118 radeon_fifo_wait (1);
|
|
1119 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
1120 GMC_BRUSH_SOLID_COLOR |
|
|
1121 GMC_SRC_DATATYPE_COLOR));
|
|
1122
|
|
1123 radeon_fifo_wait (7);
|
|
1124
|
|
1125 /* clear line drawing regs */
|
|
1126 OUTREG(DST_LINE_START, 0);
|
|
1127 OUTREG(DST_LINE_END, 0);
|
|
1128
|
|
1129 /* set brush color regs */
|
|
1130 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
1131 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
1132
|
|
1133 /* set source color regs */
|
|
1134 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
1135 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
1136
|
|
1137 /* default write mask */
|
|
1138 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
1139
|
|
1140 radeon_engine_idle ();
|
|
1141 }
|
|
1142
|
|
1143
|
|
1144
|
|
1145 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
|
|
1146 {
|
|
1147 struct fb_info *info;
|
|
1148
|
|
1149 info = &rinfo->info;
|
|
1150
|
|
1151 strcpy (info->modename, rinfo->name);
|
|
1152 info->node = -1;
|
|
1153 info->flags = FBINFO_FLAG_DEFAULT;
|
|
1154 info->fbops = &radeon_fb_ops;
|
|
1155 info->display_fg = NULL;
|
|
1156 strncpy (info->fontname, fontname, sizeof (info->fontname));
|
|
1157 info->fontname[sizeof (info->fontname) - 1] = 0;
|
|
1158 info->changevar = NULL;
|
|
1159 info->switch_con = radeonfb_switch;
|
|
1160 info->updatevar = radeonfb_updatevar;
|
|
1161 info->blank = radeonfb_blank;
|
|
1162
|
|
1163 if (radeon_init_disp (rinfo) < 0)
|
|
1164 return -1;
|
|
1165
|
|
1166 return 0;
|
|
1167 }
|
|
1168
|
|
1169
|
|
1170
|
|
1171 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
|
|
1172 {
|
|
1173 struct fb_info *info;
|
|
1174 struct display *disp;
|
|
1175
|
|
1176 info = &rinfo->info;
|
|
1177 disp = &rinfo->disp;
|
|
1178
|
|
1179 disp->var = radeonfb_default_var;
|
|
1180 info->disp = disp;
|
|
1181
|
1914
|
1182 radeon_set_dispsw (rinfo, disp);
|
1911
|
1183
|
|
1184 if (noaccel)
|
|
1185 disp->scrollmode = SCROLL_YREDRAW;
|
|
1186 else
|
|
1187 disp->scrollmode = 0;
|
|
1188
|
|
1189 rinfo->currcon_display = disp;
|
|
1190
|
|
1191 if ((radeon_init_disp_var (rinfo)) < 0)
|
|
1192 return -1;
|
|
1193
|
|
1194 return 0;
|
|
1195 }
|
|
1196
|
|
1197
|
|
1198
|
|
1199 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
|
|
1200 {
|
|
1201 #ifndef MODULE
|
|
1202 if (mode_option)
|
|
1203 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
|
|
1204 NULL, 0, NULL, 8);
|
|
1205 else
|
|
1206 #endif
|
|
1207 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
|
|
1208 NULL, 0, NULL, 0);
|
|
1209
|
|
1210 if (noaccel)
|
|
1211 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
|
|
1212 else
|
|
1213 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
|
|
1214
|
|
1215 return 0;
|
|
1216 }
|
|
1217
|
|
1218
|
1914
|
1219 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
|
1911
|
1220 {
|
|
1221 int accel;
|
|
1222
|
|
1223 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
|
|
1224
|
|
1225 disp->dispsw_data = NULL;
|
|
1226
|
|
1227 disp->screen_base = (char*)rinfo->fb_base;
|
|
1228 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
1229 disp->type_aux = 0;
|
|
1230 disp->ypanstep = 1;
|
|
1231 disp->ywrapstep = 0;
|
|
1232 disp->can_soft_blank = 1;
|
|
1233 disp->inverse = 0;
|
|
1234
|
|
1235 rinfo->depth = disp->var.bits_per_pixel;
|
|
1236 switch (disp->var.bits_per_pixel) {
|
|
1237 #ifdef FBCON_HAS_CFB8
|
|
1238 case 8:
|
1914
|
1239 disp->dispsw = &fbcon_cfb8;
|
1911
|
1240 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1241 disp->line_length = disp->var.xres_virtual;
|
|
1242 break;
|
|
1243 #endif
|
|
1244 #ifdef FBCON_HAS_CFB16
|
|
1245 case 16:
|
|
1246 disp->dispsw = &fbcon_cfb16;
|
|
1247 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
1248 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1249 disp->line_length = disp->var.xres_virtual * 2;
|
|
1250 break;
|
|
1251 #endif
|
|
1252 #ifdef FBCON_HAS_CFB32
|
1914
|
1253 case 24:
|
|
1254 disp->dispsw = &fbcon_cfb24;
|
|
1255 disp->dispsw_data = &rinfo->con_cmap.cfb24;
|
|
1256 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1257 disp->line_length = disp->var.xres_virtual * 4;
|
|
1258 break;
|
|
1259 #endif
|
|
1260 #ifdef FBCON_HAS_CFB32
|
1911
|
1261 case 32:
|
|
1262 disp->dispsw = &fbcon_cfb32;
|
|
1263 disp->dispsw_data = &rinfo->con_cmap.cfb32;
|
|
1264 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1265 disp->line_length = disp->var.xres_virtual * 4;
|
|
1266 break;
|
|
1267 #endif
|
|
1268 default:
|
|
1269 printk ("radeonfb: setting fbcon_dummy renderer\n");
|
|
1270 disp->dispsw = &fbcon_dummy;
|
|
1271 }
|
|
1272
|
|
1273 return;
|
|
1274 }
|
|
1275
|
|
1276
|
|
1277
|
|
1278 /*
|
|
1279 * fb ops
|
|
1280 */
|
|
1281
|
|
1282 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
1283 struct fb_info *info)
|
|
1284 {
|
|
1285 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1286 struct display *disp;
|
|
1287
|
|
1288 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1289
|
|
1290 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
|
|
1291 strcpy (fix->id, rinfo->name);
|
|
1292
|
|
1293 fix->smem_start = rinfo->fb_base_phys;
|
|
1294 fix->smem_len = rinfo->video_ram;
|
|
1295
|
|
1296 fix->type = disp->type;
|
|
1297 fix->type_aux = disp->type_aux;
|
|
1298 fix->visual = disp->visual;
|
|
1299
|
|
1300 fix->xpanstep = 1;
|
|
1301 fix->ypanstep = 1;
|
|
1302 fix->ywrapstep = 0;
|
|
1303
|
|
1304 fix->line_length = disp->line_length;
|
|
1305
|
|
1306 fix->mmio_start = rinfo->mmio_base_phys;
|
|
1307 fix->mmio_len = RADEON_REGSIZE;
|
|
1308 if (noaccel)
|
|
1309 fix->accel = FB_ACCEL_NONE;
|
|
1310 else
|
|
1311 fix->accel = 40; /* XXX */
|
|
1312
|
|
1313 return 0;
|
|
1314 }
|
|
1315
|
|
1316
|
|
1317
|
|
1318 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
1319 struct fb_info *info)
|
|
1320 {
|
|
1321 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1322
|
|
1323 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
|
|
1324
|
|
1325 return 0;
|
|
1326 }
|
|
1327
|
|
1328
|
|
1329
|
|
1330 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
1331 struct fb_info *info)
|
|
1332 {
|
|
1333 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1334 struct display *disp;
|
|
1335 struct fb_var_screeninfo v;
|
1914
|
1336 int nom, den, accel;
|
1911
|
1337 unsigned chgvar = 0;
|
|
1338
|
|
1339 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1340
|
|
1341 accel = var->accel_flags & FB_ACCELF_TEXT;
|
|
1342
|
|
1343 if (con >= 0) {
|
|
1344 chgvar = ((disp->var.xres != var->xres) ||
|
|
1345 (disp->var.yres != var->yres) ||
|
|
1346 (disp->var.xres_virtual != var->xres_virtual) ||
|
|
1347 (disp->var.yres_virtual != var->yres_virtual) ||
|
1914
|
1348 (disp->var.bits_per_pixel != var->bits_per_pixel) ||
|
1911
|
1349 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
|
|
1350 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
|
|
1351 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
|
|
1352 }
|
|
1353
|
|
1354 memcpy (&v, var, sizeof (v));
|
|
1355
|
|
1356 switch (v.bits_per_pixel) {
|
|
1357 #ifdef FBCON_HAS_CFB8
|
|
1358 case 8:
|
|
1359 nom = den = 1;
|
|
1360 disp->line_length = v.xres_virtual;
|
|
1361 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1362 v.red.offset = v.green.offset = v.blue.offset = 0;
|
|
1363 v.red.length = v.green.length = v.blue.length = 8;
|
1914
|
1364 v.transp.offset = v.transp.length = 0;
|
1911
|
1365 break;
|
|
1366 #endif
|
|
1367
|
|
1368 #ifdef FBCON_HAS_CFB16
|
|
1369 case 16:
|
|
1370 nom = 2;
|
|
1371 den = 1;
|
|
1372 disp->line_length = v.xres_virtual * 2;
|
|
1373 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1374 v.red.offset = 11;
|
|
1375 v.green.offset = 5;
|
|
1376 v.blue.offset = 0;
|
|
1377 v.red.length = 5;
|
|
1378 v.green.length = 6;
|
|
1379 v.blue.length = 5;
|
1914
|
1380 v.transp.offset = v.transp.length = 0;
|
1911
|
1381 break;
|
|
1382 #endif
|
|
1383
|
1914
|
1384 #ifdef FBCON_HAS_CFB24
|
|
1385 case 24:
|
|
1386 nom = 4;
|
|
1387 den = 1;
|
|
1388 disp->line_length = v.xres_virtual * 3;
|
|
1389 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1390 v.red.offset = 16;
|
|
1391 v.green.offset = 8;
|
|
1392 v.blue.offset = 0;
|
|
1393 v.red.length = v.blue.length = v.green.length = 8;
|
|
1394 v.transp.offset = v.transp.length = 0;
|
|
1395 break;
|
|
1396 #endif
|
1911
|
1397 #ifdef FBCON_HAS_CFB32
|
|
1398 case 32:
|
|
1399 nom = 4;
|
|
1400 den = 1;
|
|
1401 disp->line_length = v.xres_virtual * 4;
|
|
1402 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1403 v.red.offset = 16;
|
|
1404 v.green.offset = 8;
|
|
1405 v.blue.offset = 0;
|
|
1406 v.red.length = v.blue.length = v.green.length = 8;
|
1914
|
1407 v.transp.offset = 24;
|
|
1408 v.transp.length = 8;
|
1911
|
1409 break;
|
|
1410 #endif
|
|
1411 default:
|
|
1412 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
|
|
1413 var->xres, var->yres, var->bits_per_pixel);
|
|
1414 return -EINVAL;
|
|
1415 }
|
|
1416
|
1914
|
1417 if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
|
|
1418 return -EINVAL;
|
1911
|
1419
|
|
1420 if (v.xoffset < 0)
|
|
1421 v.xoffset = 0;
|
|
1422 if (v.yoffset < 0)
|
|
1423 v.yoffset = 0;
|
|
1424
|
|
1425 if (v.xoffset > v.xres_virtual - v.xres)
|
|
1426 v.xoffset = v.xres_virtual - v.xres - 1;
|
|
1427
|
|
1428 if (v.yoffset > v.yres_virtual - v.yres)
|
|
1429 v.yoffset = v.yres_virtual - v.yres - 1;
|
|
1430
|
|
1431 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
|
|
1432 v.transp.offset = v.transp.length =
|
|
1433 v.transp.msb_right = 0;
|
|
1434
|
|
1435 switch (v.activate & FB_ACTIVATE_MASK) {
|
|
1436 case FB_ACTIVATE_TEST:
|
|
1437 return 0;
|
|
1438 case FB_ACTIVATE_NXTOPEN:
|
|
1439 case FB_ACTIVATE_NOW:
|
|
1440 break;
|
|
1441 default:
|
|
1442 return -EINVAL;
|
|
1443 }
|
|
1444
|
|
1445 memcpy (&disp->var, &v, sizeof (v));
|
|
1446
|
1914
|
1447 if (chgvar) {
|
|
1448 radeon_set_dispsw(rinfo, disp);
|
|
1449
|
|
1450 if (noaccel)
|
|
1451 disp->scrollmode = SCROLL_YREDRAW;
|
|
1452 else
|
|
1453 disp->scrollmode = 0;
|
|
1454
|
|
1455 if (info && info->changevar)
|
|
1456 info->changevar(con);
|
|
1457 }
|
|
1458
|
1911
|
1459 radeon_load_video_mode (rinfo, &v);
|
|
1460
|
1914
|
1461 do_install_cmap(con, info);
|
|
1462
|
1911
|
1463 return 0;
|
|
1464 }
|
|
1465
|
|
1466
|
|
1467
|
|
1468 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1469 struct fb_info *info)
|
|
1470 {
|
|
1471 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1472 struct display *disp;
|
|
1473
|
|
1474 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1475
|
|
1476 if (con == rinfo->currcon) {
|
|
1477 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
|
|
1478 return rc;
|
|
1479 } else if (disp->cmap.len)
|
|
1480 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
|
|
1481 else
|
|
1482 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
|
|
1483 cmap, kspc ? 0 : 2);
|
|
1484
|
|
1485 return 0;
|
|
1486 }
|
|
1487
|
|
1488
|
|
1489
|
|
1490 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1491 struct fb_info *info)
|
|
1492 {
|
|
1493 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1494 struct display *disp;
|
|
1495 unsigned int cmap_len;
|
|
1496
|
|
1497 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1498
|
|
1499 cmap_len = radeon_get_cmap_len (&disp->var);
|
|
1500 if (disp->cmap.len != cmap_len) {
|
|
1501 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
|
|
1502 if (err)
|
|
1503 return err;
|
|
1504 }
|
|
1505
|
|
1506 if (con == rinfo->currcon) {
|
|
1507 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
|
|
1508 return rc;
|
|
1509 } else
|
|
1510 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
|
|
1511
|
|
1512 return 0;
|
|
1513 }
|
|
1514
|
|
1515
|
|
1516
|
|
1517 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
1518 struct fb_info *info)
|
|
1519 {
|
|
1520 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1521 u32 offset, xoffset, yoffset;
|
|
1522
|
|
1523 xoffset = (var->xoffset + 7) & ~7;
|
|
1524 yoffset = var->yoffset;
|
1911
|
1525
|
1914
|
1526 if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
|
|
1527 var->yres_virtual))
|
|
1528 return -EINVAL;
|
1911
|
1529
|
1914
|
1530 offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
|
|
1531
|
|
1532 OUTREG(CRTC_OFFSET, offset);
|
1911
|
1533
|
|
1534 return 0;
|
|
1535 }
|
|
1536
|
|
1537
|
1914
|
1538 static void do_install_cmap(int con, struct fb_info *info)
|
|
1539 {
|
|
1540 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1541
|
|
1542 if (con != rinfo->currcon)
|
|
1543 return;
|
|
1544
|
|
1545 if (fb_display[con].cmap.len)
|
|
1546 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
|
|
1547 else {
|
|
1548 int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
|
|
1549 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
|
|
1550 }
|
|
1551 }
|
|
1552
|
|
1553
|
|
1554 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
1555 struct fb_var_screeninfo *var,
|
|
1556 struct fb_var_screeninfo *v,
|
|
1557 int nom, int den)
|
|
1558 {
|
|
1559 static struct {
|
|
1560 int xres, yres;
|
|
1561 } modes[] = {
|
|
1562 {1600, 1280},
|
|
1563 {1280, 1024},
|
|
1564 {1024, 768},
|
|
1565 {800, 600},
|
|
1566 {640, 480},
|
|
1567 {-1, -1}
|
|
1568 };
|
|
1569 int i;
|
|
1570
|
|
1571 /* use highest possible virtual resolution */
|
|
1572 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
|
|
1573 printk("radeonfb: using max availabe virtual resolution\n");
|
|
1574 for (i=0; modes[i].xres != -1; i++) {
|
|
1575 if (modes[i].xres * nom / den * modes[i].yres <
|
|
1576 rinfo->video_ram / 2)
|
|
1577 break;
|
|
1578 }
|
|
1579 if (modes[i].xres == -1) {
|
|
1580 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
|
|
1581 return -EINVAL;
|
|
1582 }
|
|
1583 v->xres_virtual = modes[i].xres;
|
|
1584 v->yres_virtual = modes[i].yres;
|
|
1585
|
|
1586 printk("radeonfb: virtual resolution set to max of %dx%d\n",
|
|
1587 v->xres_virtual, v->yres_virtual);
|
|
1588 } else if (v->xres_virtual == -1) {
|
|
1589 v->xres_virtual = (rinfo->video_ram * den /
|
|
1590 (nom * v->yres_virtual * 2)) & ~15;
|
|
1591 } else if (v->yres_virtual == -1) {
|
|
1592 v->xres_virtual = (v->xres_virtual + 15) & ~15;
|
|
1593 v->yres_virtual = rinfo->video_ram * den /
|
|
1594 (nom * v->xres_virtual *2);
|
|
1595 } else {
|
|
1596 if (v->xres_virtual * nom / den * v->yres_virtual >
|
|
1597 rinfo->video_ram) {
|
|
1598 return -EINVAL;
|
|
1599 }
|
|
1600 }
|
|
1601
|
|
1602 if (v->xres_virtual * nom / den >= 8192) {
|
|
1603 v->xres_virtual = 8192 * den / nom - 16;
|
|
1604 }
|
|
1605
|
|
1606 if (v->xres_virtual < v->xres)
|
|
1607 return -EINVAL;
|
|
1608
|
|
1609 if (v->yres_virtual < v->yres)
|
|
1610 return -EINVAL;
|
|
1611
|
|
1612 return 0;
|
|
1613 }
|
|
1614
|
1911
|
1615
|
|
1616 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
1617 unsigned long arg, int con, struct fb_info *info)
|
|
1618 {
|
|
1619 return -EINVAL;
|
|
1620 }
|
|
1621
|
|
1622
|
|
1623
|
|
1624 static int radeonfb_switch (int con, struct fb_info *info)
|
|
1625 {
|
|
1626 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1627 struct display *disp;
|
|
1628 struct fb_cmap *cmap;
|
|
1629 int switchcon = 0;
|
1914
|
1630
|
1911
|
1631 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1632
|
|
1633 if (rinfo->currcon >= 0) {
|
|
1634 cmap = &(rinfo->currcon_display->cmap);
|
|
1635 if (cmap->len)
|
|
1636 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
|
|
1637 }
|
|
1638
|
|
1639 if ((disp->var.xres != rinfo->xres) ||
|
|
1640 (disp->var.yres != rinfo->yres) ||
|
|
1641 (disp->var.pixclock != rinfo->pixclock) ||
|
|
1642 (disp->var.bits_per_pixel != rinfo->depth))
|
|
1643 switchcon = 1;
|
|
1644
|
|
1645 if (switchcon) {
|
|
1646 rinfo->currcon = con;
|
|
1647 rinfo->currcon_display = disp;
|
|
1648 disp->var.activate = FB_ACTIVATE_NOW;
|
|
1649
|
|
1650 radeonfb_set_var (&disp->var, con, info);
|
1914
|
1651 radeon_set_dispsw (rinfo, disp);
|
|
1652 do_install_cmap(con, info);
|
1911
|
1653 }
|
1914
|
1654
|
|
1655 /* XXX absurd hack for X to restore console */
|
|
1656 {
|
|
1657 OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
|
1658 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
|
1659 }
|
|
1660
|
1911
|
1661 return 0;
|
|
1662 }
|
|
1663
|
|
1664
|
|
1665
|
|
1666 static int radeonfb_updatevar (int con, struct fb_info *info)
|
|
1667 {
|
|
1668 int rc;
|
|
1669
|
|
1670 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
|
|
1671 con, info);
|
|
1672
|
|
1673 return rc;
|
|
1674 }
|
|
1675
|
|
1676 static void radeonfb_blank (int blank, struct fb_info *info)
|
|
1677 {
|
|
1678 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1679 u32 val = INREG(CRTC_EXT_CNTL);
|
|
1680
|
|
1681 /* reset it */
|
|
1682 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
|
|
1683 CRTC_VSYNC_DIS);
|
1911
|
1684
|
|
1685 switch (blank) {
|
1914
|
1686 case VESA_NO_BLANKING:
|
|
1687 break;
|
|
1688 case VESA_VSYNC_SUSPEND:
|
|
1689 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
|
1911
|
1690 break;
|
1914
|
1691 case VESA_HSYNC_SUSPEND:
|
|
1692 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
|
1911
|
1693 break;
|
1914
|
1694 case VESA_POWERDOWN:
|
|
1695 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
|
|
1696 CRTC_HSYNC_DIS);
|
1911
|
1697 break;
|
|
1698 }
|
1915
|
1699 if(blank == VESA_NO_BLANKING && rinfo->hasCRTC2)
|
|
1700 OUTREGP(CRTC_EXT_CNTL,CRTC_CRT_ON, val);
|
|
1701 else OUTREG(CRTC_EXT_CNTL, val);
|
1911
|
1702 }
|
|
1703
|
|
1704
|
|
1705
|
|
1706 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
|
|
1707 {
|
|
1708 int rc = 16; /* reasonable default */
|
|
1709
|
|
1710 switch (var->bits_per_pixel) {
|
|
1711 case 8:
|
|
1712 rc = 256;
|
|
1713 break;
|
|
1714 case 16:
|
|
1715 rc = 64;
|
|
1716 break;
|
|
1717 default:
|
|
1718 rc = 32;
|
|
1719 break;
|
|
1720 }
|
|
1721
|
|
1722 return rc;
|
|
1723 }
|
|
1724
|
|
1725
|
|
1726
|
|
1727 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
1728 unsigned *blue, unsigned *transp,
|
|
1729 struct fb_info *info)
|
|
1730 {
|
|
1731 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1732
|
|
1733 if (regno > 255)
|
|
1734 return 1;
|
|
1735
|
|
1736 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
|
|
1737 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
|
|
1738 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
|
|
1739 *transp = 0;
|
|
1740
|
|
1741 return 0;
|
|
1742 }
|
|
1743
|
|
1744
|
|
1745
|
|
1746 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
1747 unsigned blue, unsigned transp, struct fb_info *info)
|
|
1748 {
|
|
1749 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1750 u32 pindex;
|
1911
|
1751
|
|
1752 if (regno > 255)
|
|
1753 return 1;
|
|
1754
|
|
1755 red >>= 8;
|
|
1756 green >>= 8;
|
|
1757 blue >>= 8;
|
|
1758 rinfo->palette[regno].red = red;
|
|
1759 rinfo->palette[regno].green = green;
|
|
1760 rinfo->palette[regno].blue = blue;
|
|
1761
|
|
1762 /* init gamma for hicolor */
|
|
1763 if ((rinfo->depth > 8) && (regno == 0)) {
|
|
1764 int i;
|
|
1765
|
|
1766 for (i=0; i<255; i++) {
|
|
1767 OUTREG(PALETTE_INDEX, i);
|
1914
|
1768 OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
|
1911
|
1769 }
|
|
1770 }
|
|
1771
|
|
1772 /* default */
|
|
1773 pindex = regno;
|
1914
|
1774
|
|
1775 /* XXX actually bpp, fixme */
|
|
1776 if (rinfo->depth == 16)
|
|
1777 pindex = regno * 8;
|
|
1778
|
|
1779 if (rinfo->depth == 16) {
|
|
1780 OUTREG(PALETTE_INDEX, pindex/2);
|
|
1781 OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
|
|
1782 (green << 8) | (rinfo->palette[regno/2].blue));
|
|
1783 green = rinfo->palette[regno/2].green;
|
|
1784 }
|
|
1785
|
|
1786 if ((rinfo->depth == 8) || (regno < 32)) {
|
|
1787 OUTREG(PALETTE_INDEX, pindex);
|
|
1788 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
|
|
1789 }
|
|
1790
|
|
1791 #if 0
|
1911
|
1792 col = (red << 16) | (green << 8) | blue;
|
|
1793
|
|
1794 if (rinfo->depth == 16) {
|
|
1795 pindex = regno << 3;
|
|
1796
|
|
1797 if ((rinfo->depth == 16) && (regno >= 32)) {
|
|
1798 pindex -= 252;
|
|
1799
|
|
1800 col = (rinfo->palette[regno >> 1].red << 16) |
|
|
1801 (green << 8) |
|
|
1802 (rinfo->palette[regno >> 1].blue);
|
|
1803 } else {
|
|
1804 col = (red << 16) | (green << 8) | blue;
|
|
1805 }
|
|
1806 }
|
|
1807
|
|
1808 OUTREG8(PALETTE_INDEX, pindex);
|
|
1809 radeon_fifo_wait(32);
|
|
1810 OUTREG(PALETTE_DATA, col);
|
1914
|
1811 #endif
|
1911
|
1812
|
|
1813 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
1814 if (regno < 32) {
|
|
1815 switch (rinfo->depth) {
|
|
1816 #ifdef FBCON_HAS_CFB16
|
|
1817 case 16:
|
1914
|
1818 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
|
1911
|
1819 regno;
|
|
1820 break;
|
|
1821 #endif
|
1914
|
1822 #ifdef FBCON_HAS_CFB24
|
|
1823 case 24:
|
|
1824 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
|
|
1825 break;
|
|
1826 #endif
|
1911
|
1827 #ifdef FBCON_HAS_CFB32
|
|
1828 case 32: {
|
|
1829 u32 i;
|
|
1830
|
|
1831 i = (regno << 8) | regno;
|
|
1832 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
|
|
1833 break;
|
|
1834 }
|
|
1835 #endif
|
|
1836 }
|
|
1837 }
|
|
1838 #endif
|
|
1839 return 0;
|
|
1840 }
|
|
1841
|
|
1842
|
|
1843
|
|
1844 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
1845 struct radeon_regs *save)
|
|
1846 {
|
|
1847 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
|
|
1848 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
|
|
1849 save->dac_cntl = INREG(DAC_CNTL);
|
|
1850 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
|
|
1851 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
|
|
1852 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
|
|
1853 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
|
|
1854 save->crtc_pitch = INREG(CRTC_PITCH);
|
|
1855 }
|
|
1856
|
|
1857
|
|
1858
|
|
1859 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
1860 struct fb_var_screeninfo *mode)
|
|
1861 {
|
|
1862 struct radeon_regs newmode;
|
|
1863 int hTotal, vTotal, hSyncStart, hSyncEnd,
|
|
1864 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
|
|
1865 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
|
|
1866 u32 dotClock = 1000000000 / mode->pixclock,
|
|
1867 sync, h_sync_pol, v_sync_pol;
|
|
1868 int freq = dotClock / 10; /* x 100 */
|
|
1869 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
|
|
1870 int useable_precision, roff, ron;
|
|
1871 int min_bits, format = 0;
|
|
1872 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
|
|
1873
|
|
1874 rinfo->xres = mode->xres;
|
|
1875 rinfo->yres = mode->yres;
|
|
1876 rinfo->pixclock = mode->pixclock;
|
|
1877
|
|
1878 hSyncStart = mode->xres + mode->right_margin;
|
|
1879 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1880 hTotal = hSyncEnd + mode->left_margin;
|
|
1881
|
|
1882 vSyncStart = mode->yres + mode->lower_margin;
|
|
1883 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1884 vTotal = vSyncEnd + mode->upper_margin;
|
|
1885
|
|
1886 sync = mode->sync;
|
|
1887 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1888 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
|
1889
|
|
1890 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
|
|
1891 hSyncStart, hSyncEnd, hTotal);
|
|
1892 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
|
|
1893 vSyncStart, vSyncEnd, vTotal);
|
|
1894
|
|
1895 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1896 vsync_wid = vSyncEnd - vSyncStart;
|
|
1897 if (hsync_wid == 0)
|
|
1898 hsync_wid = 1;
|
|
1899 else if (hsync_wid > 0x3f) /* max */
|
|
1900 hsync_wid = 0x3f;
|
1914
|
1901 vsync_wid = mode->vsync_len;
|
1911
|
1902 if (vsync_wid == 0)
|
|
1903 vsync_wid = 1;
|
|
1904 else if (vsync_wid > 0x1f) /* max */
|
|
1905 vsync_wid = 0x1f;
|
|
1906
|
1914
|
1907 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1908 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
1911
|
1909
|
|
1910 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
|
1911
|
|
1912 switch (mode->bits_per_pixel) {
|
|
1913 case 8:
|
|
1914 format = DST_8BPP;
|
|
1915 bytpp = 1;
|
|
1916 break;
|
|
1917 case 16:
|
|
1918 format = DST_16BPP;
|
|
1919 bytpp = 2;
|
|
1920 break;
|
|
1921 case 24:
|
|
1922 format = DST_24BPP;
|
|
1923 bytpp = 3;
|
|
1924 break;
|
|
1925 case 32:
|
|
1926 format = DST_32BPP;
|
|
1927 bytpp = 4;
|
|
1928 break;
|
|
1929 }
|
|
1930
|
|
1931 hsync_fudge = hsync_adj_tab[format-1];
|
|
1932 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1933
|
|
1934 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
|
|
1935 (format << 8);
|
1915
|
1936 if(rinfo->hasCRTC2)
|
|
1937 /* HACKED: !!! Enable CRT port here !!! */
|
|
1938 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
|
|
1939 else newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
|
1911
|
1940 newmode.dac_cntl = INREG(DAC_CNTL) | DAC_MASK_ALL | DAC_VGA_ADR_EN |
|
|
1941 DAC_8BIT_EN;
|
|
1942
|
|
1943 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0xffff) |
|
|
1944 (((mode->xres / 8) - 1) << 16));
|
|
1945
|
|
1946 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
|
1914
|
1947 (hsync_wid << 16) | (h_sync_pol << 23));
|
1911
|
1948
|
|
1949 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
|
1950 ((mode->yres - 1) << 16);
|
|
1951
|
|
1952 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
|
1914
|
1953 (vsync_wid << 16) | (v_sync_pol << 23));
|
1911
|
1954
|
|
1955 newmode.crtc_pitch = (mode->xres >> 3);
|
|
1956
|
1915
|
1957 #if defined(__BIG_ENDIAN)
|
1914
|
1958 newmode.surface_cntl = SURF_TRANSLATION_DIS;
|
|
1959 switch (mode->bits_per_pixel) {
|
|
1960 case 16:
|
|
1961 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
|
1962 break;
|
|
1963 case 24:
|
|
1964 case 32:
|
|
1965 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
|
|
1966 break;
|
|
1967 }
|
|
1968 #endif
|
|
1969
|
1911
|
1970 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
|
1971 & ~(0x3f)) / 64;
|
|
1972
|
|
1973 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
|
|
1974 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
|
|
1975 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
|
|
1976 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
|
|
1977
|
|
1978 newmode.xres = mode->xres;
|
|
1979 newmode.yres = mode->yres;
|
|
1980
|
|
1981 rinfo->bpp = mode->bits_per_pixel;
|
1914
|
1982 rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
|
|
1983 rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
|
1911
|
1984
|
|
1985 if (freq > rinfo->pll.ppll_max)
|
|
1986 freq = rinfo->pll.ppll_max;
|
|
1987 if (freq*12 < rinfo->pll.ppll_min)
|
|
1988 freq = rinfo->pll.ppll_min / 12;
|
|
1989
|
|
1990 {
|
|
1991 struct {
|
|
1992 int divider;
|
|
1993 int bitvalue;
|
|
1994 } *post_div,
|
|
1995 post_divs[] = {
|
|
1996 { 1, 0 },
|
|
1997 { 2, 1 },
|
|
1998 { 4, 2 },
|
|
1999 { 8, 3 },
|
|
2000 { 3, 4 },
|
|
2001 { 16, 5 },
|
|
2002 { 6, 6 },
|
|
2003 { 12, 7 },
|
|
2004 { 0, 0 },
|
|
2005 };
|
|
2006
|
|
2007 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
2008 rinfo->pll_output_freq = post_div->divider * freq;
|
|
2009 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
|
|
2010 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
|
|
2011 break;
|
|
2012 }
|
|
2013
|
|
2014 rinfo->post_div = post_div->divider;
|
|
2015 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
|
|
2016 rinfo->pll.ref_clk);
|
|
2017 newmode.ppll_ref_div = rinfo->pll.ref_div;
|
|
2018 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
|
|
2019 }
|
|
2020
|
|
2021 RTRACE("post div = 0x%x\n", rinfo->post_div);
|
|
2022 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
|
|
2023 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
|
|
2024
|
|
2025 /* DDA */
|
|
2026 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
|
|
2027 rinfo->pll.ref_div * rinfo->post_div);
|
|
2028 xclk_freq = rinfo->pll.xclk;
|
|
2029
|
|
2030 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
|
|
2031
|
|
2032 min_bits = min_bits_req(xclk_per_trans);
|
|
2033 useable_precision = min_bits + 1;
|
|
2034
|
|
2035 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
|
|
2036 vclk_freq * mode->bits_per_pixel);
|
|
2037
|
|
2038 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
|
|
2039 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
|
|
2040 xclk_per_trans) << (11 - useable_precision);
|
|
2041 roff = xclk_per_trans_precise * (32 - 4);
|
|
2042
|
|
2043 RTRACE("ron = %d, roff = %d\n", ron, roff);
|
|
2044 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
|
|
2045
|
|
2046 if ((ron + rinfo->ram.rloop) >= roff) {
|
|
2047 printk("radeonfb: error ron out of range\n");
|
|
2048 return;
|
|
2049 }
|
|
2050
|
|
2051 newmode.dda_config = (xclk_per_trans_precise |
|
|
2052 (useable_precision << 16) |
|
|
2053 (rinfo->ram.rloop << 20));
|
|
2054 newmode.dda_on_off = (ron << 16) | roff;
|
|
2055
|
|
2056 /* do it! */
|
|
2057 radeon_write_mode (rinfo, &newmode);
|
1915
|
2058 /* XXX absurd hack for X to restore console on VE */
|
|
2059 if(rinfo->hasCRTC2 && rinfo->crtDispType == MT_CRT &&
|
|
2060 (rinfo->dviDispType == MT_NONE || rinfo->dviDispType == MT_STV)) {
|
|
2061 OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
|
2062 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
|
2063 }
|
1911
|
2064
|
|
2065 return;
|
|
2066 }
|
|
2067
|
|
2068
|
1915
|
2069 /*****
|
|
2070 When changing mode with Dual-head card (VE/M6), care must
|
|
2071 be taken for the special order in setting registers. CRTC2 has
|
|
2072 to be set before changing CRTC_EXT register.
|
|
2073 Otherwise we may get a blank screen.
|
|
2074 *****/
|
1911
|
2075
|
|
2076 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
2077 struct radeon_regs *mode)
|
|
2078 {
|
|
2079 int i;
|
|
2080
|
|
2081 /* blank screen */
|
|
2082 OUTREG8(CRTC_EXT_CNTL + 1, 4);
|
|
2083
|
|
2084 for (i=0; i<9; i++)
|
|
2085 OUTREG(common_regs[i].reg, common_regs[i].val);
|
|
2086
|
|
2087 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
|
|
2088 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
|
2089 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
|
|
2090 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
|
|
2091 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
|
|
2092 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
|
|
2093 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
|
|
2094 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
|
|
2095 OUTREG(CRTC_OFFSET, 0);
|
|
2096 OUTREG(CRTC_OFFSET_CNTL, 0);
|
|
2097 OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
1915
|
2098 #if defined(__BIG_ENDIAN)
|
|
2099 /* XXX this code makes degradation of mplayer quality on Radeon VE */
|
1914
|
2100 OUTREG(SURFACE_CNTL, mode->surface_cntl);
|
1915
|
2101 #endif
|
|
2102 /* Here we should restore FP registers for LCD & DFP monitors */
|
1911
|
2103
|
|
2104 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
|
|
2105 PPLL_DIV_SEL_MASK) {
|
|
2106 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
|
|
2107 }
|
|
2108
|
|
2109 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
|
|
2110
|
|
2111 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
|
|
2112 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
|
|
2113 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
|
2114 }
|
|
2115
|
|
2116 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
|
|
2117 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
|
|
2118 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
|
2119 }
|
|
2120
|
|
2121 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
|
|
2122 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
|
|
2123 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
|
2124 }
|
|
2125
|
|
2126 OUTPLL(HTOTAL_CNTL, 0);
|
|
2127
|
|
2128 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
|
|
2129
|
|
2130 OUTREG(DDA_CONFIG, mode->dda_config);
|
|
2131 OUTREG(DDA_ON_OFF, mode->dda_on_off);
|
|
2132
|
|
2133 /* unblank screen */
|
|
2134 OUTREG8(CRTC_EXT_CNTL + 1, 0);
|
|
2135
|
|
2136 return;
|
|
2137 }
|
|
2138
|
1914
|
2139 #if 0
|
1911
|
2140
|
|
2141 /*
|
|
2142 * text console acceleration
|
|
2143 */
|
|
2144
|
|
2145
|
|
2146 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
|
|
2147 int dsty, int dstx, int height, int width)
|
|
2148 {
|
|
2149 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
2150 u32 dp_cntl = DST_LAST_PEL;
|
|
2151
|
|
2152 srcx *= fontwidth(p);
|
|
2153 srcy *= fontheight(p);
|
|
2154 dstx *= fontwidth(p);
|
|
2155 dsty *= fontheight(p);
|
|
2156 width *= fontwidth(p);
|
|
2157 height *= fontheight(p);
|
|
2158
|
|
2159 if (srcy < dsty) {
|
|
2160 srcy += height - 1;
|
|
2161 dsty += height - 1;
|
|
2162 } else
|
|
2163 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
|
|
2164
|
|
2165 if (srcx < dstx) {
|
|
2166 srcx += width - 1;
|
|
2167 dstx += width - 1;
|
|
2168 } else
|
|
2169 dp_cntl |= DST_X_LEFT_TO_RIGHT;
|
|
2170
|
|
2171 radeon_fifo_wait(6);
|
|
2172 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2173 GMC_BRUSH_NONE |
|
|
2174 GMC_SRC_DATATYPE_COLOR |
|
|
2175 ROP3_S |
|
|
2176 DP_SRC_SOURCE_MEMORY));
|
|
2177 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2178 OUTREG(DP_CNTL, dp_cntl);
|
|
2179 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
|
|
2180 OUTREG(DST_Y_X, (dsty << 16) | dstx);
|
|
2181 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
|
|
2182 }
|
|
2183
|
|
2184
|
|
2185
|
|
2186 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|
2187 int srcy, int srcx, int height, int width)
|
|
2188 {
|
|
2189 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
2190 u32 clr;
|
|
2191
|
|
2192 clr = attr_bgcol_ec(p, conp);
|
|
2193 clr |= (clr << 8);
|
|
2194 clr |= (clr << 16);
|
|
2195
|
|
2196 srcx *= fontwidth(p);
|
|
2197 srcy *= fontheight(p);
|
|
2198 width *= fontwidth(p);
|
|
2199 height *= fontheight(p);
|
|
2200
|
|
2201 radeon_fifo_wait(6);
|
|
2202 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2203 GMC_BRUSH_SOLID_COLOR |
|
|
2204 GMC_SRC_DATATYPE_COLOR |
|
|
2205 ROP3_P));
|
|
2206 OUTREG(DP_BRUSH_FRGD_CLR, clr);
|
|
2207 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2208 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
|
|
2209 OUTREG(DST_Y_X, (srcy << 16) | srcx);
|
|
2210 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
|
|
2211 }
|
|
2212
|
|
2213
|
|
2214
|
|
2215
|
|
2216 #ifdef FBCON_HAS_CFB8
|
|
2217 static struct display_switch fbcon_radeon8 = {
|
|
2218 setup: fbcon_cfb8_setup,
|
|
2219 bmove: fbcon_radeon_bmove,
|
|
2220 clear: fbcon_cfb8_clear,
|
|
2221 putc: fbcon_cfb8_putc,
|
|
2222 putcs: fbcon_cfb8_putcs,
|
|
2223 revc: fbcon_cfb8_revc,
|
|
2224 clear_margins: fbcon_cfb8_clear_margins,
|
|
2225 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
|
2226 };
|
|
2227 #endif
|
1914
|
2228
|
|
2229 #endif /* 0 */
|