Mercurial > mplayer.hg
annotate drivers/mga_vid.c @ 5349:80d11d6a5fca
fixed to work nicely with the new system (and yes, I did originate the RoQ
audio decoder for this project)
author | melanson |
---|---|
date | Tue, 26 Mar 2002 04:22:47 +0000 |
parents | 3cc26c4e662b |
children | cdf5b88bdaa8 |
rev | line source |
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2345 | 1 //#define CRTC2 |
2 | |
1 | 3 // YUY2 support (see config.format) added by A'rpi/ESP-team |
57 | 4 // double buffering added by A'rpi/ESP-team |
5 | |
6 // Set this value, if autodetection fails! (video ram size in megabytes) | |
91 | 7 // #define MGA_MEMORY_SIZE 16 |
1 | 8 |
68 | 9 //#define MGA_ALLOW_IRQ |
10 | |
11 #define MGA_VSYNC_POS 2 | |
12 | |
1 | 13 /* |
14 * | |
15 * mga_vid.c | |
16 * | |
17 * Copyright (C) 1999 Aaron Holtzman | |
18 * | |
19 * Module skeleton based on gutted agpgart module by Jeff Hartmann | |
20 * <slicer@ionet.net> | |
21 * | |
22 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 | |
23 * | |
24 * BES == Back End Scaler | |
25 * | |
26 * This software has been released under the terms of the GNU Public | |
27 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
28 */ | |
29 | |
30 //It's entirely possible this major conflicts with something else | |
31 /* mknod /dev/mga_vid c 178 0 */ | |
32 | |
33 #include <linux/config.h> | |
34 #include <linux/version.h> | |
35 #include <linux/module.h> | |
36 #include <linux/types.h> | |
37 #include <linux/kernel.h> | |
38 #include <linux/sched.h> | |
39 #include <linux/mm.h> | |
40 #include <linux/string.h> | |
41 #include <linux/errno.h> | |
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42 |
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43 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) |
1 | 44 #include <linux/malloc.h> |
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45 #else |
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46 #include <linux/slab.h> |
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47 #endif |
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48 |
1 | 49 #include <linux/pci.h> |
63 | 50 #include <linux/ioport.h> |
1 | 51 #include <linux/init.h> |
52 | |
53 #include "mga_vid.h" | |
54 | |
55 #ifdef CONFIG_MTRR | |
56 #include <asm/mtrr.h> | |
57 #endif | |
58 | |
59 #include <asm/uaccess.h> | |
60 #include <asm/system.h> | |
61 #include <asm/io.h> | |
62 | |
63 #define TRUE 1 | |
64 #define FALSE 0 | |
65 | |
66 #define MGA_VID_MAJOR 178 | |
67 | |
57 | 68 //#define MGA_VIDMEM_SIZE mga_ram_size |
1 | 69 |
70 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI | |
71 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 | |
72 #endif | |
73 | |
74 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP | |
75 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 | |
76 #endif | |
77 | |
78 #ifndef PCI_DEVICE_ID_MATROX_G400 | |
79 #define PCI_DEVICE_ID_MATROX_G400 0x0525 | |
80 #endif | |
81 | |
1989 | 82 #ifndef PCI_DEVICE_ID_MATROX_G550 |
83 #define PCI_DEVICE_ID_MATROX_G550 0x2527 | |
84 #endif | |
85 | |
1 | 86 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>"); |
2262 | 87 #ifdef MODULE_LICENSE |
88 MODULE_LICENSE("GPL"); | |
89 #endif | |
1 | 90 |
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91 #define PARAM_BRIGHTNESS "brightness=" |
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92 #define PARAM_CONTRAST "contrast=" |
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93 #define PARAM_BLACKIE "blackie=" |
4484 | 94 |
95 #define PARAM_BUFF_SIZE 4096 | |
96 static uint8_t *mga_param_buff = NULL; | |
97 static uint32_t mga_param_buff_size=0; | |
98 static uint32_t mga_param_buff_len=0; | |
99 | |
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100 #define min(x,y) (((x)<(y))?(x):(y)) |
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101 |
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102 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0) |
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103 #include <linux/ctype.h> |
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104 |
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105 unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base) |
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106 { |
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107 unsigned long result = 0,value; |
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108 |
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109 if (!base) { |
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110 base = 10; |
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111 if (*cp == '0') { |
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112 base = 8; |
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113 cp++; |
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114 if ((*cp == 'x') && isxdigit(cp[1])) { |
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115 cp++; |
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116 base = 16; |
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117 } |
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118 } |
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119 } |
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120 while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) |
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121 ? toupper(*cp) : *cp)-'A'+10) < base) { |
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122 result = result*base + value; |
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123 cp++; |
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124 } |
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125 if (endp) |
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126 *endp = (char *)cp; |
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127 return result; |
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128 } |
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129 |
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130 long simple_strtol(const char *cp,char **endp,unsigned int base) |
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131 { |
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132 if(*cp=='-') |
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133 return -simple_strtoul(cp+1,endp,base); |
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134 return simple_strtoul(cp,endp,base); |
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135 } |
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136 #endif |
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137 |
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138 |
1 | 139 typedef struct bes_registers_s |
140 { | |
141 //BES Control | |
142 uint32_t besctl; | |
143 //BES Global control | |
144 uint32_t besglobctl; | |
145 //Luma control (brightness and contrast) | |
146 uint32_t beslumactl; | |
147 //Line pitch | |
148 uint32_t bespitch; | |
149 | |
150 //Buffer A-1 Chroma 3 plane org | |
151 uint32_t besa1c3org; | |
152 //Buffer A-1 Chroma org | |
153 uint32_t besa1corg; | |
154 //Buffer A-1 Luma org | |
155 uint32_t besa1org; | |
156 | |
157 //Buffer A-2 Chroma 3 plane org | |
158 uint32_t besa2c3org; | |
159 //Buffer A-2 Chroma org | |
160 uint32_t besa2corg; | |
161 //Buffer A-2 Luma org | |
162 uint32_t besa2org; | |
163 | |
164 //Buffer B-1 Chroma 3 plane org | |
165 uint32_t besb1c3org; | |
166 //Buffer B-1 Chroma org | |
167 uint32_t besb1corg; | |
168 //Buffer B-1 Luma org | |
169 uint32_t besb1org; | |
170 | |
171 //Buffer B-2 Chroma 3 plane org | |
172 uint32_t besb2c3org; | |
173 //Buffer B-2 Chroma org | |
174 uint32_t besb2corg; | |
175 //Buffer B-2 Luma org | |
176 uint32_t besb2org; | |
177 | |
178 //BES Horizontal coord | |
179 uint32_t beshcoord; | |
180 //BES Horizontal inverse scaling [5.14] | |
181 uint32_t beshiscal; | |
182 //BES Horizontal source start [10.14] (for scaling) | |
183 uint32_t beshsrcst; | |
184 //BES Horizontal source ending [10.14] (for scaling) | |
185 uint32_t beshsrcend; | |
186 //BES Horizontal source last | |
187 uint32_t beshsrclst; | |
188 | |
189 | |
190 //BES Vertical coord | |
191 uint32_t besvcoord; | |
192 //BES Vertical inverse scaling [5.14] | |
193 uint32_t besviscal; | |
194 //BES Field 1 vertical source last position | |
195 uint32_t besv1srclst; | |
196 //BES Field 1 weight start | |
197 uint32_t besv1wght; | |
198 //BES Field 2 vertical source last position | |
199 uint32_t besv2srclst; | |
200 //BES Field 2 weight start | |
201 uint32_t besv2wght; | |
202 | |
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203 |
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204 //configurable stuff |
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205 int blackie; |
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206 |
1 | 207 } bes_registers_t; |
208 | |
209 static bes_registers_t regs; | |
2344 | 210 #ifdef CRTC2 |
211 typedef struct crtc2_registers_s | |
212 { | |
213 uint32_t c2ctl; | |
214 uint32_t c2datactl; | |
215 uint32_t c2misc; | |
216 uint32_t c2hparam; | |
217 uint32_t c2hsync; | |
218 uint32_t c2offset; | |
219 uint32_t c2pl2startadd0; | |
220 uint32_t c2pl2startadd1; | |
221 uint32_t c2pl3startadd0; | |
222 uint32_t c2pl3startadd1; | |
223 uint32_t c2preload; | |
224 uint32_t c2spicstartadd0; | |
225 uint32_t c2spicstartadd1; | |
226 uint32_t c2startadd0; | |
227 uint32_t c2startadd1; | |
228 uint32_t c2subpiclut; | |
229 uint32_t c2vcount; | |
230 uint32_t c2vparam; | |
231 uint32_t c2vsync; | |
232 } crtc2_registers_t; | |
233 static crtc2_registers_t cregs; | |
234 #endif | |
1 | 235 static uint32_t mga_vid_in_use = 0; |
236 static uint32_t is_g400 = 0; | |
237 static uint32_t vid_src_ready = 0; | |
238 static uint32_t vid_overlay_on = 0; | |
239 | |
240 static uint8_t *mga_mmio_base = 0; | |
241 static uint32_t mga_mem_base = 0; | |
242 | |
57 | 243 static int mga_src_base = 0; // YUV buffer position in video memory |
244 | |
245 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have | |
1 | 246 |
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247 static uint32_t mga_top_reserved = 0; // reserved space for console font (matroxfb + fastfont) |
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248 |
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249 static int mga_brightness = 0; // initial brightness |
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250 static int mga_contrast = 0; // initial contrast |
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251 |
95 | 252 //static int mga_force_memsize = 0; |
90 | 253 |
95 | 254 MODULE_PARM(mga_ram_size, "i"); |
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255 MODULE_PARM(mga_top_reserved, "i"); |
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256 MODULE_PARM(mga_brightness, "i"); |
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257 MODULE_PARM(mga_contrast, "i"); |
90 | 258 |
1 | 259 static struct pci_dev *pci_dev; |
260 | |
261 static mga_vid_config_t mga_config; | |
262 | |
2086 | 263 static int colkey_saved=0; |
264 static int colkey_on=0; | |
265 static unsigned char colkey_color[4]; | |
266 static unsigned char colkey_mask[4]; | |
267 | |
48 | 268 static int mga_irq = -1; |
1 | 269 |
270 //All register offsets are converted to word aligned offsets (32 bit) | |
271 //because we want all our register accesses to be 32 bits | |
272 #define VCOUNT 0x1e20 | |
273 | |
274 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
275 #define X_DATAREG 0x3c0a | |
276 | |
277 #define XMULCTRL 0x19 | |
278 #define BPP_8 0x00 | |
279 #define BPP_15 0x01 | |
280 #define BPP_16 0x02 | |
281 #define BPP_24 0x03 | |
282 #define BPP_32_DIR 0x04 | |
283 #define BPP_32_PAL 0x07 | |
284 | |
285 #define XCOLMSK 0x40 | |
286 #define X_COLKEY 0x42 | |
287 #define XKEYOPMODE 0x51 | |
288 #define XCOLMSK0RED 0x52 | |
289 #define XCOLMSK0GREEN 0x53 | |
290 #define XCOLMSK0BLUE 0x54 | |
291 #define XCOLKEY0RED 0x55 | |
292 #define XCOLKEY0GREEN 0x56 | |
293 #define XCOLKEY0BLUE 0x57 | |
294 | |
2344 | 295 #ifdef CRTC2 |
296 | |
297 /*CRTC2 registers*/ | |
298 #define XMISCCTRL 0x1e | |
299 #define C2CTL 0x3c10 | |
300 #define C2DATACTL 0x3c4c | |
301 #define C2MISC 0x3c44 | |
302 #define C2HPARAM 0x3c14 | |
303 #define C2HSYNC 0x3c18 | |
304 #define C2OFFSET 0x3c40 | |
305 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG | |
306 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG | |
307 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG | |
308 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG | |
309 #define C2PRELOAD 0x3c24 | |
310 #define C2SPICSTARTADD0 0x3c54 | |
311 #define C2SPICSTARTADD1 0x3c58 | |
312 #define C2STARTADD0 0x3c28 // like BESA1ORG | |
313 #define C2STARTADD1 0x3c2c // like BESA2ORG | |
314 #define C2SUBPICLUT 0x3c50 | |
315 #define C2VCOUNT 0x3c48 | |
316 #define C2VPARAM 0x3c1c | |
317 #define C2VSYNC 0x3c20 | |
318 | |
319 #endif | |
320 | |
1 | 321 // Backend Scaler registers |
322 #define BESCTL 0x3d20 | |
323 #define BESGLOBCTL 0x3dc0 | |
324 #define BESLUMACTL 0x3d40 | |
325 #define BESPITCH 0x3d24 | |
48 | 326 |
1 | 327 #define BESA1C3ORG 0x3d60 |
328 #define BESA1CORG 0x3d10 | |
329 #define BESA1ORG 0x3d00 | |
48 | 330 |
1 | 331 #define BESA2C3ORG 0x3d64 |
332 #define BESA2CORG 0x3d14 | |
333 #define BESA2ORG 0x3d04 | |
48 | 334 |
1 | 335 #define BESB1C3ORG 0x3d68 |
336 #define BESB1CORG 0x3d18 | |
337 #define BESB1ORG 0x3d08 | |
48 | 338 |
1 | 339 #define BESB2C3ORG 0x3d6C |
340 #define BESB2CORG 0x3d1C | |
341 #define BESB2ORG 0x3d0C | |
48 | 342 |
1 | 343 #define BESHCOORD 0x3d28 |
344 #define BESHISCAL 0x3d30 | |
345 #define BESHSRCEND 0x3d3C | |
346 #define BESHSRCLST 0x3d50 | |
347 #define BESHSRCST 0x3d38 | |
348 #define BESV1WGHT 0x3d48 | |
349 #define BESV2WGHT 0x3d4c | |
350 #define BESV1SRCLST 0x3d54 | |
351 #define BESV2SRCLST 0x3d58 | |
352 #define BESVISCAL 0x3d34 | |
353 #define BESVCOORD 0x3d2c | |
354 #define BESSTATUS 0x3dc4 | |
355 | |
48 | 356 #define CRTCX 0x1fd4 |
357 #define CRTCD 0x1fd5 | |
358 #define IEN 0x1e1c | |
359 #define ICLEAR 0x1e18 | |
360 #define STATUS 0x1e14 | |
361 | |
362 static int mga_next_frame=0; | |
1 | 363 |
2344 | 364 #ifdef CRTC2 |
365 static void crtc2_frame_sel(int frame) | |
366 { | |
367 switch(frame) { | |
368 case 0: | |
369 cregs.c2pl2startadd0=regs.besa1corg; | |
370 cregs.c2pl3startadd0=regs.besa1c3org; | |
371 cregs.c2startadd0=regs.besa1org; | |
372 break; | |
373 case 1: | |
374 cregs.c2pl2startadd0=regs.besa2corg; | |
375 cregs.c2pl3startadd0=regs.besa2c3org; | |
376 cregs.c2startadd0=regs.besa2org; | |
377 break; | |
378 case 2: | |
379 cregs.c2pl2startadd0=regs.besb1corg; | |
380 cregs.c2pl3startadd0=regs.besb1c3org; | |
381 cregs.c2startadd0=regs.besb1org; | |
382 break; | |
383 case 3: | |
384 cregs.c2pl2startadd0=regs.besb2corg; | |
385 cregs.c2pl3startadd0=regs.besb2c3org; | |
386 cregs.c2startadd0=regs.besb2org; | |
387 break; | |
388 } | |
389 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
390 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
391 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
392 } | |
393 #endif | |
394 | |
1 | 395 static void mga_vid_frame_sel(int frame) |
396 { | |
48 | 397 if ( mga_irq != -1 ) { |
398 mga_next_frame=frame; | |
399 } else { | |
400 | |
1 | 401 //we don't need the vcount protection as we're only hitting |
402 //one register (and it doesn't seem to be double buffered) | |
403 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); | |
404 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
68 | 405 |
406 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
407 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
408 mga_mmio_base + BESGLOBCTL); | |
2344 | 409 #ifdef CRTC2 |
410 crtc2_frame_sel(frame); | |
411 #endif | |
68 | 412 |
48 | 413 } |
1 | 414 } |
415 | |
416 | |
2086 | 417 static void mga_vid_write_regs(int restore) |
1 | 418 { |
419 //Make sure internal registers don't get updated until we're done | |
420 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
421 mga_mmio_base + BESGLOBCTL); | |
422 | |
423 // color or coordinate keying | |
2086 | 424 |
425 if(restore && colkey_saved){ | |
426 // restore it | |
427 colkey_saved=0; | |
428 | |
429 printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n", | |
430 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
431 | |
432 // Set color key registers: | |
433 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
434 writeb( colkey_on, mga_mmio_base + X_DATAREG); | |
435 | |
436 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
437 writeb( colkey_color[0], mga_mmio_base + X_DATAREG); | |
438 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
439 writeb( colkey_color[1], mga_mmio_base + X_DATAREG); | |
440 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
441 writeb( colkey_color[2], mga_mmio_base + X_DATAREG); | |
442 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
443 writeb( colkey_color[3], mga_mmio_base + X_DATAREG); | |
444 | |
445 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
446 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); | |
447 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
448 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); | |
449 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
450 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); | |
451 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
452 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); | |
453 | |
454 } else if(!colkey_saved){ | |
455 // save it | |
456 colkey_saved=1; | |
457 // Get color key registers: | |
458 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
459 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; | |
460 | |
461 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
462 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
463 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
464 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
465 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
466 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
467 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
468 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
469 | |
470 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
471 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
472 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
473 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
474 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
475 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
476 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
477 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
478 | |
479 printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n", | |
480 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
481 | |
482 } | |
483 | |
484 if(!restore){ | |
1 | 485 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); |
486 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG); | |
487 if ( mga_config.colkey_on ) | |
488 { | |
489 uint32_t r=0, g=0, b=0; | |
490 | |
491 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
492 switch (readb (mga_mmio_base + X_DATAREG)) | |
493 { | |
494 case BPP_8: | |
495 /* Need to look up the color index, just using | |
496 color 0 for now. */ | |
497 break; | |
498 | |
499 case BPP_15: | |
500 r = mga_config.colkey_red >> 3; | |
501 g = mga_config.colkey_green >> 3; | |
502 b = mga_config.colkey_blue >> 3; | |
503 break; | |
504 | |
505 case BPP_16: | |
506 r = mga_config.colkey_red >> 3; | |
507 g = mga_config.colkey_green >> 2; | |
508 b = mga_config.colkey_blue >> 3; | |
509 break; | |
510 | |
511 case BPP_24: | |
512 case BPP_32_DIR: | |
513 case BPP_32_PAL: | |
514 r = mga_config.colkey_red; | |
515 g = mga_config.colkey_green; | |
516 b = mga_config.colkey_blue; | |
517 break; | |
518 } | |
519 | |
520 // Disable color keying on alpha channel | |
521 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
522 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
523 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
524 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
525 | |
2086 | 526 |
1 | 527 // Set up color key registers |
528 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
529 writeb( r, mga_mmio_base + X_DATAREG); | |
530 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
531 writeb( g, mga_mmio_base + X_DATAREG); | |
532 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
533 writeb( b, mga_mmio_base + X_DATAREG); | |
534 | |
535 // Set up color key mask registers | |
536 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
537 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
538 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
539 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
540 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
541 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
542 } | |
543 | |
2086 | 544 } |
545 | |
1 | 546 // Backend Scaler |
547 writel( regs.besctl, mga_mmio_base + BESCTL); | |
548 if(is_g400) | |
549 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
550 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
551 | |
552 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
553 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
48 | 554 writel( regs.besa2org, mga_mmio_base + BESA2ORG); |
555 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
1 | 556 writel( regs.besb1org, mga_mmio_base + BESB1ORG); |
557 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
48 | 558 writel( regs.besb2org, mga_mmio_base + BESB2ORG); |
559 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
1 | 560 if(is_g400) |
561 { | |
562 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
48 | 563 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); |
1 | 564 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); |
48 | 565 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); |
1 | 566 } |
567 | |
568 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
569 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
570 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
571 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
572 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
573 | |
574 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
575 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
48 | 576 |
1 | 577 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); |
578 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
48 | 579 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); |
580 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
1 | 581 |
582 //update the registers somewhere between 1 and 2 frames from now. | |
583 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
584 mga_mmio_base + BESGLOBCTL); | |
585 | |
77 | 586 #if 0 |
61 | 587 printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); |
588 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", | |
1 | 589 readl(mga_mmio_base + BESCTL)); |
61 | 590 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", |
1 | 591 readl(mga_mmio_base + BESGLOBCTL)); |
61 | 592 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", |
1 | 593 readl(mga_mmio_base + BESSTATUS)); |
77 | 594 #endif |
2344 | 595 #ifdef CRTC2 |
596 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); | |
597 // printk("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); | |
598 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl); | |
599 | |
600 // writel(cregs.c2ctl, mga_mmio_base + C2CTL); | |
601 | |
602 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); | |
603 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); | |
604 // ctrc2 | |
605 // disable CRTC2 acording to specs | |
606 // writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL); | |
607 // je to treba ??? | |
608 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel | |
609 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL); | |
610 // writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL); | |
611 // writel(cregs.c2datactl, mga_mmio_base + C2DATACTL); | |
612 // writel(cregs.c2hparam, mga_mmio_base + C2HPARAM); | |
613 // writel(cregs.c2hsync, mga_mmio_base + C2HSYNC); | |
614 // writel(cregs.c2vparam, mga_mmio_base + C2VPARAM); | |
615 // writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); | |
616 writel(cregs.c2misc, mga_mmio_base + C2MISC); | |
617 | |
618 printk("c2offset = %d\n",cregs.c2offset); | |
619 | |
620 writel(cregs.c2offset, mga_mmio_base + C2OFFSET); | |
621 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
622 // writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1); | |
623 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
624 // writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1); | |
625 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
626 // writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1); | |
627 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); | |
628 // writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1); | |
629 // writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT); | |
630 // writel(cregs.c2preload, mga_mmio_base + C2PRELOAD); | |
631 // finaly enable everything | |
632 // writel(cregs.c2ctl, mga_mmio_base + C2CTL); | |
633 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); | |
634 // printk("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC)); | |
635 #endif | |
1 | 636 } |
637 | |
638 static int mga_vid_set_config(mga_vid_config_t *config) | |
639 { | |
640 int x, y, sw, sh, dw, dh; | |
641 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
57 | 642 int frame_size=config->frame_size; |
2344 | 643 #ifdef CRTC2 |
644 #define right_margin 0 | |
645 #define left_margin 18 | |
646 #define hsync_len 46 | |
647 #define lower_margin 10 | |
648 #define vsync_len 4 | |
649 #define upper_margin 39 | |
650 | |
651 unsigned int hdispend = (config->src_width + 31) & ~31; | |
652 unsigned int hsyncstart = hdispend + (right_margin & ~7); | |
653 unsigned int hsyncend = hsyncstart + (hsync_len & ~7); | |
654 unsigned int htotal = hsyncend + (left_margin & ~7); | |
655 unsigned int vdispend = config->src_height; | |
656 unsigned int vsyncstart = vdispend + lower_margin; | |
657 unsigned int vsyncend = vsyncstart + vsync_len; | |
658 unsigned int vtotal = vsyncend + upper_margin; | |
659 #endif | |
1 | 660 x = config->x_org; |
661 y = config->y_org; | |
662 sw = config->src_width; | |
663 sh = config->src_height; | |
664 dw = config->dest_width; | |
665 dh = config->dest_height; | |
666 | |
61 | 667 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", |
1 | 668 dw, dh, x, y, sw, sh, config->format); |
669 | |
3959 | 670 if(sw<4 || sh<4 || dw<4 || dh<4){ |
671 printk(KERN_ERR "mga_vid: Invalid src/dest dimenstions\n"); | |
672 return -1; | |
673 } | |
674 | |
1 | 675 //FIXME check that window is valid and inside desktop |
676 | |
677 //FIXME figure out a better way to allocate memory on card | |
678 //allocate 2 megs | |
679 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; | |
57 | 680 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; |
1 | 681 |
682 | |
683 //Setup the BES registers for a three plane 4:2:0 video source | |
684 | |
466 | 685 regs.besglobctl = 0; |
686 | |
1 | 687 switch(config->format){ |
688 case MGA_VID_FORMAT_YV12: | |
470 | 689 case MGA_VID_FORMAT_I420: |
690 case MGA_VID_FORMAT_IYUV: | |
1 | 691 regs.besctl = 1 // BES enabled |
692 + (0<<6) // even start polarity | |
693 + (1<<10) // x filtering enabled | |
694 + (1<<11) // y filtering enabled | |
695 + (1<<16) // chroma upsampling | |
696 + (1<<17) // 4:2:0 mode | |
697 + (1<<18); // dither enabled | |
466 | 698 #if 0 |
1 | 699 if(is_g400) |
700 { | |
701 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp | |
702 //disabled, rgb mode disabled | |
703 regs.besglobctl = (1<<5); | |
704 } | |
705 else | |
706 { | |
707 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr | |
708 //in 1357, BES register update on besvcnt | |
466 | 709 regs.besglobctl = 0; |
1 | 710 } |
466 | 711 #endif |
1 | 712 break; |
713 | |
714 case MGA_VID_FORMAT_YUY2: | |
715 regs.besctl = 1 // BES enabled | |
716 + (0<<6) // even start polarity | |
717 + (1<<10) // x filtering enabled | |
718 + (1<<11) // y filtering enabled | |
719 + (1<<16) // chroma upsampling | |
720 + (0<<17) // 4:2:2 mode | |
721 + (1<<18); // dither enabled | |
722 | |
723 regs.besglobctl = 0; // YUY2 format selected | |
724 break; | |
466 | 725 |
726 case MGA_VID_FORMAT_UYVY: | |
727 regs.besctl = 1 // BES enabled | |
728 + (0<<6) // even start polarity | |
729 + (1<<10) // x filtering enabled | |
730 + (1<<11) // y filtering enabled | |
731 + (1<<16) // chroma upsampling | |
732 + (0<<17) // 4:2:2 mode | |
733 + (1<<18); // dither enabled | |
734 | |
735 regs.besglobctl = 1<<6; // UYVY format selected | |
736 break; | |
737 | |
1 | 738 default: |
61 | 739 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); |
1 | 740 return -1; |
741 } | |
742 | |
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743 // setting black&white mode |
4484 | 744 regs.besctl|=(regs.blackie<<20); |
1 | 745 |
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746 //Enable contrast and brightness control |
466 | 747 regs.besglobctl |= (1<<5) + (1<<7); |
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748 |
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749 // brightness ; default is 0x7f; |
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750 regs.beslumactl = (mga_brightness << 16); |
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751 // contrast: |
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752 regs.beslumactl|= ((mga_contrast+0x80)<<0); |
1 | 753 |
754 //Setup destination window boundaries | |
755 besleft = x > 0 ? x : 0; | |
756 bestop = y > 0 ? y : 0; | |
757 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
758 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
759 | |
760 //Setup source dimensions | |
761 regs.beshsrclst = (sw - 1) << 16; | |
762 regs.bespitch = (sw + 31) & ~31 ; | |
763 | |
764 //Setup horizontal scaling | |
765 ifactor = ((sw-1)<<14)/(dw-1); | |
766 ofsleft = besleft - x; | |
767 | |
768 regs.beshiscal = ifactor<<2; | |
769 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
770 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
771 | |
772 //Setup vertical scaling | |
773 ifactor = ((sh-1)<<14)/(dh-1); | |
774 ofstop = bestop - y; | |
775 | |
776 regs.besviscal = ifactor<<2; | |
777 | |
778 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
57 | 779 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; |
1 | 780 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; |
48 | 781 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size; |
782 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size; | |
783 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size; | |
1 | 784 |
470 | 785 if(config->format==MGA_VID_FORMAT_YV12 |
786 ||config->format==MGA_VID_FORMAT_IYUV | |
787 ||config->format==MGA_VID_FORMAT_I420 | |
788 ){ | |
57 | 789 // planar YUV frames: |
1 | 790 if (is_g400) |
791 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
792 else | |
793 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
794 | |
5336 | 795 if(config->format==MGA_VID_FORMAT_YV12 || !is_g400){ |
1 | 796 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; |
48 | 797 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; |
798 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
799 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
1 | 800 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); |
48 | 801 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); |
1 | 802 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); |
48 | 803 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); |
470 | 804 } else { |
805 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
806 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; | |
807 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
808 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
809 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); | |
810 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); | |
811 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); | |
812 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); | |
813 } | |
814 | |
57 | 815 } |
1 | 816 |
817 weight = ofstop * (regs.besviscal >> 2); | |
818 weights = weight < 0 ? 1 : 0; | |
48 | 819 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); |
820 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
1 | 821 |
2344 | 822 #ifdef CRTC2 |
823 // pridat hlavni registry - tj. casovani ... | |
824 | |
825 | |
826 switch(config->format){ | |
827 case MGA_VID_FORMAT_YV12: | |
828 case MGA_VID_FORMAT_I420: | |
829 case MGA_VID_FORMAT_IYUV: | |
830 cregs.c2ctl = 1 // CRTC2 enabled | |
831 + (1<<1) // external clock | |
832 + (0<<2) // external clock | |
833 + (1<<3) // pixel clock enable - not needed ??? | |
834 + (0<<4) // high prioryty req | |
835 + (1<<5) // high prioryty req | |
836 + (0<<6) // high prioryty req | |
837 + (1<<8) // high prioryty req max | |
838 + (0<<9) // high prioryty req max | |
839 + (0<<10) // high prioryty req max | |
840 + (0<<20) // CRTC1 to DAC | |
841 + (1<<21) // 420 mode | |
842 + (1<<22) // 420 mode | |
843 + (1<<23) // 420 mode | |
844 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
845 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
846 + (0<<26) // field legth polariry | |
847 + (0<<27) // field identification polariry | |
848 + (1<<28) // VIDRST detection mode | |
849 + (0<<29) // VIDRST detection mode | |
850 + (1<<30) // Horizontal counter preload | |
851 + (1<<31) // Vertical counter preload | |
852 ; | |
853 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
854 + (1<<1) // Y filter enable | |
855 + (1<<2) // CbCr filter enable | |
856 + (0<<3) // subpicture enable (disabled) | |
857 + (0<<4) // NTSC enable (disabled - PAL) | |
858 + (0<<5) // C2 static subpicture enable (disabled) | |
859 + (0<<6) // C2 subpicture offset division (disabled) | |
860 + (0<<7) // 422 subformat selection ! | |
861 /* + (0<<8) // 15 bpp high alpha | |
862 + (0<<9) // 15 bpp high alpha | |
863 + (0<<10) // 15 bpp high alpha | |
864 + (0<<11) // 15 bpp high alpha | |
865 + (0<<12) // 15 bpp high alpha | |
866 + (0<<13) // 15 bpp high alpha | |
867 + (0<<14) // 15 bpp high alpha | |
868 + (0<<15) // 15 bpp high alpha | |
869 + (0<<16) // 15 bpp low alpha | |
870 + (0<<17) // 15 bpp low alpha | |
871 + (0<<18) // 15 bpp low alpha | |
872 + (0<<19) // 15 bpp low alpha | |
873 + (0<<20) // 15 bpp low alpha | |
874 + (0<<21) // 15 bpp low alpha | |
875 + (0<<22) // 15 bpp low alpha | |
876 + (0<<23) // 15 bpp low alpha | |
877 + (0<<24) // static subpicture key | |
878 + (0<<25) // static subpicture key | |
879 + (0<<26) // static subpicture key | |
880 + (0<<27) // static subpicture key | |
881 + (0<<28) // static subpicture key | |
882 */ ; | |
883 break; | |
884 | |
885 case MGA_VID_FORMAT_YUY2: | |
886 cregs.c2ctl = 1 // CRTC2 enabled | |
887 + (1<<1) // external clock | |
888 + (0<<2) // external clock | |
889 + (1<<3) // pixel clock enable - not needed ??? | |
890 + (0<<4) // high prioryty req - acc to spec | |
891 + (1<<5) // high prioryty req | |
892 + (0<<6) // high prioryty req | |
893 // 7 reserved | |
894 + (1<<8) // high prioryty req max | |
895 + (0<<9) // high prioryty req max | |
896 + (0<<10) // high prioryty req max | |
897 // 11-19 reserved | |
898 + (0<<20) // CRTC1 to DAC | |
899 + (1<<21) // 422 mode | |
900 + (0<<22) // 422 mode | |
901 + (1<<23) // 422 mode | |
902 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
903 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
904 + (0<<26) // field legth polariry | |
905 + (0<<27) // field identification polariry | |
906 + (1<<28) // VIDRST detection mode | |
907 + (0<<29) // VIDRST detection mode | |
908 + (1<<30) // Horizontal counter preload | |
909 + (1<<31) // Vertical counter preload | |
910 ; | |
911 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
912 + (1<<1) // Y filter enable | |
913 + (1<<2) // CbCr filter enable | |
914 + (0<<3) // subpicture enable (disabled) | |
915 + (0<<4) // NTSC enable (disabled - PAL) | |
916 + (0<<5) // C2 static subpicture enable (disabled) | |
917 + (0<<6) // C2 subpicture offset division (disabled) | |
918 + (0<<7) // 422 subformat selection ! | |
919 /* + (0<<8) // 15 bpp high alpha | |
920 + (0<<9) // 15 bpp high alpha | |
921 + (0<<10) // 15 bpp high alpha | |
922 + (0<<11) // 15 bpp high alpha | |
923 + (0<<12) // 15 bpp high alpha | |
924 + (0<<13) // 15 bpp high alpha | |
925 + (0<<14) // 15 bpp high alpha | |
926 + (0<<15) // 15 bpp high alpha | |
927 + (0<<16) // 15 bpp low alpha | |
928 + (0<<17) // 15 bpp low alpha | |
929 + (0<<18) // 15 bpp low alpha | |
930 + (0<<19) // 15 bpp low alpha | |
931 + (0<<20) // 15 bpp low alpha | |
932 + (0<<21) // 15 bpp low alpha | |
933 + (0<<22) // 15 bpp low alpha | |
934 + (0<<23) // 15 bpp low alpha | |
935 + (0<<24) // static subpicture key | |
936 + (0<<25) // static subpicture key | |
937 + (0<<26) // static subpicture key | |
938 + (0<<27) // static subpicture key | |
939 + (0<<28) // static subpicture key | |
940 */ ; | |
941 break; | |
942 | |
943 case MGA_VID_FORMAT_UYVY: | |
944 cregs.c2ctl = 1 // CRTC2 enabled | |
945 + (1<<1) // external clock | |
946 + (0<<2) // external clock | |
947 + (1<<3) // pixel clock enable - not needed ??? | |
948 + (0<<4) // high prioryty req | |
949 + (1<<5) // high prioryty req | |
950 + (0<<6) // high prioryty req | |
951 + (1<<8) // high prioryty req max | |
952 + (0<<9) // high prioryty req max | |
953 + (0<<10) // high prioryty req max | |
954 + (0<<20) // CRTC1 to DAC | |
955 + (1<<21) // 422 mode | |
956 + (0<<22) // 422 mode | |
957 + (1<<23) // 422 mode | |
958 + (1<<24) // single chroma line for 420 mode - need to be corrected | |
959 + (1<<25) /*/ interlace mode - need to be corrected*/ | |
960 + (0<<26) // field legth polariry | |
961 + (0<<27) // field identification polariry | |
962 + (1<<28) // VIDRST detection mode | |
963 + (0<<29) // VIDRST detection mode | |
964 + (1<<30) // Horizontal counter preload | |
965 + (1<<31) // Vertical counter preload | |
966 ; | |
967 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode | |
968 + (1<<1) // Y filter enable | |
969 + (1<<2) // CbCr filter enable | |
970 + (0<<3) // subpicture enable (disabled) | |
971 + (0<<4) // NTSC enable (disabled - PAL) | |
972 + (0<<5) // C2 static subpicture enable (disabled) | |
973 + (0<<6) // C2 subpicture offset division (disabled) | |
974 + (1<<7) // 422 subformat selection ! | |
975 /* + (0<<8) // 15 bpp high alpha | |
976 + (0<<9) // 15 bpp high alpha | |
977 + (0<<10) // 15 bpp high alpha | |
978 + (0<<11) // 15 bpp high alpha | |
979 + (0<<12) // 15 bpp high alpha | |
980 + (0<<13) // 15 bpp high alpha | |
981 + (0<<14) // 15 bpp high alpha | |
982 + (0<<15) // 15 bpp high alpha | |
983 + (0<<16) // 15 bpp low alpha | |
984 + (0<<17) // 15 bpp low alpha | |
985 + (0<<18) // 15 bpp low alpha | |
986 + (0<<19) // 15 bpp low alpha | |
987 + (0<<20) // 15 bpp low alpha | |
988 + (0<<21) // 15 bpp low alpha | |
989 + (0<<22) // 15 bpp low alpha | |
990 + (0<<23) // 15 bpp low alpha | |
991 + (0<<24) // static subpicture key | |
992 + (0<<25) // static subpicture key | |
993 + (0<<26) // static subpicture key | |
994 + (0<<27) // static subpicture key | |
995 + (0<<28) // static subpicture key | |
996 */ ; | |
997 break; | |
998 | |
999 default: | |
1000 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); | |
1001 return -1; | |
1002 } | |
1003 | |
1004 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); | |
1005 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); | |
1006 | |
1007 cregs.c2misc=0 // CRTCV2 656 togg f0 | |
1008 +(0<<1) // CRTCV2 656 togg f0 | |
1009 +(0<<2) // CRTCV2 656 togg f0 | |
1010 +(0<<4) // CRTCV2 656 togg f1 | |
1011 +(0<<5) // CRTCV2 656 togg f1 | |
1012 +(0<<6) // CRTCV2 656 togg f1 | |
1013 +(0<<8) // Hsync active high | |
1014 +(0<<9) // Vsync active high | |
1015 // 16-27 c2vlinecomp - nevim co tam dat | |
1016 ; | |
1017 cregs.c2offset=(regs.bespitch << 1); | |
1018 | |
1019 cregs.c2pl2startadd0=regs.besa1corg; | |
1020 // cregs.c2pl2startadd1=regs.besa2corg; | |
1021 cregs.c2pl3startadd0=regs.besa1c3org; | |
1022 // cregs.c2pl3startadd1=regs.besa2c3org; | |
1023 | |
1024 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from | |
1025 | |
1026 cregs.c2spicstartadd0=0; // not used | |
1027 // cregs.c2spicstartadd1=0; // not used | |
1028 | |
1029 cregs.c2startadd0=regs.besa1org; | |
1030 // cregs.c2startadd1=regs.besa2org; | |
1031 | |
1032 cregs.c2subpiclut=0; //not used | |
1033 | |
1034 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); | |
1035 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); | |
1036 | |
1037 | |
1038 #endif | |
1039 | |
2086 | 1040 mga_vid_write_regs(0); |
1 | 1041 return 0; |
1042 } | |
1043 | |
68 | 1044 #ifdef MGA_ALLOW_IRQ |
1045 | |
48 | 1046 static void enable_irq(){ |
1047 long int cc; | |
1048 | |
1049 cc = readl(mga_mmio_base + IEN); | |
63 | 1050 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff)); |
48 | 1051 |
1052 writeb( 0x11, mga_mmio_base + CRTCX); | |
1053 | |
1054 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
1055 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
1056 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
1057 | |
1058 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
1059 | |
1060 } | |
1061 | |
1062 static void disable_irq(){ | |
1063 | |
1064 writeb( 0x11, mga_mmio_base + CRTCX); | |
1065 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
1066 | |
1067 } | |
1068 | |
1069 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) { | |
1070 // static int frame=0; | |
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1071 // static int counter=0; |
48 | 1072 long int cc; |
1073 // if ( ! mga_enabled_flag ) return; | |
1074 | |
68 | 1075 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
1076 | |
48 | 1077 //printk("mga_interrupt #%d\n", irq); |
1078 | |
1079 if ( irq != -1 ) { | |
1080 | |
1081 cc = readl(mga_mmio_base + STATUS); | |
1082 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
1083 // debug_irqcnt++; | |
1084 } | |
1085 | |
1086 // if ( debug_irqignore ) { | |
1087 // debug_irqignore = 0; | |
1088 | |
1089 | |
1090 /* | |
1091 if ( mga_conf_deinterlace ) { | |
1092 if ( mga_first_field ) { | |
1093 // printk("mga_interrupt first field\n"); | |
1094 if ( syncfb_interrupt() ) | |
1095 mga_first_field = 0; | |
1096 } else { | |
1097 // printk("mga_interrupt second field\n"); | |
1098 mga_select_buffer( mga_current_field | 2 ); | |
1099 mga_first_field = 1; | |
1100 } | |
1101 } else { | |
1102 syncfb_interrupt(); | |
1103 } | |
1104 */ | |
1105 | |
1106 // frame=(frame+1)&1; | |
1107 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
1108 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
2344 | 1109 |
1110 #ifdef CRTC2 | |
1111 // sem pridat vyber obrazku !!!! | |
1112 crtc2_frame_sel(mga_next_frame); | |
1113 #endif | |
48 | 1114 |
1115 #if 0 | |
1116 ++counter; | |
1117 if(!(counter&63)){ | |
1118 printk("mga irq counter = %d\n",counter); | |
1119 } | |
1120 #endif | |
1121 | |
1122 // } else { | |
1123 // debug_irqignore = 1; | |
1124 // } | |
1125 | |
1126 if ( irq != -1 ) { | |
1127 writeb( 0x11, mga_mmio_base + CRTCX); | |
1128 writeb( 0, mga_mmio_base + CRTCD ); | |
1129 writeb( 0x10, mga_mmio_base + CRTCD ); | |
1130 } | |
1131 | |
1132 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); | |
1133 | |
1134 | |
1135 return; | |
1136 | |
1137 } | |
1138 | |
68 | 1139 #endif |
1 | 1140 |
1141 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
1142 { | |
1143 int frame; | |
5013
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1144 uint32_t tmp; |
52c008dd6e93
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1145 |
1 | 1146 |
1147 switch(cmd) | |
1148 { | |
1149 case MGA_VID_CONFIG: | |
1150 //FIXME remove | |
68 | 1151 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
61 | 1152 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base); |
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1153 printk(KERN_DEBUG "mga_mem_base = %08x\n",mga_mem_base); |
1 | 1154 //FIXME remove |
1155 | |
61 | 1156 printk(KERN_DEBUG "mga_vid: Received configuration\n"); |
1 | 1157 |
1158 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
1159 { | |
61 | 1160 printk(KERN_ERR "mga_vid: failed copy from userspace\n"); |
1 | 1161 return(-EFAULT); |
1162 } | |
57 | 1163 if(mga_config.version != MGA_VID_VERSION){ |
61 | 1164 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version); |
57 | 1165 return(-EFAULT); |
1166 } | |
1167 | |
1168 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){ | |
61 | 1169 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size); |
57 | 1170 return(-EFAULT); |
1171 } | |
1172 | |
1173 if(mga_config.num_frames<1 || mga_config.num_frames>4){ | |
61 | 1174 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames); |
57 | 1175 return(-EFAULT); |
1176 } | |
1177 | |
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1178 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size-mga_top_reserved); |
57 | 1179 if(mga_src_base<0){ |
61 | 1180 printk(KERN_ERR "mga_vid: not enough memory for frames!\n"); |
57 | 1181 return(-EFAULT); |
1182 } | |
1183 mga_src_base &= (~0xFFFF); // 64k boundary | |
61 | 1184 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base); |
57 | 1185 |
1 | 1186 if (is_g400) |
1187 mga_config.card_type = MGA_G400; | |
1188 else | |
1189 mga_config.card_type = MGA_G200; | |
1190 | |
1191 mga_config.ram_size = mga_ram_size; | |
1192 | |
1193 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t))) | |
1194 { | |
61 | 1195 printk(KERN_ERR "mga_vid: failed copy to userspace\n"); |
1 | 1196 return(-EFAULT); |
1197 } | |
1198 return mga_vid_set_config(&mga_config); | |
1199 break; | |
1200 | |
1201 case MGA_VID_ON: | |
61 | 1202 printk(KERN_DEBUG "mga_vid: Video ON\n"); |
1 | 1203 vid_src_ready = 1; |
1204 if(vid_overlay_on) | |
1205 { | |
1206 regs.besctl |= 1; | |
2086 | 1207 mga_vid_write_regs(0); |
1 | 1208 } |
68 | 1209 #ifdef MGA_ALLOW_IRQ |
48 | 1210 if ( mga_irq != -1 ) enable_irq(); |
68 | 1211 #endif |
48 | 1212 mga_next_frame=0; |
1 | 1213 break; |
1214 | |
1215 case MGA_VID_OFF: | |
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1216 printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n"); |
1 | 1217 vid_src_ready = 0; |
68 | 1218 #ifdef MGA_ALLOW_IRQ |
48 | 1219 if ( mga_irq != -1 ) disable_irq(); |
68 | 1220 #endif |
1 | 1221 regs.besctl &= ~1; |
466 | 1222 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 1223 mga_vid_write_regs(0); |
1 | 1224 break; |
1225 | |
1226 case MGA_VID_FSEL: | |
1227 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
1228 { | |
61 | 1229 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n"); |
1 | 1230 return(-EFAULT); |
1231 } | |
1232 | |
1233 mga_vid_frame_sel(frame); | |
1234 break; | |
1235 | |
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1236 case MGA_VID_GET_LUMA: |
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1237 tmp = regs.beslumactl - 0x80; |
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1238 if (copy_to_user((uint32_t *) arg, &tmp, sizeof(uint32_t))) |
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1239 { |
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1240 printk(KERN_ERR "mga_vid: failed copy %p to userspace %p\n", |
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1241 &tmp, (uint32_t *) arg); |
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1242 return(-EFAULT); |
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1243 } |
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|
1244 break; |
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1245 |
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1246 case MGA_VID_SET_LUMA: |
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1247 tmp = arg; |
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1248 regs.beslumactl = tmp + 0x80; |
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1249 mga_vid_write_regs(0); |
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1250 break; |
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1251 |
1 | 1252 default: |
61 | 1253 printk(KERN_ERR "mga_vid: Invalid ioctl\n"); |
1 | 1254 return (-EINVAL); |
1255 } | |
1256 | |
1257 return 0; | |
1258 } | |
1259 | |
1260 | |
1261 static int mga_vid_find_card(void) | |
1262 { | |
1263 struct pci_dev *dev = NULL; | |
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1264 unsigned int card_option; |
1 | 1265 |
1989 | 1266 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, NULL))) |
1267 { | |
1268 is_g400 = 1; | |
1269 printk(KERN_INFO "mga_vid: Found MGA G550\n"); | |
1270 } | |
1271 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL))) | |
1 | 1272 { |
1273 is_g400 = 1; | |
77 | 1274 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n"); |
1 | 1275 } |
1276 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL))) | |
1277 { | |
1278 is_g400 = 0; | |
63 | 1279 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n"); |
1 | 1280 } |
1281 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL))) | |
1282 { | |
1283 is_g400 = 0; | |
63 | 1284 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n"); |
1 | 1285 } |
1286 else | |
1287 { | |
61 | 1288 printk(KERN_ERR "mga_vid: No supported cards found\n"); |
1 | 1289 return FALSE; |
1290 } | |
1291 | |
1292 pci_dev = dev; | |
48 | 1293 |
1294 mga_irq = pci_dev->irq; | |
1 | 1295 |
1296 #if LINUX_VERSION_CODE >= 0x020300 | |
1297 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000); | |
1298 mga_mem_base = dev->resource[0].start; | |
1299 #else | |
1300 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000); | |
1301 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; | |
1302 #endif | |
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1303 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", mga_mmio_base, mga_irq, mga_mem_base); |
1 | 1304 |
1305 pci_read_config_dword(dev, 0x40, &card_option); | |
77 | 1306 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, |
1307 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1 | 1308 |
57 | 1309 // temp = (card_option >> 10) & 0x17; |
1310 | |
95 | 1311 if (mga_ram_size) { |
1312 printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size); | |
91 | 1313 } else { |
90 | 1314 |
101
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1315 #ifdef MGA_MEMORY_SIZE |
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1316 mga_ram_size = MGA_MEMORY_SIZE; |
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1317 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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1318 |
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1319 #else |
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1320 |
95 | 1321 if (is_g400){ |
75 | 1322 switch((card_option>>10)&0x17){ |
1323 // SDRAM: | |
1324 case 0x00: | |
1325 case 0x04: mga_ram_size = 16; break; | |
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1326 case 0x03: |
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1327 case 0x05: mga_ram_size = 32; break; |
75 | 1328 // SGRAM: |
1329 case 0x10: | |
1330 case 0x14: mga_ram_size = 32; break; | |
1331 case 0x11: | |
1332 case 0x12: mga_ram_size = 16; break; | |
1333 default: | |
1334 mga_ram_size = 16; | |
1335 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!"); | |
1336 } | |
95 | 1337 }else{ |
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1338 switch((card_option>>10)&0x17){ |
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1339 // case 0x10: |
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1340 // case 0x13: mga_ram_size = 8; break; |
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1341 default: mga_ram_size = 8; |
64 | 1342 } |
95 | 1343 } |
64 | 1344 #if 0 |
95 | 1345 // printk("List resources -----------\n"); |
1346 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ | |
1347 struct resource *res=&pci_dev->resource[temp]; | |
1348 if(res->flags){ | |
1349 int size=(1+res->end-res->start)>>20; | |
1350 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); | |
1351 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ | |
1352 if(size>mga_ram_size && size<=64) mga_ram_size=size; | |
1353 } | |
1354 } | |
57 | 1355 } |
64 | 1356 #endif |
95 | 1357 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
101
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1358 #endif |
95 | 1359 } |
57 | 1360 |
48 | 1361 |
68 | 1362 #ifdef MGA_ALLOW_IRQ |
48 | 1363 if ( mga_irq != -1 ) { |
1364 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
1365 if ( tmp ) { | |
61 | 1366 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); |
48 | 1367 mga_irq=-1; |
1368 } else { | |
61 | 1369 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq); |
48 | 1370 } |
1371 } else { | |
61 | 1372 printk(KERN_INFO "syncfb (mga): No valid irq was found\n"); |
48 | 1373 mga_irq=-1; |
1374 } | |
68 | 1375 #else |
1376 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
1377 mga_irq=-1; | |
1378 #endif | |
48 | 1379 |
1 | 1380 return TRUE; |
1381 } | |
1382 | |
4484 | 1383 static void mga_param_buff_fill( void ) |
1384 { | |
1385 unsigned len; | |
1386 len = 0; | |
1387 len += sprintf(&mga_param_buff[len],"Interface version: %04X\n",MGA_VID_VERSION); | |
4527 | 1388 len += sprintf(&mga_param_buff[len],"Memory: %x:%dM\n",mga_mem_base,(unsigned int) mga_ram_size); |
4484 | 1389 len += sprintf(&mga_param_buff[len],"MMIO: %p\n",mga_mmio_base); |
1390 len += sprintf(&mga_param_buff[len],"Configurable stuff:\n"); | |
1391 len += sprintf(&mga_param_buff[len],"~~~~~~~~~~~~~~~~~~~\n"); | |
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1392 len += sprintf(&mga_param_buff[len],PARAM_BRIGHTNESS"%d\n",mga_brightness); |
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1393 len += sprintf(&mga_param_buff[len],PARAM_CONTRAST"%d\n",mga_contrast); |
4484 | 1394 len += sprintf(&mga_param_buff[len],PARAM_BLACKIE"%s\n",regs.blackie?"on":"off"); |
1395 mga_param_buff_len = len; | |
4527 | 1396 // check boundaries of mga_param_buff before writing to it!!! |
4484 | 1397 } |
1398 | |
1 | 1399 |
1400 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
1401 { | |
4484 | 1402 uint32_t size; |
1403 if(!mga_param_buff) return -ESPIPE; | |
1404 if(!(*ppos)) mga_param_buff_fill(); | |
1405 if(*ppos >= mga_param_buff_len) return 0; | |
1406 size = min(count,mga_param_buff_len-(uint32_t)(*ppos)); | |
1407 memcpy(buf,mga_param_buff,size); | |
1408 *ppos += size; | |
1409 return size; | |
1 | 1410 } |
1411 | |
1412 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
1413 { | |
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1414 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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1415 { |
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1416 short brightness; |
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1417 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
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1418 if (brightness>127 || brightness<-128) { brightness=0;} |
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1419 // printk(KERN_DEBUG "mga_vid: brightness modified ( %d ) \n",brightness); |
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1420 mga_brightness=brightness; |
4483
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1421 } else |
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1422 if(memcmp(buf,PARAM_CONTRAST,min(count,strlen(PARAM_CONTRAST))) == 0) |
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1423 { |
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1424 short contrast; |
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1425 contrast=simple_strtol(&buf[strlen(PARAM_CONTRAST)],NULL,10); |
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1426 if (contrast>127 || contrast<-128) { contrast=0;} |
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1427 // printk(KERN_DEBUG "mga_vid: contrast modified ( %d ) \n",contrast); |
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1428 mga_contrast=contrast; |
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1429 } else |
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1430 |
4483
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1431 if(memcmp(buf,PARAM_BLACKIE,min(count,strlen(PARAM_BLACKIE))) == 0) |
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1432 { |
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1433 short blackie; |
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1434 blackie=simple_strtol(&buf[strlen(PARAM_BLACKIE)],NULL,10); |
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1435 // printk(KERN_DEBUG "mga_vid: shadow mode: ( %d ) \n",blackie); |
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1436 regs.blackie=(blackie>0)?1:0; |
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1437 } else count = -EIO; |
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1438 // TODO: reset settings |
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1439 return count; |
1 | 1440 } |
1441 | |
1442 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
1443 { | |
1444 | |
61 | 1445 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n"); |
57 | 1446 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base, |
1 | 1447 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
1448 { | |
63 | 1449 printk(KERN_ERR "mga_vid: error mapping video memory\n"); |
1 | 1450 return(-EAGAIN); |
1451 } | |
1452 | |
1453 return(0); | |
1454 } | |
1455 | |
1456 static int mga_vid_release(struct inode *inode, struct file *file) | |
1457 { | |
1458 //Close the window just in case | |
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1459 printk(KERN_DEBUG "mga_vid: Video OFF (release)\n"); |
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1460 |
1 | 1461 vid_src_ready = 0; |
1462 regs.besctl &= ~1; | |
466 | 1463 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 1464 // mga_config.colkey_on=0; //!!! |
1465 mga_vid_write_regs(1); | |
1 | 1466 mga_vid_in_use = 0; |
1467 | |
93 | 1468 MOD_DEC_USE_COUNT; |
1 | 1469 return 0; |
1470 } | |
1471 | |
1472 static long long mga_vid_lseek(struct file *file, long long offset, int origin) | |
1473 { | |
1474 return -ESPIPE; | |
1475 } | |
1476 | |
1477 static int mga_vid_open(struct inode *inode, struct file *file) | |
1478 { | |
1479 int minor = MINOR(inode->i_rdev); | |
1480 | |
1481 if(minor != 0) | |
1482 return(-ENXIO); | |
1483 | |
1484 if(mga_vid_in_use == 1) | |
1485 return(-EBUSY); | |
1486 | |
1487 mga_vid_in_use = 1; | |
93 | 1488 MOD_INC_USE_COUNT; |
1 | 1489 return(0); |
1490 } | |
1491 | |
1492 #if LINUX_VERSION_CODE >= 0x020400 | |
1493 static struct file_operations mga_vid_fops = | |
1494 { | |
1495 llseek: mga_vid_lseek, | |
1496 read: mga_vid_read, | |
1497 write: mga_vid_write, | |
1498 ioctl: mga_vid_ioctl, | |
1499 mmap: mga_vid_mmap, | |
1500 open: mga_vid_open, | |
1501 release: mga_vid_release | |
1502 }; | |
1503 #else | |
1504 static struct file_operations mga_vid_fops = | |
1505 { | |
1506 mga_vid_lseek, | |
1507 mga_vid_read, | |
1508 mga_vid_write, | |
1509 NULL, | |
1510 NULL, | |
1511 mga_vid_ioctl, | |
1512 mga_vid_mmap, | |
1513 mga_vid_open, | |
1514 NULL, | |
1515 mga_vid_release | |
1516 }; | |
1517 #endif | |
1518 | |
1519 | |
1520 /* | |
1521 * Main Initialization Function | |
1522 */ | |
1523 | |
1524 static int mga_vid_initialize(void) | |
1525 { | |
1526 mga_vid_in_use = 0; | |
1527 | |
77 | 1528 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n"); |
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1529 printk(KERN_INFO "Matrox MGA G200/G400/G450/G550 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); |
90 | 1530 |
95 | 1531 if (mga_ram_size) { |
1532 if (mga_ram_size<4 || mga_ram_size>64) { | |
1533 printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size); | |
90 | 1534 return -EINVAL; |
1535 } | |
1536 } | |
1537 | |
1 | 1538 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops)) |
1539 { | |
61 | 1540 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR); |
1 | 1541 return -EIO; |
1542 } | |
1543 | |
1544 if (!mga_vid_find_card()) | |
1545 { | |
61 | 1546 printk(KERN_ERR "mga_vid: no supported devices found\n"); |
1 | 1547 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1548 return -EINVAL; | |
1549 } | |
4484 | 1550 mga_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL); |
1551 if(mga_param_buff) mga_param_buff_size = PARAM_BUFF_SIZE; | |
1 | 1552 |
1553 return(0); | |
1554 } | |
1555 | |
1556 int init_module(void) | |
1557 { | |
1558 return mga_vid_initialize(); | |
1559 } | |
1560 | |
1561 void cleanup_module(void) | |
1562 { | |
48 | 1563 |
68 | 1564 #ifdef MGA_ALLOW_IRQ |
48 | 1565 if ( mga_irq != -1) |
1566 free_irq(mga_irq, &mga_irq); | |
68 | 1567 #endif |
48 | 1568 |
1 | 1569 if(mga_mmio_base) |
1570 iounmap(mga_mmio_base); | |
4520 | 1571 if(mga_param_buff) |
1572 kfree(mga_param_buff); | |
1 | 1573 |
1574 //FIXME turn off BES | |
63 | 1575 printk(KERN_INFO "mga_vid: Cleaning up module\n"); |
1 | 1576 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1577 } | |
1578 |