Mercurial > mplayer.hg
annotate drivers/mga_vid.c @ 4483:fb4b914eab8a
framework for settings modifications like in radeon_vid ( /dev/mga_vid can
be written to ).
Brightness and chroma control.
author | eyck |
---|---|
date | Sat, 02 Feb 2002 20:49:52 +0000 |
parents | 72d8a4d0de18 |
children | c150a35fd22b |
rev | line source |
---|---|
2345 | 1 //#define CRTC2 |
2 | |
1 | 3 // YUY2 support (see config.format) added by A'rpi/ESP-team |
57 | 4 // double buffering added by A'rpi/ESP-team |
5 | |
6 // Set this value, if autodetection fails! (video ram size in megabytes) | |
91 | 7 // #define MGA_MEMORY_SIZE 16 |
1 | 8 |
68 | 9 //#define MGA_ALLOW_IRQ |
10 | |
11 #define MGA_VSYNC_POS 2 | |
12 | |
1 | 13 /* |
14 * | |
15 * mga_vid.c | |
16 * | |
17 * Copyright (C) 1999 Aaron Holtzman | |
18 * | |
19 * Module skeleton based on gutted agpgart module by Jeff Hartmann | |
20 * <slicer@ionet.net> | |
21 * | |
22 * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 | |
23 * | |
24 * BES == Back End Scaler | |
25 * | |
26 * This software has been released under the terms of the GNU Public | |
27 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
28 */ | |
29 | |
30 //It's entirely possible this major conflicts with something else | |
31 /* mknod /dev/mga_vid c 178 0 */ | |
32 | |
33 #include <linux/config.h> | |
34 #include <linux/version.h> | |
35 #include <linux/module.h> | |
36 #include <linux/types.h> | |
37 #include <linux/kernel.h> | |
38 #include <linux/sched.h> | |
39 #include <linux/mm.h> | |
40 #include <linux/string.h> | |
41 #include <linux/errno.h> | |
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42 |
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43 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,10) |
1 | 44 #include <linux/malloc.h> |
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45 #else |
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46 #include <linux/slab.h> |
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47 #endif |
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48 |
1 | 49 #include <linux/pci.h> |
63 | 50 #include <linux/ioport.h> |
1 | 51 #include <linux/init.h> |
52 | |
53 #include "mga_vid.h" | |
54 | |
55 #ifdef CONFIG_MTRR | |
56 #include <asm/mtrr.h> | |
57 #endif | |
58 | |
59 #include <asm/uaccess.h> | |
60 #include <asm/system.h> | |
61 #include <asm/io.h> | |
62 | |
63 #define TRUE 1 | |
64 #define FALSE 0 | |
65 | |
66 #define MGA_VID_MAJOR 178 | |
67 | |
57 | 68 //#define MGA_VIDMEM_SIZE mga_ram_size |
1 | 69 |
70 #ifndef PCI_DEVICE_ID_MATROX_G200_PCI | |
71 #define PCI_DEVICE_ID_MATROX_G200_PCI 0x0520 | |
72 #endif | |
73 | |
74 #ifndef PCI_DEVICE_ID_MATROX_G200_AGP | |
75 #define PCI_DEVICE_ID_MATROX_G200_AGP 0x0521 | |
76 #endif | |
77 | |
78 #ifndef PCI_DEVICE_ID_MATROX_G400 | |
79 #define PCI_DEVICE_ID_MATROX_G400 0x0525 | |
80 #endif | |
81 | |
1989 | 82 #ifndef PCI_DEVICE_ID_MATROX_G550 |
83 #define PCI_DEVICE_ID_MATROX_G550 0x2527 | |
84 #endif | |
85 | |
1 | 86 MODULE_AUTHOR("Aaron Holtzman <aholtzma@engr.uvic.ca>"); |
2262 | 87 #ifdef MODULE_LICENSE |
88 MODULE_LICENSE("GPL"); | |
89 #endif | |
1 | 90 |
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91 // WARNING - eyck changes |
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92 #define PARAM_BRIGHTNESS "brightness=" |
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93 #define PARAM_SATURATION "saturation=" |
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94 #define PARAM_BLACKIE "blackie=" |
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95 // end eyck |
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96 |
1 | 97 typedef struct bes_registers_s |
98 { | |
99 //BES Control | |
100 uint32_t besctl; | |
101 //BES Global control | |
102 uint32_t besglobctl; | |
103 //Luma control (brightness and contrast) | |
104 uint32_t beslumactl; | |
105 //Line pitch | |
106 uint32_t bespitch; | |
107 | |
108 //Buffer A-1 Chroma 3 plane org | |
109 uint32_t besa1c3org; | |
110 //Buffer A-1 Chroma org | |
111 uint32_t besa1corg; | |
112 //Buffer A-1 Luma org | |
113 uint32_t besa1org; | |
114 | |
115 //Buffer A-2 Chroma 3 plane org | |
116 uint32_t besa2c3org; | |
117 //Buffer A-2 Chroma org | |
118 uint32_t besa2corg; | |
119 //Buffer A-2 Luma org | |
120 uint32_t besa2org; | |
121 | |
122 //Buffer B-1 Chroma 3 plane org | |
123 uint32_t besb1c3org; | |
124 //Buffer B-1 Chroma org | |
125 uint32_t besb1corg; | |
126 //Buffer B-1 Luma org | |
127 uint32_t besb1org; | |
128 | |
129 //Buffer B-2 Chroma 3 plane org | |
130 uint32_t besb2c3org; | |
131 //Buffer B-2 Chroma org | |
132 uint32_t besb2corg; | |
133 //Buffer B-2 Luma org | |
134 uint32_t besb2org; | |
135 | |
136 //BES Horizontal coord | |
137 uint32_t beshcoord; | |
138 //BES Horizontal inverse scaling [5.14] | |
139 uint32_t beshiscal; | |
140 //BES Horizontal source start [10.14] (for scaling) | |
141 uint32_t beshsrcst; | |
142 //BES Horizontal source ending [10.14] (for scaling) | |
143 uint32_t beshsrcend; | |
144 //BES Horizontal source last | |
145 uint32_t beshsrclst; | |
146 | |
147 | |
148 //BES Vertical coord | |
149 uint32_t besvcoord; | |
150 //BES Vertical inverse scaling [5.14] | |
151 uint32_t besviscal; | |
152 //BES Field 1 vertical source last position | |
153 uint32_t besv1srclst; | |
154 //BES Field 1 weight start | |
155 uint32_t besv1wght; | |
156 //BES Field 2 vertical source last position | |
157 uint32_t besv2srclst; | |
158 //BES Field 2 weight start | |
159 uint32_t besv2wght; | |
160 | |
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161 |
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162 //configurable stuff |
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163 int brightness; |
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164 int blackie; |
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165 |
1 | 166 } bes_registers_t; |
167 | |
168 static bes_registers_t regs; | |
2344 | 169 #ifdef CRTC2 |
170 typedef struct crtc2_registers_s | |
171 { | |
172 uint32_t c2ctl; | |
173 uint32_t c2datactl; | |
174 uint32_t c2misc; | |
175 uint32_t c2hparam; | |
176 uint32_t c2hsync; | |
177 uint32_t c2offset; | |
178 uint32_t c2pl2startadd0; | |
179 uint32_t c2pl2startadd1; | |
180 uint32_t c2pl3startadd0; | |
181 uint32_t c2pl3startadd1; | |
182 uint32_t c2preload; | |
183 uint32_t c2spicstartadd0; | |
184 uint32_t c2spicstartadd1; | |
185 uint32_t c2startadd0; | |
186 uint32_t c2startadd1; | |
187 uint32_t c2subpiclut; | |
188 uint32_t c2vcount; | |
189 uint32_t c2vparam; | |
190 uint32_t c2vsync; | |
191 } crtc2_registers_t; | |
192 static crtc2_registers_t cregs; | |
193 #endif | |
1 | 194 static uint32_t mga_vid_in_use = 0; |
195 static uint32_t is_g400 = 0; | |
196 static uint32_t vid_src_ready = 0; | |
197 static uint32_t vid_overlay_on = 0; | |
198 | |
199 static uint8_t *mga_mmio_base = 0; | |
200 static uint32_t mga_mem_base = 0; | |
201 | |
57 | 202 static int mga_src_base = 0; // YUV buffer position in video memory |
203 | |
204 static uint32_t mga_ram_size = 0; // how much megabytes videoram we have | |
1 | 205 |
95 | 206 //static int mga_force_memsize = 0; |
90 | 207 |
95 | 208 MODULE_PARM(mga_ram_size, "i"); |
90 | 209 |
1 | 210 static struct pci_dev *pci_dev; |
211 | |
212 static mga_vid_config_t mga_config; | |
213 | |
2086 | 214 static int colkey_saved=0; |
215 static int colkey_on=0; | |
216 static unsigned char colkey_color[4]; | |
217 static unsigned char colkey_mask[4]; | |
218 | |
48 | 219 static int mga_irq = -1; |
1 | 220 |
221 //All register offsets are converted to word aligned offsets (32 bit) | |
222 //because we want all our register accesses to be 32 bits | |
223 #define VCOUNT 0x1e20 | |
224 | |
225 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
226 #define X_DATAREG 0x3c0a | |
227 | |
228 #define XMULCTRL 0x19 | |
229 #define BPP_8 0x00 | |
230 #define BPP_15 0x01 | |
231 #define BPP_16 0x02 | |
232 #define BPP_24 0x03 | |
233 #define BPP_32_DIR 0x04 | |
234 #define BPP_32_PAL 0x07 | |
235 | |
236 #define XCOLMSK 0x40 | |
237 #define X_COLKEY 0x42 | |
238 #define XKEYOPMODE 0x51 | |
239 #define XCOLMSK0RED 0x52 | |
240 #define XCOLMSK0GREEN 0x53 | |
241 #define XCOLMSK0BLUE 0x54 | |
242 #define XCOLKEY0RED 0x55 | |
243 #define XCOLKEY0GREEN 0x56 | |
244 #define XCOLKEY0BLUE 0x57 | |
245 | |
2344 | 246 #ifdef CRTC2 |
247 | |
248 /*CRTC2 registers*/ | |
249 #define XMISCCTRL 0x1e | |
250 #define C2CTL 0x3c10 | |
251 #define C2DATACTL 0x3c4c | |
252 #define C2MISC 0x3c44 | |
253 #define C2HPARAM 0x3c14 | |
254 #define C2HSYNC 0x3c18 | |
255 #define C2OFFSET 0x3c40 | |
256 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG | |
257 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG | |
258 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG | |
259 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG | |
260 #define C2PRELOAD 0x3c24 | |
261 #define C2SPICSTARTADD0 0x3c54 | |
262 #define C2SPICSTARTADD1 0x3c58 | |
263 #define C2STARTADD0 0x3c28 // like BESA1ORG | |
264 #define C2STARTADD1 0x3c2c // like BESA2ORG | |
265 #define C2SUBPICLUT 0x3c50 | |
266 #define C2VCOUNT 0x3c48 | |
267 #define C2VPARAM 0x3c1c | |
268 #define C2VSYNC 0x3c20 | |
269 | |
270 #endif | |
271 | |
1 | 272 // Backend Scaler registers |
273 #define BESCTL 0x3d20 | |
274 #define BESGLOBCTL 0x3dc0 | |
275 #define BESLUMACTL 0x3d40 | |
276 #define BESPITCH 0x3d24 | |
48 | 277 |
1 | 278 #define BESA1C3ORG 0x3d60 |
279 #define BESA1CORG 0x3d10 | |
280 #define BESA1ORG 0x3d00 | |
48 | 281 |
1 | 282 #define BESA2C3ORG 0x3d64 |
283 #define BESA2CORG 0x3d14 | |
284 #define BESA2ORG 0x3d04 | |
48 | 285 |
1 | 286 #define BESB1C3ORG 0x3d68 |
287 #define BESB1CORG 0x3d18 | |
288 #define BESB1ORG 0x3d08 | |
48 | 289 |
1 | 290 #define BESB2C3ORG 0x3d6C |
291 #define BESB2CORG 0x3d1C | |
292 #define BESB2ORG 0x3d0C | |
48 | 293 |
1 | 294 #define BESHCOORD 0x3d28 |
295 #define BESHISCAL 0x3d30 | |
296 #define BESHSRCEND 0x3d3C | |
297 #define BESHSRCLST 0x3d50 | |
298 #define BESHSRCST 0x3d38 | |
299 #define BESV1WGHT 0x3d48 | |
300 #define BESV2WGHT 0x3d4c | |
301 #define BESV1SRCLST 0x3d54 | |
302 #define BESV2SRCLST 0x3d58 | |
303 #define BESVISCAL 0x3d34 | |
304 #define BESVCOORD 0x3d2c | |
305 #define BESSTATUS 0x3dc4 | |
306 | |
48 | 307 #define CRTCX 0x1fd4 |
308 #define CRTCD 0x1fd5 | |
309 #define IEN 0x1e1c | |
310 #define ICLEAR 0x1e18 | |
311 #define STATUS 0x1e14 | |
312 | |
313 static int mga_next_frame=0; | |
1 | 314 |
2344 | 315 #ifdef CRTC2 |
316 static void crtc2_frame_sel(int frame) | |
317 { | |
318 switch(frame) { | |
319 case 0: | |
320 cregs.c2pl2startadd0=regs.besa1corg; | |
321 cregs.c2pl3startadd0=regs.besa1c3org; | |
322 cregs.c2startadd0=regs.besa1org; | |
323 break; | |
324 case 1: | |
325 cregs.c2pl2startadd0=regs.besa2corg; | |
326 cregs.c2pl3startadd0=regs.besa2c3org; | |
327 cregs.c2startadd0=regs.besa2org; | |
328 break; | |
329 case 2: | |
330 cregs.c2pl2startadd0=regs.besb1corg; | |
331 cregs.c2pl3startadd0=regs.besb1c3org; | |
332 cregs.c2startadd0=regs.besb1org; | |
333 break; | |
334 case 3: | |
335 cregs.c2pl2startadd0=regs.besb2corg; | |
336 cregs.c2pl3startadd0=regs.besb2c3org; | |
337 cregs.c2startadd0=regs.besb2org; | |
338 break; | |
339 } | |
340 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
341 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
342 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
343 } | |
344 #endif | |
345 | |
1 | 346 static void mga_vid_frame_sel(int frame) |
347 { | |
48 | 348 if ( mga_irq != -1 ) { |
349 mga_next_frame=frame; | |
350 } else { | |
351 | |
1 | 352 //we don't need the vcount protection as we're only hitting |
353 //one register (and it doesn't seem to be double buffered) | |
354 regs.besctl = (regs.besctl & ~0x07000000) + (frame << 25); | |
355 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
68 | 356 |
357 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
358 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
359 mga_mmio_base + BESGLOBCTL); | |
2344 | 360 #ifdef CRTC2 |
361 crtc2_frame_sel(frame); | |
362 #endif | |
68 | 363 |
48 | 364 } |
1 | 365 } |
366 | |
367 | |
2086 | 368 static void mga_vid_write_regs(int restore) |
1 | 369 { |
370 //Make sure internal registers don't get updated until we're done | |
371 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
372 mga_mmio_base + BESGLOBCTL); | |
373 | |
374 // color or coordinate keying | |
2086 | 375 |
376 if(restore && colkey_saved){ | |
377 // restore it | |
378 colkey_saved=0; | |
379 | |
380 printk("mga_vid: Restoring colorkey (ON: %d %02X:%02X:%02X)\n", | |
381 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
382 | |
383 // Set color key registers: | |
384 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
385 writeb( colkey_on, mga_mmio_base + X_DATAREG); | |
386 | |
387 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
388 writeb( colkey_color[0], mga_mmio_base + X_DATAREG); | |
389 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
390 writeb( colkey_color[1], mga_mmio_base + X_DATAREG); | |
391 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
392 writeb( colkey_color[2], mga_mmio_base + X_DATAREG); | |
393 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
394 writeb( colkey_color[3], mga_mmio_base + X_DATAREG); | |
395 | |
396 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
397 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); | |
398 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
399 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); | |
400 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
401 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); | |
402 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
403 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); | |
404 | |
405 } else if(!colkey_saved){ | |
406 // save it | |
407 colkey_saved=1; | |
408 // Get color key registers: | |
409 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
410 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; | |
411 | |
412 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
413 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
414 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
415 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
416 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
417 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
418 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
419 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
420 | |
421 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
422 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
423 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
424 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
425 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
426 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
427 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
428 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
429 | |
430 printk("mga_vid: Saved colorkey (ON: %d %02X:%02X:%02X)\n", | |
431 colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); | |
432 | |
433 } | |
434 | |
435 if(!restore){ | |
1 | 436 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); |
437 writeb( mga_config.colkey_on, mga_mmio_base + X_DATAREG); | |
438 if ( mga_config.colkey_on ) | |
439 { | |
440 uint32_t r=0, g=0, b=0; | |
441 | |
442 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
443 switch (readb (mga_mmio_base + X_DATAREG)) | |
444 { | |
445 case BPP_8: | |
446 /* Need to look up the color index, just using | |
447 color 0 for now. */ | |
448 break; | |
449 | |
450 case BPP_15: | |
451 r = mga_config.colkey_red >> 3; | |
452 g = mga_config.colkey_green >> 3; | |
453 b = mga_config.colkey_blue >> 3; | |
454 break; | |
455 | |
456 case BPP_16: | |
457 r = mga_config.colkey_red >> 3; | |
458 g = mga_config.colkey_green >> 2; | |
459 b = mga_config.colkey_blue >> 3; | |
460 break; | |
461 | |
462 case BPP_24: | |
463 case BPP_32_DIR: | |
464 case BPP_32_PAL: | |
465 r = mga_config.colkey_red; | |
466 g = mga_config.colkey_green; | |
467 b = mga_config.colkey_blue; | |
468 break; | |
469 } | |
470 | |
471 // Disable color keying on alpha channel | |
472 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
473 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
474 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
475 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
476 | |
2086 | 477 |
1 | 478 // Set up color key registers |
479 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
480 writeb( r, mga_mmio_base + X_DATAREG); | |
481 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
482 writeb( g, mga_mmio_base + X_DATAREG); | |
483 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
484 writeb( b, mga_mmio_base + X_DATAREG); | |
485 | |
486 // Set up color key mask registers | |
487 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
488 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
489 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
490 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
491 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
492 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
493 } | |
494 | |
2086 | 495 } |
496 | |
1 | 497 // Backend Scaler |
498 writel( regs.besctl, mga_mmio_base + BESCTL); | |
499 if(is_g400) | |
500 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
501 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
502 | |
503 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
504 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
48 | 505 writel( regs.besa2org, mga_mmio_base + BESA2ORG); |
506 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
1 | 507 writel( regs.besb1org, mga_mmio_base + BESB1ORG); |
508 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
48 | 509 writel( regs.besb2org, mga_mmio_base + BESB2ORG); |
510 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
1 | 511 if(is_g400) |
512 { | |
513 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
48 | 514 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); |
1 | 515 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); |
48 | 516 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); |
1 | 517 } |
518 | |
519 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
520 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
521 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
522 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
523 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
524 | |
525 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
526 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
48 | 527 |
1 | 528 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); |
529 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
48 | 530 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); |
531 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
1 | 532 |
533 //update the registers somewhere between 1 and 2 frames from now. | |
534 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
535 mga_mmio_base + BESGLOBCTL); | |
536 | |
77 | 537 #if 0 |
61 | 538 printk(KERN_DEBUG "mga_vid: wrote BES registers\n"); |
539 printk(KERN_DEBUG "mga_vid: BESCTL = 0x%08x\n", | |
1 | 540 readl(mga_mmio_base + BESCTL)); |
61 | 541 printk(KERN_DEBUG "mga_vid: BESGLOBCTL = 0x%08x\n", |
1 | 542 readl(mga_mmio_base + BESGLOBCTL)); |
61 | 543 printk(KERN_DEBUG "mga_vid: BESSTATUS= 0x%08x\n", |
1 | 544 readl(mga_mmio_base + BESSTATUS)); |
77 | 545 #endif |
2344 | 546 #ifdef CRTC2 |
547 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); | |
548 // printk("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); | |
549 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl); | |
550 | |
551 // writel(cregs.c2ctl, mga_mmio_base + C2CTL); | |
552 | |
553 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); | |
554 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); | |
555 // ctrc2 | |
556 // disable CRTC2 acording to specs | |
557 // writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL); | |
558 // je to treba ??? | |
559 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel | |
560 // writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL); | |
561 // writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL); | |
562 // writel(cregs.c2datactl, mga_mmio_base + C2DATACTL); | |
563 // writel(cregs.c2hparam, mga_mmio_base + C2HPARAM); | |
564 // writel(cregs.c2hsync, mga_mmio_base + C2HSYNC); | |
565 // writel(cregs.c2vparam, mga_mmio_base + C2VPARAM); | |
566 // writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); | |
567 writel(cregs.c2misc, mga_mmio_base + C2MISC); | |
568 | |
569 printk("c2offset = %d\n",cregs.c2offset); | |
570 | |
571 writel(cregs.c2offset, mga_mmio_base + C2OFFSET); | |
572 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
573 // writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1); | |
574 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
575 // writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1); | |
576 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
577 // writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1); | |
578 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); | |
579 // writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1); | |
580 // writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT); | |
581 // writel(cregs.c2preload, mga_mmio_base + C2PRELOAD); | |
582 // finaly enable everything | |
583 // writel(cregs.c2ctl, mga_mmio_base + C2CTL); | |
584 // printk("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); | |
585 // printk("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC)); | |
586 #endif | |
1 | 587 } |
588 | |
589 static int mga_vid_set_config(mga_vid_config_t *config) | |
590 { | |
591 int x, y, sw, sh, dw, dh; | |
592 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
57 | 593 int frame_size=config->frame_size; |
2344 | 594 #ifdef CRTC2 |
595 #define right_margin 0 | |
596 #define left_margin 18 | |
597 #define hsync_len 46 | |
598 #define lower_margin 10 | |
599 #define vsync_len 4 | |
600 #define upper_margin 39 | |
601 | |
602 unsigned int hdispend = (config->src_width + 31) & ~31; | |
603 unsigned int hsyncstart = hdispend + (right_margin & ~7); | |
604 unsigned int hsyncend = hsyncstart + (hsync_len & ~7); | |
605 unsigned int htotal = hsyncend + (left_margin & ~7); | |
606 unsigned int vdispend = config->src_height; | |
607 unsigned int vsyncstart = vdispend + lower_margin; | |
608 unsigned int vsyncend = vsyncstart + vsync_len; | |
609 unsigned int vtotal = vsyncend + upper_margin; | |
610 #endif | |
1 | 611 x = config->x_org; |
612 y = config->y_org; | |
613 sw = config->src_width; | |
614 sh = config->src_height; | |
615 dw = config->dest_width; | |
616 dh = config->dest_height; | |
617 | |
61 | 618 printk(KERN_DEBUG "mga_vid: Setting up a %dx%d+%d+%d video window (src %dx%d) format %X\n", |
1 | 619 dw, dh, x, y, sw, sh, config->format); |
620 | |
3959 | 621 if(sw<4 || sh<4 || dw<4 || dh<4){ |
622 printk(KERN_ERR "mga_vid: Invalid src/dest dimenstions\n"); | |
623 return -1; | |
624 } | |
625 | |
1 | 626 //FIXME check that window is valid and inside desktop |
627 | |
628 //FIXME figure out a better way to allocate memory on card | |
629 //allocate 2 megs | |
630 //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; | |
57 | 631 //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; |
1 | 632 |
633 | |
634 //Setup the BES registers for a three plane 4:2:0 video source | |
635 | |
466 | 636 regs.besglobctl = 0; |
637 | |
1 | 638 switch(config->format){ |
639 case MGA_VID_FORMAT_YV12: | |
470 | 640 case MGA_VID_FORMAT_I420: |
641 case MGA_VID_FORMAT_IYUV: | |
1 | 642 regs.besctl = 1 // BES enabled |
643 + (0<<6) // even start polarity | |
644 + (1<<10) // x filtering enabled | |
645 + (1<<11) // y filtering enabled | |
646 + (1<<16) // chroma upsampling | |
647 + (1<<17) // 4:2:0 mode | |
648 + (1<<18); // dither enabled | |
466 | 649 #if 0 |
1 | 650 if(is_g400) |
651 { | |
652 //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp | |
653 //disabled, rgb mode disabled | |
654 regs.besglobctl = (1<<5); | |
655 } | |
656 else | |
657 { | |
658 //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr | |
659 //in 1357, BES register update on besvcnt | |
466 | 660 regs.besglobctl = 0; |
1 | 661 } |
466 | 662 #endif |
1 | 663 break; |
664 | |
665 case MGA_VID_FORMAT_YUY2: | |
666 regs.besctl = 1 // BES enabled | |
667 + (0<<6) // even start polarity | |
668 + (1<<10) // x filtering enabled | |
669 + (1<<11) // y filtering enabled | |
670 + (1<<16) // chroma upsampling | |
671 + (0<<17) // 4:2:2 mode | |
672 + (1<<18); // dither enabled | |
673 | |
674 regs.besglobctl = 0; // YUY2 format selected | |
675 break; | |
466 | 676 |
677 case MGA_VID_FORMAT_UYVY: | |
678 regs.besctl = 1 // BES enabled | |
679 + (0<<6) // even start polarity | |
680 + (1<<10) // x filtering enabled | |
681 + (1<<11) // y filtering enabled | |
682 + (1<<16) // chroma upsampling | |
683 + (0<<17) // 4:2:2 mode | |
684 + (1<<18); // dither enabled | |
685 | |
686 regs.besglobctl = 1<<6; // UYVY format selected | |
687 break; | |
688 | |
1 | 689 default: |
61 | 690 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); |
1 | 691 return -1; |
692 } | |
693 | |
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694 // setting black&white mode |
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695 regs.besctl|=(regs.blackie<<20); // TODO: check g200 & g400 (maybe tomorrow) |
1 | 696 |
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697 //Enable contrast and brightness control |
466 | 698 regs.besglobctl |= (1<<5) + (1<<7); |
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699 |
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700 // brightness ; default is 0x7f; |
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701 regs.beslumactl = (regs.brightness << 16); |
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702 // contrast: |
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703 regs.beslumactl|= (0x80<<0); |
1 | 704 |
705 //Setup destination window boundaries | |
706 besleft = x > 0 ? x : 0; | |
707 bestop = y > 0 ? y : 0; | |
708 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
709 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
710 | |
711 //Setup source dimensions | |
712 regs.beshsrclst = (sw - 1) << 16; | |
713 regs.bespitch = (sw + 31) & ~31 ; | |
714 | |
715 //Setup horizontal scaling | |
716 ifactor = ((sw-1)<<14)/(dw-1); | |
717 ofsleft = besleft - x; | |
718 | |
719 regs.beshiscal = ifactor<<2; | |
720 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
721 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
722 | |
723 //Setup vertical scaling | |
724 ifactor = ((sh-1)<<14)/(dh-1); | |
725 ofstop = bestop - y; | |
726 | |
727 regs.besviscal = ifactor<<2; | |
728 | |
729 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
57 | 730 //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; |
1 | 731 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; |
48 | 732 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size; |
733 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size; | |
734 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size; | |
1 | 735 |
470 | 736 if(config->format==MGA_VID_FORMAT_YV12 |
737 ||config->format==MGA_VID_FORMAT_IYUV | |
738 ||config->format==MGA_VID_FORMAT_I420 | |
739 ){ | |
57 | 740 // planar YUV frames: |
1 | 741 if (is_g400) |
742 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
743 else | |
744 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
745 | |
470 | 746 if(config->format==MGA_VID_FORMAT_YV12){ |
1 | 747 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; |
48 | 748 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; |
749 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
750 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
1 | 751 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); |
48 | 752 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); |
1 | 753 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); |
48 | 754 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); |
470 | 755 } else { |
756 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
757 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*frame_size + regs.bespitch * sh; | |
758 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*frame_size + regs.bespitch * sh; | |
759 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*frame_size + regs.bespitch * sh; | |
760 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); | |
761 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); | |
762 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); | |
763 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); | |
764 } | |
765 | |
57 | 766 } |
1 | 767 |
768 weight = ofstop * (regs.besviscal >> 2); | |
769 weights = weight < 0 ? 1 : 0; | |
48 | 770 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); |
771 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
1 | 772 |
2344 | 773 #ifdef CRTC2 |
774 // pridat hlavni registry - tj. casovani ... | |
775 | |
776 | |
777 switch(config->format){ | |
778 case MGA_VID_FORMAT_YV12: | |
779 case MGA_VID_FORMAT_I420: | |
780 case MGA_VID_FORMAT_IYUV: | |
781 cregs.c2ctl = 1 // CRTC2 enabled | |
782 + (1<<1) // external clock | |
783 + (0<<2) // external clock | |
784 + (1<<3) // pixel clock enable - not needed ??? | |
785 + (0<<4) // high prioryty req | |
786 + (1<<5) // high prioryty req | |
787 + (0<<6) // high prioryty req | |
788 + (1<<8) // high prioryty req max | |
789 + (0<<9) // high prioryty req max | |
790 + (0<<10) // high prioryty req max | |
791 + (0<<20) // CRTC1 to DAC | |
792 + (1<<21) // 420 mode | |
793 + (1<<22) // 420 mode | |
794 + (1<<23) // 420 mode | |
795 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
796 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
797 + (0<<26) // field legth polariry | |
798 + (0<<27) // field identification polariry | |
799 + (1<<28) // VIDRST detection mode | |
800 + (0<<29) // VIDRST detection mode | |
801 + (1<<30) // Horizontal counter preload | |
802 + (1<<31) // Vertical counter preload | |
803 ; | |
804 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
805 + (1<<1) // Y filter enable | |
806 + (1<<2) // CbCr filter enable | |
807 + (0<<3) // subpicture enable (disabled) | |
808 + (0<<4) // NTSC enable (disabled - PAL) | |
809 + (0<<5) // C2 static subpicture enable (disabled) | |
810 + (0<<6) // C2 subpicture offset division (disabled) | |
811 + (0<<7) // 422 subformat selection ! | |
812 /* + (0<<8) // 15 bpp high alpha | |
813 + (0<<9) // 15 bpp high alpha | |
814 + (0<<10) // 15 bpp high alpha | |
815 + (0<<11) // 15 bpp high alpha | |
816 + (0<<12) // 15 bpp high alpha | |
817 + (0<<13) // 15 bpp high alpha | |
818 + (0<<14) // 15 bpp high alpha | |
819 + (0<<15) // 15 bpp high alpha | |
820 + (0<<16) // 15 bpp low alpha | |
821 + (0<<17) // 15 bpp low alpha | |
822 + (0<<18) // 15 bpp low alpha | |
823 + (0<<19) // 15 bpp low alpha | |
824 + (0<<20) // 15 bpp low alpha | |
825 + (0<<21) // 15 bpp low alpha | |
826 + (0<<22) // 15 bpp low alpha | |
827 + (0<<23) // 15 bpp low alpha | |
828 + (0<<24) // static subpicture key | |
829 + (0<<25) // static subpicture key | |
830 + (0<<26) // static subpicture key | |
831 + (0<<27) // static subpicture key | |
832 + (0<<28) // static subpicture key | |
833 */ ; | |
834 break; | |
835 | |
836 case MGA_VID_FORMAT_YUY2: | |
837 cregs.c2ctl = 1 // CRTC2 enabled | |
838 + (1<<1) // external clock | |
839 + (0<<2) // external clock | |
840 + (1<<3) // pixel clock enable - not needed ??? | |
841 + (0<<4) // high prioryty req - acc to spec | |
842 + (1<<5) // high prioryty req | |
843 + (0<<6) // high prioryty req | |
844 // 7 reserved | |
845 + (1<<8) // high prioryty req max | |
846 + (0<<9) // high prioryty req max | |
847 + (0<<10) // high prioryty req max | |
848 // 11-19 reserved | |
849 + (0<<20) // CRTC1 to DAC | |
850 + (1<<21) // 422 mode | |
851 + (0<<22) // 422 mode | |
852 + (1<<23) // 422 mode | |
853 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
854 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
855 + (0<<26) // field legth polariry | |
856 + (0<<27) // field identification polariry | |
857 + (1<<28) // VIDRST detection mode | |
858 + (0<<29) // VIDRST detection mode | |
859 + (1<<30) // Horizontal counter preload | |
860 + (1<<31) // Vertical counter preload | |
861 ; | |
862 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
863 + (1<<1) // Y filter enable | |
864 + (1<<2) // CbCr filter enable | |
865 + (0<<3) // subpicture enable (disabled) | |
866 + (0<<4) // NTSC enable (disabled - PAL) | |
867 + (0<<5) // C2 static subpicture enable (disabled) | |
868 + (0<<6) // C2 subpicture offset division (disabled) | |
869 + (0<<7) // 422 subformat selection ! | |
870 /* + (0<<8) // 15 bpp high alpha | |
871 + (0<<9) // 15 bpp high alpha | |
872 + (0<<10) // 15 bpp high alpha | |
873 + (0<<11) // 15 bpp high alpha | |
874 + (0<<12) // 15 bpp high alpha | |
875 + (0<<13) // 15 bpp high alpha | |
876 + (0<<14) // 15 bpp high alpha | |
877 + (0<<15) // 15 bpp high alpha | |
878 + (0<<16) // 15 bpp low alpha | |
879 + (0<<17) // 15 bpp low alpha | |
880 + (0<<18) // 15 bpp low alpha | |
881 + (0<<19) // 15 bpp low alpha | |
882 + (0<<20) // 15 bpp low alpha | |
883 + (0<<21) // 15 bpp low alpha | |
884 + (0<<22) // 15 bpp low alpha | |
885 + (0<<23) // 15 bpp low alpha | |
886 + (0<<24) // static subpicture key | |
887 + (0<<25) // static subpicture key | |
888 + (0<<26) // static subpicture key | |
889 + (0<<27) // static subpicture key | |
890 + (0<<28) // static subpicture key | |
891 */ ; | |
892 break; | |
893 | |
894 case MGA_VID_FORMAT_UYVY: | |
895 cregs.c2ctl = 1 // CRTC2 enabled | |
896 + (1<<1) // external clock | |
897 + (0<<2) // external clock | |
898 + (1<<3) // pixel clock enable - not needed ??? | |
899 + (0<<4) // high prioryty req | |
900 + (1<<5) // high prioryty req | |
901 + (0<<6) // high prioryty req | |
902 + (1<<8) // high prioryty req max | |
903 + (0<<9) // high prioryty req max | |
904 + (0<<10) // high prioryty req max | |
905 + (0<<20) // CRTC1 to DAC | |
906 + (1<<21) // 422 mode | |
907 + (0<<22) // 422 mode | |
908 + (1<<23) // 422 mode | |
909 + (1<<24) // single chroma line for 420 mode - need to be corrected | |
910 + (1<<25) /*/ interlace mode - need to be corrected*/ | |
911 + (0<<26) // field legth polariry | |
912 + (0<<27) // field identification polariry | |
913 + (1<<28) // VIDRST detection mode | |
914 + (0<<29) // VIDRST detection mode | |
915 + (1<<30) // Horizontal counter preload | |
916 + (1<<31) // Vertical counter preload | |
917 ; | |
918 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode | |
919 + (1<<1) // Y filter enable | |
920 + (1<<2) // CbCr filter enable | |
921 + (0<<3) // subpicture enable (disabled) | |
922 + (0<<4) // NTSC enable (disabled - PAL) | |
923 + (0<<5) // C2 static subpicture enable (disabled) | |
924 + (0<<6) // C2 subpicture offset division (disabled) | |
925 + (1<<7) // 422 subformat selection ! | |
926 /* + (0<<8) // 15 bpp high alpha | |
927 + (0<<9) // 15 bpp high alpha | |
928 + (0<<10) // 15 bpp high alpha | |
929 + (0<<11) // 15 bpp high alpha | |
930 + (0<<12) // 15 bpp high alpha | |
931 + (0<<13) // 15 bpp high alpha | |
932 + (0<<14) // 15 bpp high alpha | |
933 + (0<<15) // 15 bpp high alpha | |
934 + (0<<16) // 15 bpp low alpha | |
935 + (0<<17) // 15 bpp low alpha | |
936 + (0<<18) // 15 bpp low alpha | |
937 + (0<<19) // 15 bpp low alpha | |
938 + (0<<20) // 15 bpp low alpha | |
939 + (0<<21) // 15 bpp low alpha | |
940 + (0<<22) // 15 bpp low alpha | |
941 + (0<<23) // 15 bpp low alpha | |
942 + (0<<24) // static subpicture key | |
943 + (0<<25) // static subpicture key | |
944 + (0<<26) // static subpicture key | |
945 + (0<<27) // static subpicture key | |
946 + (0<<28) // static subpicture key | |
947 */ ; | |
948 break; | |
949 | |
950 default: | |
951 printk(KERN_ERR "mga_vid: Unsupported pixel format: 0x%X\n",config->format); | |
952 return -1; | |
953 } | |
954 | |
955 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); | |
956 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); | |
957 | |
958 cregs.c2misc=0 // CRTCV2 656 togg f0 | |
959 +(0<<1) // CRTCV2 656 togg f0 | |
960 +(0<<2) // CRTCV2 656 togg f0 | |
961 +(0<<4) // CRTCV2 656 togg f1 | |
962 +(0<<5) // CRTCV2 656 togg f1 | |
963 +(0<<6) // CRTCV2 656 togg f1 | |
964 +(0<<8) // Hsync active high | |
965 +(0<<9) // Vsync active high | |
966 // 16-27 c2vlinecomp - nevim co tam dat | |
967 ; | |
968 cregs.c2offset=(regs.bespitch << 1); | |
969 | |
970 cregs.c2pl2startadd0=regs.besa1corg; | |
971 // cregs.c2pl2startadd1=regs.besa2corg; | |
972 cregs.c2pl3startadd0=regs.besa1c3org; | |
973 // cregs.c2pl3startadd1=regs.besa2c3org; | |
974 | |
975 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from | |
976 | |
977 cregs.c2spicstartadd0=0; // not used | |
978 // cregs.c2spicstartadd1=0; // not used | |
979 | |
980 cregs.c2startadd0=regs.besa1org; | |
981 // cregs.c2startadd1=regs.besa2org; | |
982 | |
983 cregs.c2subpiclut=0; //not used | |
984 | |
985 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); | |
986 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); | |
987 | |
988 | |
989 #endif | |
990 | |
2086 | 991 mga_vid_write_regs(0); |
1 | 992 return 0; |
993 } | |
994 | |
68 | 995 #ifdef MGA_ALLOW_IRQ |
996 | |
48 | 997 static void enable_irq(){ |
998 long int cc; | |
999 | |
1000 cc = readl(mga_mmio_base + IEN); | |
63 | 1001 // printk(KERN_ALERT "*** !!! IRQREG = %d\n", (int)(cc&0xff)); |
48 | 1002 |
1003 writeb( 0x11, mga_mmio_base + CRTCX); | |
1004 | |
1005 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
1006 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
1007 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
1008 | |
1009 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
1010 | |
1011 } | |
1012 | |
1013 static void disable_irq(){ | |
1014 | |
1015 writeb( 0x11, mga_mmio_base + CRTCX); | |
1016 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
1017 | |
1018 } | |
1019 | |
1020 void mga_handle_irq(int irq, void *dev_id, struct pt_regs *pregs) { | |
1021 // static int frame=0; | |
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1022 // static int counter=0; |
48 | 1023 long int cc; |
1024 // if ( ! mga_enabled_flag ) return; | |
1025 | |
68 | 1026 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
1027 | |
48 | 1028 //printk("mga_interrupt #%d\n", irq); |
1029 | |
1030 if ( irq != -1 ) { | |
1031 | |
1032 cc = readl(mga_mmio_base + STATUS); | |
1033 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
1034 // debug_irqcnt++; | |
1035 } | |
1036 | |
1037 // if ( debug_irqignore ) { | |
1038 // debug_irqignore = 0; | |
1039 | |
1040 | |
1041 /* | |
1042 if ( mga_conf_deinterlace ) { | |
1043 if ( mga_first_field ) { | |
1044 // printk("mga_interrupt first field\n"); | |
1045 if ( syncfb_interrupt() ) | |
1046 mga_first_field = 0; | |
1047 } else { | |
1048 // printk("mga_interrupt second field\n"); | |
1049 mga_select_buffer( mga_current_field | 2 ); | |
1050 mga_first_field = 1; | |
1051 } | |
1052 } else { | |
1053 syncfb_interrupt(); | |
1054 } | |
1055 */ | |
1056 | |
1057 // frame=(frame+1)&1; | |
1058 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
1059 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
2344 | 1060 |
1061 #ifdef CRTC2 | |
1062 // sem pridat vyber obrazku !!!! | |
1063 crtc2_frame_sel(mga_next_frame); | |
1064 #endif | |
48 | 1065 |
1066 #if 0 | |
1067 ++counter; | |
1068 if(!(counter&63)){ | |
1069 printk("mga irq counter = %d\n",counter); | |
1070 } | |
1071 #endif | |
1072 | |
1073 // } else { | |
1074 // debug_irqignore = 1; | |
1075 // } | |
1076 | |
1077 if ( irq != -1 ) { | |
1078 writeb( 0x11, mga_mmio_base + CRTCX); | |
1079 writeb( 0, mga_mmio_base + CRTCD ); | |
1080 writeb( 0x10, mga_mmio_base + CRTCD ); | |
1081 } | |
1082 | |
1083 // writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); | |
1084 | |
1085 | |
1086 return; | |
1087 | |
1088 } | |
1089 | |
68 | 1090 #endif |
1 | 1091 |
1092 static int mga_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) | |
1093 { | |
1094 int frame; | |
1095 | |
1096 switch(cmd) | |
1097 { | |
1098 case MGA_VID_CONFIG: | |
1099 //FIXME remove | |
68 | 1100 // printk(KERN_DEBUG "vcount = %d\n",readl(mga_mmio_base + VCOUNT)); |
61 | 1101 printk(KERN_DEBUG "mga_mmio_base = %p\n",mga_mmio_base); |
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1102 printk(KERN_DEBUG "mga_mem_base = %08x\n",mga_mem_base); |
1 | 1103 //FIXME remove |
1104 | |
61 | 1105 printk(KERN_DEBUG "mga_vid: Received configuration\n"); |
1 | 1106 |
1107 if(copy_from_user(&mga_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
1108 { | |
61 | 1109 printk(KERN_ERR "mga_vid: failed copy from userspace\n"); |
1 | 1110 return(-EFAULT); |
1111 } | |
57 | 1112 if(mga_config.version != MGA_VID_VERSION){ |
61 | 1113 printk(KERN_ERR "mga_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,mga_config.version); |
57 | 1114 return(-EFAULT); |
1115 } | |
1116 | |
1117 if(mga_config.frame_size==0 || mga_config.frame_size>1024*768*2){ | |
61 | 1118 printk(KERN_ERR "mga_vid: illegal frame_size: %d\n",mga_config.frame_size); |
57 | 1119 return(-EFAULT); |
1120 } | |
1121 | |
1122 if(mga_config.num_frames<1 || mga_config.num_frames>4){ | |
61 | 1123 printk(KERN_ERR "mga_vid: illegal num_frames: %d\n",mga_config.num_frames); |
57 | 1124 return(-EFAULT); |
1125 } | |
1126 | |
1127 mga_src_base = (mga_ram_size*0x100000-mga_config.num_frames*mga_config.frame_size); | |
1128 if(mga_src_base<0){ | |
61 | 1129 printk(KERN_ERR "mga_vid: not enough memory for frames!\n"); |
57 | 1130 return(-EFAULT); |
1131 } | |
1132 mga_src_base &= (~0xFFFF); // 64k boundary | |
61 | 1133 printk(KERN_DEBUG "mga YUV buffer base: 0x%X\n", mga_src_base); |
57 | 1134 |
1 | 1135 if (is_g400) |
1136 mga_config.card_type = MGA_G400; | |
1137 else | |
1138 mga_config.card_type = MGA_G200; | |
1139 | |
1140 mga_config.ram_size = mga_ram_size; | |
1141 | |
1142 if (copy_to_user((mga_vid_config_t *) arg, &mga_config, sizeof(mga_vid_config_t))) | |
1143 { | |
61 | 1144 printk(KERN_ERR "mga_vid: failed copy to userspace\n"); |
1 | 1145 return(-EFAULT); |
1146 } | |
1147 return mga_vid_set_config(&mga_config); | |
1148 break; | |
1149 | |
1150 case MGA_VID_ON: | |
61 | 1151 printk(KERN_DEBUG "mga_vid: Video ON\n"); |
1 | 1152 vid_src_ready = 1; |
1153 if(vid_overlay_on) | |
1154 { | |
1155 regs.besctl |= 1; | |
2086 | 1156 mga_vid_write_regs(0); |
1 | 1157 } |
68 | 1158 #ifdef MGA_ALLOW_IRQ |
48 | 1159 if ( mga_irq != -1 ) enable_irq(); |
68 | 1160 #endif |
48 | 1161 mga_next_frame=0; |
1 | 1162 break; |
1163 | |
1164 case MGA_VID_OFF: | |
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1165 printk(KERN_DEBUG "mga_vid: Video OFF (ioctl)\n"); |
1 | 1166 vid_src_ready = 0; |
68 | 1167 #ifdef MGA_ALLOW_IRQ |
48 | 1168 if ( mga_irq != -1 ) disable_irq(); |
68 | 1169 #endif |
1 | 1170 regs.besctl &= ~1; |
466 | 1171 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 1172 mga_vid_write_regs(0); |
1 | 1173 break; |
1174 | |
1175 case MGA_VID_FSEL: | |
1176 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
1177 { | |
61 | 1178 printk(KERN_ERR "mga_vid: FSEL failed copy from userspace\n"); |
1 | 1179 return(-EFAULT); |
1180 } | |
1181 | |
1182 mga_vid_frame_sel(frame); | |
1183 break; | |
1184 | |
1185 default: | |
61 | 1186 printk(KERN_ERR "mga_vid: Invalid ioctl\n"); |
1 | 1187 return (-EINVAL); |
1188 } | |
1189 | |
1190 return 0; | |
1191 } | |
1192 | |
1193 | |
1194 static int mga_vid_find_card(void) | |
1195 { | |
1196 struct pci_dev *dev = NULL; | |
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1197 unsigned int card_option; |
1 | 1198 |
1989 | 1199 if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G550, NULL))) |
1200 { | |
1201 is_g400 = 1; | |
1202 printk(KERN_INFO "mga_vid: Found MGA G550\n"); | |
1203 } | |
1204 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G400, NULL))) | |
1 | 1205 { |
1206 is_g400 = 1; | |
77 | 1207 printk(KERN_INFO "mga_vid: Found MGA G400/G450\n"); |
1 | 1208 } |
1209 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_AGP, NULL))) | |
1210 { | |
1211 is_g400 = 0; | |
63 | 1212 printk(KERN_INFO "mga_vid: Found MGA G200 AGP\n"); |
1 | 1213 } |
1214 else if((dev = pci_find_device(PCI_VENDOR_ID_MATROX, PCI_DEVICE_ID_MATROX_G200_PCI, NULL))) | |
1215 { | |
1216 is_g400 = 0; | |
63 | 1217 printk(KERN_INFO "mga_vid: Found MGA G200 PCI\n"); |
1 | 1218 } |
1219 else | |
1220 { | |
61 | 1221 printk(KERN_ERR "mga_vid: No supported cards found\n"); |
1 | 1222 return FALSE; |
1223 } | |
1224 | |
1225 pci_dev = dev; | |
48 | 1226 |
1227 mga_irq = pci_dev->irq; | |
1 | 1228 |
1229 #if LINUX_VERSION_CODE >= 0x020300 | |
1230 mga_mmio_base = ioremap_nocache(dev->resource[1].start,0x4000); | |
1231 mga_mem_base = dev->resource[0].start; | |
1232 #else | |
1233 mga_mmio_base = ioremap_nocache(dev->base_address[1] & PCI_BASE_ADDRESS_MEM_MASK,0x4000); | |
1234 mga_mem_base = dev->base_address[0] & PCI_BASE_ADDRESS_MEM_MASK; | |
1235 #endif | |
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1236 printk(KERN_INFO "mga_vid: MMIO at 0x%p IRQ: %d framebuffer: 0x%08X\n", mga_mmio_base, mga_irq, mga_mem_base); |
1 | 1237 |
1238 pci_read_config_dword(dev, 0x40, &card_option); | |
77 | 1239 printk(KERN_INFO "mga_vid: OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, |
1240 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1 | 1241 |
57 | 1242 // temp = (card_option >> 10) & 0x17; |
1243 | |
95 | 1244 if (mga_ram_size) { |
1245 printk(KERN_INFO "mga_vid: RAMSIZE forced to %d MB\n", mga_ram_size); | |
91 | 1246 } else { |
90 | 1247 |
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1248 #ifdef MGA_MEMORY_SIZE |
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1249 mga_ram_size = MGA_MEMORY_SIZE; |
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1250 printk(KERN_INFO "mga_vid: hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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1251 |
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1252 #else |
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1253 |
95 | 1254 if (is_g400){ |
75 | 1255 switch((card_option>>10)&0x17){ |
1256 // SDRAM: | |
1257 case 0x00: | |
1258 case 0x04: mga_ram_size = 16; break; | |
105 | 1259 case 0x03: mga_ram_size = 32; break; |
75 | 1260 // SGRAM: |
1261 case 0x10: | |
1262 case 0x14: mga_ram_size = 32; break; | |
1263 case 0x11: | |
1264 case 0x12: mga_ram_size = 16; break; | |
1265 default: | |
1266 mga_ram_size = 16; | |
1267 printk(KERN_INFO "mga_vid: Couldn't detect RAMSIZE, assuming 16MB!"); | |
1268 } | |
95 | 1269 }else{ |
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1270 switch((card_option>>10)&0x17){ |
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1271 // case 0x10: |
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1272 // case 0x13: mga_ram_size = 8; break; |
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1273 default: mga_ram_size = 8; |
64 | 1274 } |
95 | 1275 } |
64 | 1276 #if 0 |
95 | 1277 // printk("List resources -----------\n"); |
1278 for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ | |
1279 struct resource *res=&pci_dev->resource[temp]; | |
1280 if(res->flags){ | |
1281 int size=(1+res->end-res->start)>>20; | |
1282 printk(KERN_DEBUG "res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); | |
1283 if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ | |
1284 if(size>mga_ram_size && size<=64) mga_ram_size=size; | |
1285 } | |
1286 } | |
57 | 1287 } |
64 | 1288 #endif |
95 | 1289 printk(KERN_INFO "mga_vid: detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); |
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1290 #endif |
95 | 1291 } |
57 | 1292 |
48 | 1293 |
68 | 1294 #ifdef MGA_ALLOW_IRQ |
48 | 1295 if ( mga_irq != -1 ) { |
1296 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
1297 if ( tmp ) { | |
61 | 1298 printk(KERN_INFO "syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); |
48 | 1299 mga_irq=-1; |
1300 } else { | |
61 | 1301 printk(KERN_DEBUG "syncfb (mga): registered irq %d\n", mga_irq); |
48 | 1302 } |
1303 } else { | |
61 | 1304 printk(KERN_INFO "syncfb (mga): No valid irq was found\n"); |
48 | 1305 mga_irq=-1; |
1306 } | |
68 | 1307 #else |
1308 printk(KERN_INFO "syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
1309 mga_irq=-1; | |
1310 #endif | |
48 | 1311 |
1 | 1312 return TRUE; |
1313 } | |
1314 | |
1315 | |
1316 static ssize_t mga_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
1317 { | |
1318 return -EINVAL; | |
1319 } | |
1320 | |
1321 static ssize_t mga_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
1322 { | |
4483
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1323 // WARNING: eyck changes |
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1324 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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1325 { |
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1326 short brightness; |
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1327 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
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1328 if (brightness>127 || brightness<-128) { brightness=0;} |
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1329 // printk(KERN_DEBUG "mga_vid: brightness modified ( %d ) \n",brightness); |
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1330 regs.brightness=brightness; |
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1331 } else |
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1332 if(memcmp(buf,PARAM_BLACKIE,min(count,strlen(PARAM_BLACKIE))) == 0) |
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1333 { |
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1334 short blackie; |
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1335 blackie=simple_strtol(&buf[strlen(PARAM_BLACKIE)],NULL,10); |
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1336 // printk(KERN_DEBUG "mga_vid: shadow mode: ( %d ) \n",blackie); |
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1337 regs.blackie=(blackie>0)?1:0; |
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1338 } else count = -EIO; |
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1339 // TODO: reset settings |
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1340 return count; |
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1341 // return -EINVAL; |
1 | 1342 } |
1343 | |
1344 static int mga_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
1345 { | |
1346 | |
61 | 1347 printk(KERN_DEBUG "mga_vid: mapping video memory into userspace\n"); |
57 | 1348 if(remap_page_range(vma->vm_start, mga_mem_base + mga_src_base, |
1 | 1349 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
1350 { | |
63 | 1351 printk(KERN_ERR "mga_vid: error mapping video memory\n"); |
1 | 1352 return(-EAGAIN); |
1353 } | |
1354 | |
1355 return(0); | |
1356 } | |
1357 | |
1358 static int mga_vid_release(struct inode *inode, struct file *file) | |
1359 { | |
1360 //Close the window just in case | |
94
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1361 printk(KERN_DEBUG "mga_vid: Video OFF (release)\n"); |
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1362 |
1 | 1363 vid_src_ready = 0; |
1364 regs.besctl &= ~1; | |
466 | 1365 regs.besglobctl &= ~(1<<6); // UYVY format selected |
2086 | 1366 // mga_config.colkey_on=0; //!!! |
1367 mga_vid_write_regs(1); | |
1 | 1368 mga_vid_in_use = 0; |
1369 | |
93 | 1370 MOD_DEC_USE_COUNT; |
1 | 1371 return 0; |
1372 } | |
1373 | |
1374 static long long mga_vid_lseek(struct file *file, long long offset, int origin) | |
1375 { | |
1376 return -ESPIPE; | |
1377 } | |
1378 | |
1379 static int mga_vid_open(struct inode *inode, struct file *file) | |
1380 { | |
1381 int minor = MINOR(inode->i_rdev); | |
1382 | |
1383 if(minor != 0) | |
1384 return(-ENXIO); | |
1385 | |
1386 if(mga_vid_in_use == 1) | |
1387 return(-EBUSY); | |
1388 | |
1389 mga_vid_in_use = 1; | |
93 | 1390 MOD_INC_USE_COUNT; |
1 | 1391 return(0); |
1392 } | |
1393 | |
1394 #if LINUX_VERSION_CODE >= 0x020400 | |
1395 static struct file_operations mga_vid_fops = | |
1396 { | |
1397 llseek: mga_vid_lseek, | |
1398 read: mga_vid_read, | |
1399 write: mga_vid_write, | |
1400 ioctl: mga_vid_ioctl, | |
1401 mmap: mga_vid_mmap, | |
1402 open: mga_vid_open, | |
1403 release: mga_vid_release | |
1404 }; | |
1405 #else | |
1406 static struct file_operations mga_vid_fops = | |
1407 { | |
1408 mga_vid_lseek, | |
1409 mga_vid_read, | |
1410 mga_vid_write, | |
1411 NULL, | |
1412 NULL, | |
1413 mga_vid_ioctl, | |
1414 mga_vid_mmap, | |
1415 mga_vid_open, | |
1416 NULL, | |
1417 mga_vid_release | |
1418 }; | |
1419 #endif | |
1420 | |
1421 | |
1422 /* | |
1423 * Main Initialization Function | |
1424 */ | |
1425 | |
1426 static int mga_vid_initialize(void) | |
1427 { | |
1428 mga_vid_in_use = 0; | |
1429 | |
77 | 1430 // printk(KERN_INFO "Matrox MGA G200/G400 YUV Video interface v0.01 (c) Aaron Holtzman \n"); |
1431 printk(KERN_INFO "Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); | |
90 | 1432 |
95 | 1433 if (mga_ram_size) { |
1434 if (mga_ram_size<4 || mga_ram_size>64) { | |
1435 printk(KERN_ERR "mga_vid: invalid RAMSIZE: %d MB\n", mga_ram_size); | |
90 | 1436 return -EINVAL; |
1437 } | |
1438 } | |
1439 | |
1 | 1440 if(register_chrdev(MGA_VID_MAJOR, "mga_vid", &mga_vid_fops)) |
1441 { | |
61 | 1442 printk(KERN_ERR "mga_vid: unable to get major: %d\n", MGA_VID_MAJOR); |
1 | 1443 return -EIO; |
1444 } | |
1445 | |
1446 if (!mga_vid_find_card()) | |
1447 { | |
61 | 1448 printk(KERN_ERR "mga_vid: no supported devices found\n"); |
1 | 1449 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1450 return -EINVAL; | |
1451 } | |
1452 | |
1453 return(0); | |
1454 } | |
1455 | |
1456 int init_module(void) | |
1457 { | |
1458 return mga_vid_initialize(); | |
1459 } | |
1460 | |
1461 void cleanup_module(void) | |
1462 { | |
48 | 1463 |
68 | 1464 #ifdef MGA_ALLOW_IRQ |
48 | 1465 if ( mga_irq != -1) |
1466 free_irq(mga_irq, &mga_irq); | |
68 | 1467 #endif |
48 | 1468 |
1 | 1469 if(mga_mmio_base) |
1470 iounmap(mga_mmio_base); | |
1471 | |
1472 //FIXME turn off BES | |
63 | 1473 printk(KERN_INFO "mga_vid: Cleaning up module\n"); |
1 | 1474 unregister_chrdev(MGA_VID_MAJOR, "mga_vid"); |
1475 } | |
1476 |