Mercurial > mplayer.hg
annotate vidix/drivers/nvidia_vid.c @ 10970:de7036f31e5a
Sometimes (especially with big images) reading pitch 0 from card's register
returns 0 (probably due to full card's FIFO), which leads to SIGFPE later.
Fixed (or workarounded) by rereading pitch0, until it's not zero.
author | lumag |
---|---|
date | Wed, 01 Oct 2003 21:03:00 +0000 |
parents | 4d4d0c1c7142 |
children | 3da6b1de1c33 |
rev | line source |
---|---|
10954 | 1 /* |
2 nvidia_vid - VIDIX based video driver for NVIDIA chips | |
3 Copyrights 2003 Sascha Sommer. This file is based on sources from | |
4 RIVATV (rivatv.sf.net) | |
5 Licence: GPL | |
6 WARNING: THIS DRIVER IS IN BETTA STAGE | |
7 | |
8 multi buffer support, TNT2 fixes and experimental yv12 support by Dmitry Baryshkov | |
9 */ | |
10 | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <inttypes.h> | |
17 #include <unistd.h> | |
18 | |
19 | |
20 #include "../vidix.h" | |
21 #include "../fourcc.h" | |
22 #include "../../libdha/libdha.h" | |
23 #include "../../libdha/pci_ids.h" | |
24 #include "../../libdha/pci_names.h" | |
25 #include "../../config.h" | |
26 #include "../../bswap.h" | |
27 | |
28 | |
29 pciinfo_t pci_info; | |
30 | |
31 | |
32 #define MAX_FRAMES 3 | |
33 #define NV04_BES_SIZE 1024*2000*4 | |
34 | |
35 | |
36 static vidix_capability_t nvidia_cap = { | |
37 "NVIDIA RIVA OVERLAY DRIVER", | |
38 "Sascha Sommer <saschasommer@freenet.de>", | |
39 TYPE_OUTPUT, | |
40 { 0, 0, 0, 0 }, | |
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according to xfree cvs maximum overlay size is only 2046x2046
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41 2046, |
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according to xfree cvs maximum overlay size is only 2046x2046
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42 2046, |
10954 | 43 4, |
44 4, | |
45 -1, | |
46 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
47 VENDOR_NVIDIA2, | |
48 -1, | |
49 { 0, 0, 0, 0 } | |
50 }; | |
51 | |
52 | |
53 unsigned int vixGetVersion(void){ | |
54 return(VIDIX_VERSION); | |
55 } | |
56 | |
57 | |
58 #define NV_ARCH_03 0x03 | |
59 #define NV_ARCH_04 0x04 | |
60 #define NV_ARCH_10 0x10 | |
61 #define NV_ARCH_20 0x20 | |
62 #define NV_ARCH_30 0x30 | |
63 | |
64 struct nvidia_cards { | |
65 unsigned short chip_id; | |
66 unsigned short arch; | |
67 }; | |
68 | |
69 | |
70 static struct nvidia_cards nvidia_card_ids[] = { | |
71 /*tested && working*/ | |
72 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, | |
73 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, | |
74 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
75 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, | |
76 /*untested*/ | |
77 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, | |
78 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, | |
79 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, | |
80 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, | |
81 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
82 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, | |
83 }; | |
84 | |
85 | |
86 static int find_chip(unsigned chip_id){ | |
87 unsigned i; | |
88 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
89 { | |
90 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
91 } | |
92 return -1; | |
93 } | |
94 | |
95 int vixProbe(int verbose, int force){ | |
96 pciinfo_t lst[MAX_PCI_DEVICES]; | |
97 unsigned i,num_pci; | |
98 int err; | |
99 | |
100 if (force) | |
101 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
102 err = pci_scan(lst,&num_pci); | |
103 if(err){ | |
104 printf("[nvidia_vid] Error occured during pci scan: %s\n",strerror(err)); | |
105 return err; | |
106 } | |
107 else { | |
108 err = ENXIO; | |
109 for(i=0; i < num_pci; i++){ | |
110 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
111 int idx; | |
112 const char *dname; | |
113 idx = find_chip(lst[i].device); | |
114 if(idx == -1) | |
115 continue; | |
116 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
117 dname = dname ? dname : "Unknown chip"; | |
118 printf("[nvidia_vid] Found chip: %s\n", dname); | |
119 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
120 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
121 continue; | |
122 } | |
123 nvidia_cap.device_id = lst[i].device; | |
124 err = 0; | |
125 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
126 break; | |
127 } | |
128 } | |
129 } | |
130 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
131 return err; | |
132 } | |
133 | |
134 | |
135 | |
136 | |
137 /* | |
138 * PCI-Memory IO access macros. | |
139 */ | |
140 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
141 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
142 | |
143 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
144 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
145 | |
146 #ifndef USE_RMW_CYCLES | |
147 /* | |
148 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
149 */ | |
150 | |
151 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
152 | |
153 #undef VID_WR08 | |
154 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
155 #undef VID_RD08 | |
156 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
157 | |
158 #undef VID_WR32 | |
159 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
160 #undef VID_RD32 | |
161 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
162 #endif /* USE_RMW_CYCLES */ | |
163 | |
164 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
165 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
166 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
167 | |
168 | |
169 | |
170 | |
171 | |
172 | |
173 struct rivatv_chip { | |
174 volatile uint32_t *PMC; /* general control */ | |
175 volatile uint32_t *PME; /* multimedia port */ | |
176 volatile uint32_t *PFB; /* framebuffer control */ | |
177 volatile uint32_t *PVIDEO; /* overlay control */ | |
178 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
179 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
180 volatile uint32_t *PRAMIN; /* instance memory */ | |
181 volatile uint32_t *PRAMHT; /* hash table */ | |
182 volatile uint32_t *PRAMFC; /* fifo context table */ | |
183 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
184 volatile uint32_t *PFIFO; /* fifo control region */ | |
185 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
186 volatile uint32_t *PGRAPH; /* graphics engine */ | |
187 | |
188 unsigned long fbsize; /* framebuffer size */ | |
189 int arch; /* compatible NV_ARCH_XX define */ | |
190 int realarch; /* real architecture */ | |
191 void (* lock) (struct rivatv_chip *, int); | |
192 }; | |
193 typedef struct rivatv_chip rivatv_chip; | |
194 | |
195 | |
196 struct rivatv_info { | |
197 unsigned int colorkey; /* saved xv colorkey*/ | |
198 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
199 unsigned int depth; | |
200 unsigned int format; | |
201 unsigned int pitch; | |
202 unsigned int width,height; | |
203 unsigned int d_width,d_height; /*scaled width && height*/ | |
204 unsigned int wx,wy; /*window x && y*/ | |
205 unsigned int screen_x; /*screen width*/ | |
206 unsigned long buffer_size; /* size of the image buffer */ | |
207 struct rivatv_chip chip; /* NV architecture structure */ | |
208 void* video_base; /* virtual address of control region */ | |
209 void* control_base; /* virtual address of fb region */ | |
210 unsigned long picture_base; /* direct pointer to video picture */ | |
211 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
212 // struct rivatv_dma dma; /* DMA structure */ | |
213 unsigned int next_frame; | |
214 unsigned int num_frames; /* number of buffers */ | |
215 }; | |
216 typedef struct rivatv_info rivatv_info; | |
217 | |
218 //framebuffer size funcs | |
219 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
220 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
221 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
222 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
223 /* SDRAM 128 ZX. */ | |
224 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
225 } | |
226 else { | |
227 return 1024 * 1024 * 8; | |
228 } | |
229 } | |
230 else { | |
231 /* SGRAM 128. */ | |
232 switch (chip->PFB[0x00000000] & 0x00000003) { | |
233 case 0: | |
234 return 1024 * 1024 * 8; | |
235 break; | |
236 case 2: | |
237 return 1024 * 1024 * 4; | |
238 break; | |
239 default: | |
240 return 1024 * 1024 * 2; | |
241 break; | |
242 } | |
243 } | |
244 } | |
245 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
246 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
247 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
248 + 1024 * 1024 * 2; | |
249 } else { | |
250 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
251 case 0: | |
252 return 1024 * 1024 * 32; | |
253 break; | |
254 case 1: | |
255 return 1024 * 1024 * 4; | |
256 break; | |
257 case 2: | |
258 return 1024 * 1024 * 8; | |
259 break; | |
260 case 3: | |
261 default: | |
262 return 1024 * 1024 * 16; | |
263 break; | |
264 } | |
265 } | |
266 } | |
267 | |
268 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
269 return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 1024; | |
270 } | |
271 | |
272 //lock funcs | |
273 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
274 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
275 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
276 } | |
277 | |
278 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
279 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
280 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
281 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
282 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
283 } | |
284 | |
285 | |
286 | |
287 | |
288 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
289 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
290 uint32_t reg; | |
291 | |
292 /* switch off interrupts once for a while */ | |
293 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
294 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
295 | |
296 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
297 | |
298 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
299 | |
300 if ((reg & 0x10100010) != 0x10100010) { | |
301 printf("PVIDEO and PFB disabled, enabling...\n"); | |
302 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
303 } | |
304 | |
305 /* save the current colorkey */ | |
306 switch (info->chip.arch ) { | |
307 case NV_ARCH_10: | |
308 case NV_ARCH_20: | |
309 case NV_ARCH_30: | |
310 /* NV_PVIDEO_COLOR_KEY */ | |
311 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
312 break; | |
313 case NV_ARCH_03: | |
314 case NV_ARCH_04: | |
315 /* NV_PVIDEO_KEY */ | |
316 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
317 break; | |
318 } | |
319 | |
320 | |
321 /* re-enable interrupts again */ | |
322 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
323 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
324 } | |
325 | |
326 /* Stop overlay video. */ | |
327 void rivatv_overlay_stop (struct rivatv_info *info) { | |
328 switch (info->chip.arch ) { | |
329 case NV_ARCH_10: | |
330 case NV_ARCH_20: | |
331 case NV_ARCH_30: | |
332 /* NV_PVIDEO_COLOR_KEY */ | |
333 /* Xv-Extension-Hack: Restore previously saved value. */ | |
334 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
335 /* NV_PVIDEO_STOP */ | |
336 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
337 /* NV_PVIDEO_BUFFER */ | |
338 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
339 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
340 VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); | |
341 break; | |
342 case NV_ARCH_03: | |
343 case NV_ARCH_04: | |
344 /* NV_PVIDEO_KEY */ | |
345 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
346 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
347 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
348 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
349 VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); | |
350 /* NV_PVIDEO_OE_STATE */ | |
351 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
352 /* NV_PVIDEO_SU_STATE */ | |
353 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
354 /* NV_PVIDEO_RM_STATE */ | |
355 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
356 break; | |
357 } | |
358 } | |
359 | |
360 /* Get pan offset of the physical screen. */ | |
361 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
362 uint32_t pan; | |
363 info->chip.lock (&info->chip, 0); | |
364 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
365 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
366 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
367 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
368 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
369 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
370 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
371 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
372 return pan << 2; | |
373 } | |
374 | |
375 /* Compute and set colorkey depending on the colour depth. */ | |
376 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
377 uint32_t r, g, b, key = 0; | |
378 r = (chromakey & 0x00FF0000) >> 16; | |
379 g = (chromakey & 0x0000FF00) >> 8; | |
380 b = chromakey & 0x000000FF; | |
381 switch (info->depth) { | |
382 case 15: | |
383 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); | |
384 break; | |
385 case 16: | |
386 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); | |
387 break; | |
388 case 24: | |
389 key = chromakey & 0x00FFFFFF; | |
390 break; | |
391 case 32: | |
392 key = chromakey; | |
393 break; | |
394 default: | |
395 /* THINKME: Possible to pass a colour index for 8 bpp ? */ | |
396 printf ("invalid color depth: %d bpp\n", info->depth); | |
397 break; | |
398 } | |
399 switch (info->chip.arch) { | |
400 case NV_ARCH_10: | |
401 case NV_ARCH_20: | |
402 case NV_ARCH_30: | |
403 VID_WR32 (info->chip.PVIDEO, 0xB00, key); | |
404 break; | |
405 case NV_ARCH_03: | |
406 case NV_ARCH_04: | |
407 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
408 break; | |
409 } | |
410 } | |
411 | |
412 | |
413 /* Start overlay video. */ | |
414 void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
415 uint32_t base, size, offset, xscale, yscale, pan,bpp, pitch0=0; | |
416 int x, y; | |
417 int lwidth=info->d_width, lheight=info->d_height; | |
418 int bps; | |
419 | |
420 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ | |
421 info->chip.lock (&info->chip, 0); | |
10970
de7036f31e5a
Sometimes (especially with big images) reading pitch 0 from card's register
lumag
parents:
10957
diff
changeset
|
422 do { |
10954 | 423 switch (info->chip.arch) { |
424 case NV_ARCH_03: | |
425 pitch0 = info->chip.PGRAPH[0x00000650/4]; | |
426 break; | |
427 case NV_ARCH_04: | |
428 case NV_ARCH_10: | |
429 case NV_ARCH_20: | |
430 case NV_ARCH_30: | |
431 pitch0 = info->chip.PGRAPH[0x00000670/4]; | |
432 break; | |
433 } | |
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Sometimes (especially with big images) reading pitch 0 from card's register
lumag
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434 if (pitch0 == 0) |
de7036f31e5a
Sometimes (especially with big images) reading pitch 0 from card's register
lumag
parents:
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diff
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435 printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n"); |
de7036f31e5a
Sometimes (especially with big images) reading pitch 0 from card's register
lumag
parents:
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436 } while (pitch0 == 0); |
10954 | 437 VID_WR08(info->chip.PCIO, 0x03D4, 0x28); |
438 bpp = VID_RD08(info->chip.PCIO,0x03D5); | |
439 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? | |
440 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16 | |
441 else info->depth = bpp*8; | |
442 if(!bpp)printf("[nvidia_vid] error invalid bpp\n"); | |
443 else | |
444 { | |
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Sometimes (especially with big images) reading pitch 0 from card's register
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445 // printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); |
10954 | 446 info->screen_x = pitch0/bpp; |
447 } | |
448 | |
449 bps = info->screen_x * ((info->depth+1)/8); | |
450 /* get pan offset of the physical screen */ | |
451 pan = rivatv_overlay_pan (info); | |
452 size = info->buffer_size; | |
453 /* adjust window position depending on the pan offset */ | |
454 x = info->wx - (pan % bps) * 8 / info->depth; | |
455 y = info->wy - (pan / bps); | |
456 | |
457 base = info->picture_offset; | |
458 offset = bufno*size; | |
459 | |
460 /* adjust negative output window variables */ | |
461 if (x < 0) { | |
462 lwidth = info->d_width + x; | |
463 offset += (-x * info->width / info->d_width) << 1; | |
464 // offset += (-window->x * port->vld_width / window->width) << 1; | |
465 x = 0; | |
466 } | |
467 if (y < 0) { | |
468 lheight = info->d_height + y; | |
469 offset += (-y * info->height / info->d_height * info->width) << 1; | |
470 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; | |
471 y = 0; | |
472 } | |
473 | |
474 switch (info->chip.arch) { | |
475 case NV_ARCH_10: | |
476 case NV_ARCH_20: | |
477 case NV_ARCH_30: | |
478 | |
479 /* NV_PVIDEO_BASE */ | |
480 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base); | |
481 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); | |
482 /* NV_PVIDEO_LIMIT */ | |
483 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + size - 1); | |
484 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); | |
485 | |
486 /* extra code for NV20 && NV30 architectures */ | |
487 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { | |
488 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base); | |
489 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); | |
490 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + size - 1); | |
491 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); | |
492 } | |
493 | |
494 /* NV_PVIDEO_LUMINANCE */ | |
495 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000); | |
496 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
497 /* NV_PVIDEO_CHROMINANCE */ | |
498 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000); | |
499 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
500 | |
501 /* NV_PVIDEO_OFFSET */ | |
502 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, offset + 0); | |
503 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); | |
504 /* NV_PVIDEO_SIZE_IN */ | |
505 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
506 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
507 /* NV_PVIDEO_POINT_IN */ | |
508 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
509 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
510 /* NV_PVIDEO_DS_DX_RATIO */ | |
511 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
512 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
513 /* NV_PVIDEO_DT_DY_RATIO */ | |
514 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
515 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
516 | |
517 /* NV_PVIDEO_POINT_OUT */ | |
518 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
519 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
520 /* NV_PVIDEO_SIZE_OUT */ | |
521 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
522 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
523 | |
524 /* NV_PVIDEO_FORMAT */ | |
525 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, (info->pitch << 0) | 0x00100000|(((info->format==IMGFMT_YV12)?1:0))<<16); | |
526 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
527 | |
528 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
529 VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); | |
530 /* NV_PVIDEO_STOP */ | |
531 VID_AND32 (info->chip.PVIDEO, 0x704, 0xFFFFFFEE); | |
532 /* NV_PVIDEO_BUFFER */ | |
533 VID_OR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); | |
534 break; | |
535 | |
536 case NV_ARCH_03: | |
537 case NV_ARCH_04: | |
538 | |
539 | |
540 /* NV_PVIDEO_OE_STATE */ | |
541 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
542 /* NV_PVIDEO_SU_STATE */ | |
543 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
544 /* NV_PVIDEO_RM_STATE */ | |
545 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
546 | |
547 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
548 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
549 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
550 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
551 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
552 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
553 | |
554 /* NV_PVIDEO_WINDOW_START */ | |
555 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
556 /* NV_PVIDEO_WINDOW_SIZE */ | |
557 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
558 /* NV_PVIDEO_STEP_SIZE */ | |
559 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
560 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
561 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
562 | |
563 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
564 VID_WR32 (info->chip.PVIDEO, 0x280, 0x69); | |
565 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
566 VID_WR32 (info->chip.PVIDEO, 0x284, 0x3e); | |
567 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
568 VID_WR32 (info->chip.PVIDEO, 0x288, 0x89); | |
569 /* NV_PVIDEO_CSC_ADJUST */ | |
570 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
571 | |
572 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
573 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
574 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
575 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*rivatv 0x110 */ | |
576 | |
577 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
578 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
579 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
580 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
581 | |
582 /* NV_PVIDEO_BUFF0_OFFSET */ | |
583 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
584 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
585 | |
586 | |
587 | |
588 | |
589 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
590 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
591 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ | |
592 | |
593 VID_WR32 (info->chip.PVIDEO, 0x244, (info->format==IMGFMT_YUY2)?0x111:0x011); | |
594 /* NV_PVIDEO_SU_STATE */ | |
595 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
596 break; | |
597 } | |
598 /*set colorkey*/ | |
599 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
600 | |
601 } | |
602 | |
603 | |
604 static rivatv_info* info; | |
605 | |
606 | |
607 | |
608 | |
609 int vixInit(void){ | |
610 int mtrr; | |
611 info = (rivatv_info*)calloc(1,sizeof(rivatv_info)); | |
612 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
613 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
614 printf("[nvidia_vid] arch %x register base %x\n",info->chip.arch,(unsigned int)info->control_base); | |
615 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
616 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
617 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
618 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
619 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
620 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
621 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
622 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
623 /* setup chip specific functions */ | |
624 switch (info->chip.arch) { | |
625 case NV_ARCH_03: | |
626 info->chip.lock = rivatv_lock_nv03; | |
627 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
628 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
629 break; | |
630 case NV_ARCH_04: | |
631 info->chip.lock = rivatv_lock_nv04; | |
632 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
633 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
634 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
635 break; | |
636 case NV_ARCH_10: | |
637 case NV_ARCH_20: | |
638 case NV_ARCH_30: | |
639 info->chip.lock = rivatv_lock_nv04; | |
640 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
641 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
642 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
643 break; | |
644 } | |
645 switch (info->chip.arch) { | |
646 case NV_ARCH_03: | |
647 { | |
648 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
649 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
650 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
651 info->picture_offset = 2*1024*768*4 ; | |
652 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
653 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
654 break; | |
655 } | |
656 case NV_ARCH_04: | |
657 case NV_ARCH_10: | |
658 case NV_ARCH_20: | |
659 case NV_ARCH_30: | |
660 { | |
661 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
662 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
663 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
664 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
665 break; | |
666 } | |
667 } | |
668 | |
669 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
670 | |
671 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
672 printf("[nvidia_vid]: unable to setup MTRR: %s\n", strerror(mtrr)); | |
673 else | |
674 printf("[nvidia_vid]: MTRR set up\n"); | |
675 | |
676 /*get some info about the screen dimension and depth*/ | |
677 { | |
678 uint32_t bpp=0,pitch0=0; | |
679 info->chip.lock (&info->chip, 0); | |
10970
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680 do { |
10954 | 681 switch (info->chip.arch) { |
682 case NV_ARCH_03: | |
683 pitch0 = info->chip.PGRAPH[0x00000650/4]; | |
684 break; | |
685 case NV_ARCH_04: | |
686 case NV_ARCH_10: | |
687 case NV_ARCH_20: | |
688 case NV_ARCH_30: | |
689 pitch0 = info->chip.PGRAPH[0x00000670/4]; | |
690 break; | |
691 } | |
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692 if (pitch0 == 0) |
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693 printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n"); |
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694 } while (pitch0 == 0); |
10954 | 695 VID_WR08(info->chip.PCIO, 0x03D4, 0x28); |
696 bpp = VID_RD08(info->chip.PCIO,0x03D5); | |
697 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? | |
698 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16 | |
699 else info->depth = bpp*8; | |
700 if(!bpp)printf("[nvidia_vid] error invalid bpp\n"); | |
701 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); | |
702 } | |
703 | |
704 rivatv_enable_PMEDIA(info); | |
705 info->next_frame = 0; | |
706 return 0; | |
707 } | |
708 | |
709 void vixDestroy(void){ | |
710 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); | |
711 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
712 free(info); | |
713 } | |
714 | |
715 int vixGetCapability(vidix_capability_t *to){ | |
716 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); | |
717 return 0; | |
718 } | |
719 | |
720 inline static int is_supported_fourcc(uint32_t fourcc) | |
721 { | |
722 if (fourcc == IMGFMT_UYVY || | |
723 (fourcc == IMGFMT_YUY2 && info->chip.arch <= NV_ARCH_04) || | |
724 (fourcc == IMGFMT_YV12 && info->chip.arch >= NV_ARCH_10)) | |
725 return 1; | |
726 else | |
727 return 0; | |
728 } | |
729 | |
730 int vixQueryFourcc(vidix_fourcc_t *to){ | |
731 if(is_supported_fourcc(to->fourcc)){ | |
732 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
733 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
734 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
735 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
736 VID_DEPTH_32BPP; | |
737 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
738 return 0; | |
739 } | |
740 else to->depth = to->flags = 0; | |
741 return ENOSYS; | |
742 } | |
743 | |
744 int vixConfigPlayback(vidix_playback_t *vinfo){ | |
745 uint32_t i; | |
746 printf("called %s\n", __FUNCTION__); | |
747 if (! is_supported_fourcc(vinfo->fourcc)) | |
748 return ENOSYS; | |
749 | |
750 info->width = vinfo->src.w; | |
751 info->height = vinfo->src.h; | |
752 | |
753 info->d_width = vinfo->dest.w; | |
754 info->d_height = vinfo->dest.h; | |
755 info->wx = vinfo->dest.x; | |
756 info->wy = vinfo->dest.y; | |
757 info->format = vinfo->fourcc; | |
758 | |
759 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
760 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
761 | |
762 | |
763 vinfo->dga_addr=(void*)(info->picture_base); | |
764 | |
765 switch (vinfo->fourcc) | |
766 { | |
767 case IMGFMT_YUY2: | |
768 case IMGFMT_UYVY: | |
769 | |
770 vinfo->dest.pitch.y = 2; | |
771 vinfo->dest.pitch.u = 0; | |
772 vinfo->dest.pitch.v = 0; | |
773 | |
774 vinfo->offset.y = 0; | |
775 vinfo->offset.v = 0; | |
776 vinfo->offset.u = 0; | |
777 | |
778 info->pitch = info->width << 1; | |
779 vinfo->frame_size = info->pitch * info->height; | |
780 break; | |
781 case IMGFMT_YV12: | |
782 vinfo->dest.pitch.y = 1; | |
783 vinfo->dest.pitch.u = 1; | |
784 vinfo->dest.pitch.v = 1; | |
785 | |
786 vinfo->offset.y = 0; | |
787 vinfo->offset.v = (info->width) * info->height; | |
788 vinfo->offset.u = vinfo->offset.v * 5 / 4; | |
789 | |
790 info->pitch = info->width + (info->width >> 1); | |
791 vinfo->frame_size = info->pitch * info->height; | |
792 break; | |
793 } | |
794 info->buffer_size = vinfo->frame_size; | |
795 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
796 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
797 // vinfo->num_frames = 1; | |
798 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
799 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
800 return 0; | |
801 } | |
802 | |
803 int vixPlaybackOn(void){ | |
804 rivatv_overlay_start(info,info->next_frame); | |
805 return 0; | |
806 } | |
807 | |
808 int vixPlaybackOff(void){ | |
809 rivatv_overlay_stop(info); | |
810 return 0; | |
811 } | |
812 | |
813 int vixSetGrKeys( const vidix_grkey_t * grkey){ | |
814 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
815 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
816 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
817 return 0; | |
818 } | |
819 | |
820 int vixPlaybackFrameSelect(unsigned int frame){ | |
821 // printf("selecting buffer %d\n", frame); | |
822 rivatv_overlay_start(info, frame); | |
823 if (info->num_frames >= 1) | |
824 info->next_frame = (frame+1)%info->num_frames; | |
825 return 0; | |
826 } |