Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 12512:58bd8cb86f5d libavcodec
Remove unused variable.
author | rbultje |
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date | Fri, 24 Sep 2010 15:31:46 +0000 |
parents | 9fef0a8ddd63 |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org> |
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5 * |
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6 * This file is part of FFmpeg. |
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7 * |
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8 * FFmpeg is free software; you can redistribute it and/or |
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9 * modify it under the terms of the GNU Lesser General Public |
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10 * License as published by the Free Software Foundation; either |
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11 * version 2.1 of the License, or (at your option) any later version. |
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12 * |
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13 * FFmpeg is distributed in the hope that it will be useful, |
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 * Lesser General Public License for more details. |
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17 * |
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18 * You should have received a copy of the GNU Lesser General Public |
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19 * License along with FFmpeg; if not, write to the Free Software |
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20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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21 */ |
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22 |
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23 #include "libavutil/cpu.h" |
6763 | 24 #include "libavcodec/dsputil.h" |
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25 #include "dsputil_altivec.h" |
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26 |
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27 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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28 /* |
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29 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a |
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30 cache line size not equal to 32 bytes. |
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31 Fortunately all processor used by Apple up to at least the 7450 (aka second |
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32 generation G4) use 32 bytes cache line. |
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33 This is due to the use of the 'dcbz' instruction. It simply clear to zero a |
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34 single cache line, so you need to know the cache line size to use it ! |
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35 It's absurd, but it's fast... |
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36 |
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37 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line |
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38 size: 128 bytes. Oups. |
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39 The semantic of dcbz was changed, it always clear 32 bytes. so the function |
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40 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl, |
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41 which is defined to clear a cache line (as dcbz before). So we still can |
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42 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required. |
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43 |
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44 see <http://developer.apple.com/technotes/tn/tn2087.html> |
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45 and <http://developer.apple.com/technotes/tn/tn2086.html> |
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46 */ |
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47 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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48 { |
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49 register int misal = ((unsigned long)blocks & 0x00000010); |
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50 register int i = 0; |
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51 #if 1 |
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52 if (misal) { |
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53 ((unsigned long*)blocks)[0] = 0L; |
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54 ((unsigned long*)blocks)[1] = 0L; |
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55 ((unsigned long*)blocks)[2] = 0L; |
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56 ((unsigned long*)blocks)[3] = 0L; |
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57 i += 16; |
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58 } |
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59 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) { |
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61 } |
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62 if (misal) { |
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63 ((unsigned long*)blocks)[188] = 0L; |
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64 ((unsigned long*)blocks)[189] = 0L; |
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65 ((unsigned long*)blocks)[190] = 0L; |
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66 ((unsigned long*)blocks)[191] = 0L; |
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67 i += 16; |
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68 } |
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69 #else |
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70 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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71 #endif |
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72 } |
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73 |
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74 /* same as above, when dcbzl clear a whole 128B cache line |
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75 i.e. the PPC970 aka G5 */ |
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77 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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78 { |
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79 register int misal = ((unsigned long)blocks & 0x0000007f); |
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80 register int i = 0; |
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81 #if 1 |
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82 if (misal) { |
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83 // we could probably also optimize this case, |
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84 // but there's not much point as the machines |
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85 // aren't available yet (2003-06-26) |
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86 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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87 } |
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88 else |
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89 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
8031 | 90 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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91 } |
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92 #else |
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93 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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94 #endif |
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95 } |
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96 #else |
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97 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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98 { |
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99 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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100 } |
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101 #endif |
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102 |
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104 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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105 /* update 24/06/2003 : replace dcbz by dcbzl to get |
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106 the intended effect (Apple "fixed" dcbz) |
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107 unfortunately this cannot be used unless the assembler |
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108 knows about dcbzl ... */ |
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109 static long check_dcbzl_effect(void) |
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110 { |
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111 register char *fakedata = av_malloc(1024); |
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112 register char *fakedata_middle; |
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113 register long zero = 0; |
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114 register long i = 0; |
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115 long count = 0; |
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116 |
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117 if (!fakedata) { |
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118 return 0L; |
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119 } |
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120 |
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121 fakedata_middle = (fakedata + 512); |
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122 |
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123 memset(fakedata, 0xFF, 1024); |
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124 |
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125 /* below the constraint "b" seems to mean "Address base register" |
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126 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */ |
8031 | 127 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero)); |
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128 |
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129 for (i = 0; i < 1024 ; i ++) { |
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130 if (fakedata[i] == (char)0) |
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131 count++; |
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132 } |
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133 |
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134 av_free(fakedata); |
2967 | 135 |
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136 return count; |
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137 } |
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138 #else |
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139 static long check_dcbzl_effect(void) |
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140 { |
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141 return 0; |
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142 } |
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143 #endif |
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144 |
4003 | 145 static void prefetch_ppc(void *mem, int stride, int h) |
146 { | |
147 register const uint8_t *p = mem; | |
148 do { | |
8031 | 149 __asm__ volatile ("dcbt 0,%0" : : "r" (p)); |
4003 | 150 p+= stride; |
151 } while(--h); | |
152 } | |
153 | |
1092 | 154 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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155 { |
5749 | 156 // Common optimizations whether AltiVec is available or not |
4003 | 157 c->prefetch = prefetch_ppc; |
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158 switch (check_dcbzl_effect()) { |
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159 case 32: |
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160 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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161 break; |
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162 case 128: |
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163 c->clear_blocks = clear_blocks_dcbz128_ppc; |
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164 break; |
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165 default: |
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166 break; |
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167 } |
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168 |
8590 | 169 #if HAVE_ALTIVEC |
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170 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx); |
2967 | 171 |
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172 if (av_get_cpu_flags() & AV_CPU_FLAG_ALTIVEC) { |
3547 | 173 dsputil_init_altivec(c, avctx); |
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174 if(CONFIG_VC1_DECODER) |
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175 vc1dsp_init_altivec(c, avctx); |
3581 | 176 float_init_altivec(c, avctx); |
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177 int_init_altivec(c, avctx); |
2979 | 178 c->gmc1 = gmc1_altivec; |
1092 | 179 |
8590 | 180 #if CONFIG_ENCODERS |
2979 | 181 if (avctx->dct_algo == FF_DCT_AUTO || |
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182 avctx->dct_algo == FF_DCT_ALTIVEC) { |
2979 | 183 c->fdct = fdct_altivec; |
184 } | |
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185 #endif //CONFIG_ENCODERS |
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186 |
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187 if (avctx->lowres==0) { |
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188 if ((avctx->idct_algo == FF_IDCT_AUTO) || |
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189 (avctx->idct_algo == FF_IDCT_ALTIVEC)) { |
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190 c->idct_put = idct_put_altivec; |
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191 c->idct_add = idct_add_altivec; |
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192 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; |
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193 }else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) && |
9711 | 194 avctx->idct_algo==FF_IDCT_VP3){ |
195 c->idct_put = ff_vp3_idct_put_altivec; | |
196 c->idct_add = ff_vp3_idct_add_altivec; | |
197 c->idct = ff_vp3_idct_altivec; | |
198 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; | |
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199 } |
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200 } |
2967 | 201 |
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202 } |
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203 #endif /* HAVE_ALTIVEC */ |
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204 } |