Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 3702:7e7d8a3fe080 libavcodec
make AVOptions default value field work.
Patch by Panagiotis Issaris % takis P issaris A uhasselt P be %
Original thread:
Date: Sep 8, 2006 3:22 PM
Subject: [Ffmpeg-devel] [PATCH 1/2] Enable usage of AVOption default value
author | gpoirier |
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date | Sun, 10 Sep 2006 20:21:40 +0000 |
parents | 49082584828a |
children | c8c591fe26f8 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org> |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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19 */ |
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20 |
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21 #include "../dsputil.h" |
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22 |
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23 #include "dsputil_ppc.h" |
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24 |
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25 #ifdef HAVE_ALTIVEC |
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26 #include "dsputil_altivec.h" |
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27 |
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28 extern void fdct_altivec(int16_t *block); |
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29 extern void gmc1_altivec(uint8_t *dst, uint8_t *src, int stride, int h, |
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30 int x16, int y16, int rounder); |
1092 | 31 extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block); |
32 extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block); | |
3547 | 33 |
34 void dsputil_h264_init_ppc(DSPContext* c, AVCodecContext *avctx); | |
3532 | 35 |
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36 void dsputil_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3542 | 37 void vc1dsp_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3547 | 38 void snow_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3581 | 39 void float_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3532 | 40 |
41 #endif | |
3223 | 42 |
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43 int mm_flags = 0; |
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44 |
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45 int mm_support(void) |
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46 { |
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47 int result = 0; |
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48 #ifdef HAVE_ALTIVEC |
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49 if (has_altivec()) { |
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50 result |= MM_ALTIVEC; |
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51 } |
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52 #endif /* result */ |
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53 return result; |
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54 } |
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55 |
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56 #ifdef POWERPC_PERFORMANCE_REPORT |
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57 unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total]; |
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58 /* list below must match enum in dsputil_ppc.h */ |
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59 static unsigned char* perfname[] = { |
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60 "ff_fft_calc_altivec", |
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61 "gmc1_altivec", |
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62 "dct_unquantize_h263_altivec", |
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63 "fdct_altivec", |
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64 "idct_add_altivec", |
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65 "idct_put_altivec", |
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66 "put_pixels16_altivec", |
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67 "avg_pixels16_altivec", |
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68 "avg_pixels8_altivec", |
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69 "put_pixels8_xy2_altivec", |
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70 "put_no_rnd_pixels8_xy2_altivec", |
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71 "put_pixels16_xy2_altivec", |
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72 "put_no_rnd_pixels16_xy2_altivec", |
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73 "hadamard8_diff8x8_altivec", |
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74 "hadamard8_diff16_altivec", |
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75 "avg_pixels8_xy2_altivec", |
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76 "clear_blocks_dcbz32_ppc", |
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77 "clear_blocks_dcbz128_ppc", |
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78 "put_h264_chroma_mc8_altivec", |
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79 "avg_h264_chroma_mc8_altivec", |
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80 "put_h264_qpel16_h_lowpass_altivec", |
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81 "avg_h264_qpel16_h_lowpass_altivec", |
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82 "put_h264_qpel16_v_lowpass_altivec", |
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83 "avg_h264_qpel16_v_lowpass_altivec", |
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84 "put_h264_qpel16_hv_lowpass_altivec", |
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85 "avg_h264_qpel16_hv_lowpass_altivec", |
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86 "" |
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87 }; |
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88 #include <stdio.h> |
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89 #endif |
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90 |
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91 #ifdef POWERPC_PERFORMANCE_REPORT |
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92 void powerpc_display_perf_report(void) |
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93 { |
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94 int i, j; |
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95 av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n"); |
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96 for(i = 0 ; i < powerpc_perf_total ; i++) |
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97 { |
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98 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) |
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99 { |
2979 | 100 if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0) |
101 av_log(NULL, AV_LOG_INFO, | |
102 " Function \"%s\" (pmc%d):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n", | |
103 perfname[i], | |
104 j+1, | |
105 perfdata[j][i][powerpc_data_min], | |
106 perfdata[j][i][powerpc_data_max], | |
107 (double)perfdata[j][i][powerpc_data_sum] / | |
108 (double)perfdata[j][i][powerpc_data_num], | |
109 perfdata[j][i][powerpc_data_num]); | |
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110 } |
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111 } |
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112 } |
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113 #endif /* POWERPC_PERFORMANCE_REPORT */ |
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114 |
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115 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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116 /* |
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117 clear_blocks_dcbz32_ppc will not work properly |
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118 on PowerPC processors with a cache line size |
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119 not equal to 32 bytes. |
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120 Fortunately all processor used by Apple up to |
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121 at least the 7450 (aka second generation G4) |
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122 use 32 bytes cache line. |
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123 This is due to the use of the 'dcbz' instruction. |
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124 It simply clear to zero a single cache line, |
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125 so you need to know the cache line size to use it ! |
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126 It's absurd, but it's fast... |
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127 |
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128 update 24/06/2003 : Apple released yesterday the G5, |
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129 with a PPC970. cache line size : 128 bytes. Oups. |
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130 The semantic of dcbz was changed, it always clear |
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131 32 bytes. so the function below will work, but will |
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132 be slow. So I fixed check_dcbz_effect to use dcbzl, |
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133 which is defined to clear a cache line (as dcbz before). |
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134 So we still can distinguish, and use dcbz (32 bytes) |
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135 or dcbzl (one cache line) as required. |
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136 |
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137 see <http://developer.apple.com/technotes/tn/tn2087.html> |
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138 and <http://developer.apple.com/technotes/tn/tn2086.html> |
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139 */ |
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140 void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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141 { |
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142 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1); |
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143 register int misal = ((unsigned long)blocks & 0x00000010); |
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144 register int i = 0; |
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145 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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146 #if 1 |
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147 if (misal) { |
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148 ((unsigned long*)blocks)[0] = 0L; |
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149 ((unsigned long*)blocks)[1] = 0L; |
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150 ((unsigned long*)blocks)[2] = 0L; |
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151 ((unsigned long*)blocks)[3] = 0L; |
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152 i += 16; |
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153 } |
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154 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) { |
1839
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155 #ifndef __MWERKS__ |
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156 asm volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
1839
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157 #else |
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158 __dcbz( blocks, i ); |
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159 #endif |
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160 } |
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161 if (misal) { |
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162 ((unsigned long*)blocks)[188] = 0L; |
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163 ((unsigned long*)blocks)[189] = 0L; |
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164 ((unsigned long*)blocks)[190] = 0L; |
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165 ((unsigned long*)blocks)[191] = 0L; |
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166 i += 16; |
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167 } |
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168 #else |
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169 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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170 #endif |
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171 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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172 } |
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173 |
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174 /* same as above, when dcbzl clear a whole 128B cache line |
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175 i.e. the PPC970 aka G5 */ |
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176 #ifndef NO_DCBZL |
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177 void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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178 { |
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179 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1); |
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180 register int misal = ((unsigned long)blocks & 0x0000007f); |
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181 register int i = 0; |
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182 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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183 #if 1 |
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184 if (misal) { |
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185 // we could probably also optimize this case, |
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186 // but there's not much point as the machines |
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187 // aren't available yet (2003-06-26) |
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188 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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189 } |
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190 else |
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191 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
2979 | 192 asm volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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193 } |
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194 #else |
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195 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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196 #endif |
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197 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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198 } |
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199 #else |
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200 void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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201 { |
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202 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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203 } |
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204 #endif |
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205 |
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206 #ifndef NO_DCBZL |
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207 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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208 /* update 24/06/2003 : replace dcbz by dcbzl to get |
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209 the intended effect (Apple "fixed" dcbz) |
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210 unfortunately this cannot be used unless the assembler |
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211 knows about dcbzl ... */ |
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212 long check_dcbzl_effect(void) |
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213 { |
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214 register char *fakedata = (char*)av_malloc(1024); |
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215 register char *fakedata_middle; |
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216 register long zero = 0; |
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217 register long i = 0; |
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218 long count = 0; |
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219 |
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220 if (!fakedata) |
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221 { |
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222 return 0L; |
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223 } |
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224 |
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225 fakedata_middle = (fakedata + 512); |
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226 |
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227 memset(fakedata, 0xFF, 1024); |
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228 |
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229 /* below the constraint "b" seems to mean "Address base register" |
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230 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */ |
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231 asm volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero)); |
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232 |
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233 for (i = 0; i < 1024 ; i ++) |
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234 { |
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235 if (fakedata[i] == (char)0) |
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236 count++; |
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237 } |
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238 |
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239 av_free(fakedata); |
2967 | 240 |
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241 return count; |
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242 } |
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243 #else |
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244 long check_dcbzl_effect(void) |
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245 { |
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246 return 0; |
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247 } |
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248 #endif |
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249 |
1092 | 250 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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251 { |
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252 // Common optimizations whether Altivec is available or not |
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253 |
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254 switch (check_dcbzl_effect()) { |
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255 case 32: |
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256 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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257 break; |
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258 case 128: |
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259 c->clear_blocks = clear_blocks_dcbz128_ppc; |
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260 break; |
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261 default: |
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262 break; |
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263 } |
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264 |
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265 #ifdef HAVE_ALTIVEC |
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266 dsputil_h264_init_ppc(c, avctx); |
2967 | 267 |
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268 if (has_altivec()) { |
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269 mm_flags |= MM_ALTIVEC; |
2967 | 270 |
3547 | 271 dsputil_init_altivec(c, avctx); |
272 snow_init_altivec(c, avctx); | |
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273 vc1dsp_init_altivec(c, avctx); |
3581 | 274 float_init_altivec(c, avctx); |
2979 | 275 c->gmc1 = gmc1_altivec; |
1092 | 276 |
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277 #ifdef CONFIG_ENCODERS |
2979 | 278 if (avctx->dct_algo == FF_DCT_AUTO || |
279 avctx->dct_algo == FF_DCT_ALTIVEC) | |
280 { | |
281 c->fdct = fdct_altivec; | |
282 } | |
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283 #endif //CONFIG_ENCODERS |
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284 |
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285 if (avctx->lowres==0) |
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286 { |
1092 | 287 if ((avctx->idct_algo == FF_IDCT_AUTO) || |
288 (avctx->idct_algo == FF_IDCT_ALTIVEC)) | |
289 { | |
290 c->idct_put = idct_put_altivec; | |
291 c->idct_add = idct_add_altivec; | |
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292 #ifndef ALTIVEC_USE_REFERENCE_C_CODE |
1092 | 293 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; |
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294 #else /* ALTIVEC_USE_REFERENCE_C_CODE */ |
1092 | 295 c->idct_permutation_type = FF_NO_IDCT_PERM; |
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296 #endif /* ALTIVEC_USE_REFERENCE_C_CODE */ |
1092 | 297 } |
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298 } |
2967 | 299 |
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300 #ifdef POWERPC_PERFORMANCE_REPORT |
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301 { |
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302 int i, j; |
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303 for (i = 0 ; i < powerpc_perf_total ; i++) |
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304 { |
2979 | 305 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) |
306 { | |
307 perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL; | |
308 perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL; | |
309 perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL; | |
310 perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL; | |
311 } | |
312 } | |
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313 } |
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314 #endif /* POWERPC_PERFORMANCE_REPORT */ |
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315 } else |
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316 #endif /* HAVE_ALTIVEC */ |
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317 { |
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318 // Non-AltiVec PPC optimisations |
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319 |
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320 // ... pending ... |
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321 } |
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322 } |