Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 3537:f52e3f60481b libavcodec
Some AltiVec optimizations for VC-1
author | kostya |
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date | Thu, 03 Aug 2006 05:02:31 +0000 |
parents | 95e2e92328c0 |
children | bdbe52f38868 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org> |
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5 * |
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6 * This library is free software; you can redistribute it and/or |
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7 * modify it under the terms of the GNU Lesser General Public |
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8 * License as published by the Free Software Foundation; either |
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9 * version 2 of the License, or (at your option) any later version. |
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10 * |
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11 * This library is distributed in the hope that it will be useful, |
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 * Lesser General Public License for more details. |
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15 * |
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16 * You should have received a copy of the GNU Lesser General Public |
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17 * License along with this library; if not, write to the Free Software |
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18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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19 */ |
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20 |
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21 #include "../dsputil.h" |
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22 |
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23 #include "dsputil_ppc.h" |
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24 |
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25 #ifdef HAVE_ALTIVEC |
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26 #include "dsputil_altivec.h" |
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27 |
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28 extern void fdct_altivec(int16_t *block); |
1092 | 29 extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block); |
30 extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block); | |
3223 | 31 extern void ff_snow_horizontal_compose97i_altivec(DWTELEM *b, int width); |
32 extern void ff_snow_vertical_compose97i_altivec(DWTELEM *b0, DWTELEM *b1, | |
33 DWTELEM *b2, DWTELEM *b3, | |
34 DWTELEM *b4, DWTELEM *b5, | |
35 int width); | |
3532 | 36 extern void ff_snow_inner_add_yblock_altivec(uint8_t *obmc, |
37 const int obmc_stride, | |
38 uint8_t * * block, int b_w, | |
39 int b_h, int src_x, int src_y, | |
40 int src_stride, slice_buffer * sb, | |
41 int add, uint8_t * dst8); | |
42 | |
43 void dsputil_h264_init_ppc(DSPContext* c, AVCodecContext *avctx); | |
44 | |
45 #endif | |
3223 | 46 |
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47 int mm_flags = 0; |
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48 |
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49 int mm_support(void) |
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50 { |
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51 int result = 0; |
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52 #ifdef HAVE_ALTIVEC |
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53 if (has_altivec()) { |
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54 result |= MM_ALTIVEC; |
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55 } |
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56 #endif /* result */ |
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57 return result; |
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58 } |
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59 |
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60 #ifdef POWERPC_PERFORMANCE_REPORT |
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61 unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total]; |
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62 /* list below must match enum in dsputil_ppc.h */ |
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63 static unsigned char* perfname[] = { |
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64 "ff_fft_calc_altivec", |
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65 "gmc1_altivec", |
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66 "dct_unquantize_h263_altivec", |
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67 "fdct_altivec", |
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68 "idct_add_altivec", |
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69 "idct_put_altivec", |
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70 "put_pixels16_altivec", |
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71 "avg_pixels16_altivec", |
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72 "avg_pixels8_altivec", |
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73 "put_pixels8_xy2_altivec", |
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74 "put_no_rnd_pixels8_xy2_altivec", |
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75 "put_pixels16_xy2_altivec", |
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76 "put_no_rnd_pixels16_xy2_altivec", |
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77 "hadamard8_diff8x8_altivec", |
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78 "hadamard8_diff16_altivec", |
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79 "avg_pixels8_xy2_altivec", |
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80 "clear_blocks_dcbz32_ppc", |
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81 "clear_blocks_dcbz128_ppc", |
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82 "put_h264_chroma_mc8_altivec", |
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83 "avg_h264_chroma_mc8_altivec", |
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84 "put_h264_qpel16_h_lowpass_altivec", |
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85 "avg_h264_qpel16_h_lowpass_altivec", |
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86 "put_h264_qpel16_v_lowpass_altivec", |
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87 "avg_h264_qpel16_v_lowpass_altivec", |
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88 "put_h264_qpel16_hv_lowpass_altivec", |
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89 "avg_h264_qpel16_hv_lowpass_altivec", |
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90 "" |
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91 }; |
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92 #include <stdio.h> |
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93 #endif |
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94 |
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95 #ifdef POWERPC_PERFORMANCE_REPORT |
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96 void powerpc_display_perf_report(void) |
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97 { |
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98 int i, j; |
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99 av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n"); |
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100 for(i = 0 ; i < powerpc_perf_total ; i++) |
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101 { |
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102 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) |
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103 { |
2979 | 104 if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0) |
105 av_log(NULL, AV_LOG_INFO, | |
106 " Function \"%s\" (pmc%d):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n", | |
107 perfname[i], | |
108 j+1, | |
109 perfdata[j][i][powerpc_data_min], | |
110 perfdata[j][i][powerpc_data_max], | |
111 (double)perfdata[j][i][powerpc_data_sum] / | |
112 (double)perfdata[j][i][powerpc_data_num], | |
113 perfdata[j][i][powerpc_data_num]); | |
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114 } |
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115 } |
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116 } |
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117 #endif /* POWERPC_PERFORMANCE_REPORT */ |
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118 |
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119 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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120 /* |
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121 clear_blocks_dcbz32_ppc will not work properly |
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122 on PowerPC processors with a cache line size |
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123 not equal to 32 bytes. |
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124 Fortunately all processor used by Apple up to |
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125 at least the 7450 (aka second generation G4) |
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126 use 32 bytes cache line. |
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127 This is due to the use of the 'dcbz' instruction. |
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128 It simply clear to zero a single cache line, |
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129 so you need to know the cache line size to use it ! |
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130 It's absurd, but it's fast... |
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131 |
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132 update 24/06/2003 : Apple released yesterday the G5, |
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133 with a PPC970. cache line size : 128 bytes. Oups. |
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134 The semantic of dcbz was changed, it always clear |
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135 32 bytes. so the function below will work, but will |
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136 be slow. So I fixed check_dcbz_effect to use dcbzl, |
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137 which is defined to clear a cache line (as dcbz before). |
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138 So we still can distinguish, and use dcbz (32 bytes) |
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139 or dcbzl (one cache line) as required. |
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140 |
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141 see <http://developer.apple.com/technotes/tn/tn2087.html> |
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142 and <http://developer.apple.com/technotes/tn/tn2086.html> |
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143 */ |
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144 void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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145 { |
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146 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1); |
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147 register int misal = ((unsigned long)blocks & 0x00000010); |
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148 register int i = 0; |
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149 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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150 #if 1 |
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151 if (misal) { |
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152 ((unsigned long*)blocks)[0] = 0L; |
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153 ((unsigned long*)blocks)[1] = 0L; |
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154 ((unsigned long*)blocks)[2] = 0L; |
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155 ((unsigned long*)blocks)[3] = 0L; |
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156 i += 16; |
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157 } |
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158 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) { |
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159 #ifndef __MWERKS__ |
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160 asm volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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161 #else |
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162 __dcbz( blocks, i ); |
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163 #endif |
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164 } |
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165 if (misal) { |
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166 ((unsigned long*)blocks)[188] = 0L; |
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167 ((unsigned long*)blocks)[189] = 0L; |
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168 ((unsigned long*)blocks)[190] = 0L; |
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169 ((unsigned long*)blocks)[191] = 0L; |
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170 i += 16; |
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171 } |
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172 #else |
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173 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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174 #endif |
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175 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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176 } |
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177 |
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178 /* same as above, when dcbzl clear a whole 128B cache line |
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179 i.e. the PPC970 aka G5 */ |
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180 #ifndef NO_DCBZL |
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181 void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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182 { |
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183 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1); |
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184 register int misal = ((unsigned long)blocks & 0x0000007f); |
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185 register int i = 0; |
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186 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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187 #if 1 |
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188 if (misal) { |
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189 // we could probably also optimize this case, |
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190 // but there's not much point as the machines |
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191 // aren't available yet (2003-06-26) |
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192 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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193 } |
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194 else |
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195 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
2979 | 196 asm volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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197 } |
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198 #else |
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199 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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200 #endif |
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201 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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202 } |
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203 #else |
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204 void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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205 { |
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206 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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207 } |
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208 #endif |
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209 |
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210 #ifndef NO_DCBZL |
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211 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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212 /* update 24/06/2003 : replace dcbz by dcbzl to get |
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213 the intended effect (Apple "fixed" dcbz) |
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214 unfortunately this cannot be used unless the assembler |
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215 knows about dcbzl ... */ |
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216 long check_dcbzl_effect(void) |
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217 { |
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218 register char *fakedata = (char*)av_malloc(1024); |
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219 register char *fakedata_middle; |
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220 register long zero = 0; |
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221 register long i = 0; |
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222 long count = 0; |
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223 |
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224 if (!fakedata) |
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225 { |
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226 return 0L; |
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227 } |
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228 |
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229 fakedata_middle = (fakedata + 512); |
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230 |
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231 memset(fakedata, 0xFF, 1024); |
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232 |
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233 /* below the constraint "b" seems to mean "Address base register" |
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234 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */ |
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235 asm volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero)); |
1015
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236 |
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237 for (i = 0; i < 1024 ; i ++) |
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238 { |
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239 if (fakedata[i] == (char)0) |
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240 count++; |
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241 } |
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242 |
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243 av_free(fakedata); |
2967 | 244 |
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245 return count; |
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246 } |
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247 #else |
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248 long check_dcbzl_effect(void) |
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249 { |
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250 return 0; |
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251 } |
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252 #endif |
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253 |
3537 | 254 #ifdef HAVE_ALTIVEC |
255 void vc1dsp_init_altivec(DSPContext* c, AVCodecContext *avctx); | |
256 #endif | |
257 | |
1092 | 258 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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259 { |
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260 // Common optimizations whether Altivec is available or not |
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261 |
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262 switch (check_dcbzl_effect()) { |
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263 case 32: |
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264 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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265 break; |
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266 case 128: |
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267 c->clear_blocks = clear_blocks_dcbz128_ppc; |
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268 break; |
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269 default: |
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270 break; |
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271 } |
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272 |
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273 #ifdef HAVE_ALTIVEC |
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274 dsputil_h264_init_ppc(c, avctx); |
2967 | 275 |
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276 if (has_altivec()) { |
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277 mm_flags |= MM_ALTIVEC; |
2967 | 278 |
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279 // Altivec specific optimisations |
1708 | 280 c->pix_abs[0][1] = sad16_x2_altivec; |
281 c->pix_abs[0][2] = sad16_y2_altivec; | |
282 c->pix_abs[0][3] = sad16_xy2_altivec; | |
283 c->pix_abs[0][0] = sad16_altivec; | |
284 c->pix_abs[1][0] = sad8_altivec; | |
285 c->sad[0]= sad16_altivec; | |
286 c->sad[1]= sad8_altivec; | |
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287 c->pix_norm1 = pix_norm1_altivec; |
981 | 288 c->sse[1]= sse8_altivec; |
289 c->sse[0]= sse16_altivec; | |
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290 c->pix_sum = pix_sum_altivec; |
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291 c->diff_pixels = diff_pixels_altivec; |
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292 c->get_pixels = get_pixels_altivec; |
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293 // next one disabled as it's untested. |
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294 #if 0 |
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295 c->add_bytes= add_bytes_altivec; |
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296 #endif /* 0 */ |
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297 c->put_pixels_tab[0][0] = put_pixels16_altivec; |
1949
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298 /* the two functions do the same thing, so use the same code */ |
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299 c->put_no_rnd_pixels_tab[0][0] = put_pixels16_altivec; |
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300 c->avg_pixels_tab[0][0] = avg_pixels16_altivec; |
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301 c->avg_pixels_tab[1][0] = avg_pixels8_altivec; |
2979 | 302 c->avg_pixels_tab[1][3] = avg_pixels8_xy2_altivec; |
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303 c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec; |
1024
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304 c->put_no_rnd_pixels_tab[1][3] = put_no_rnd_pixels8_xy2_altivec; |
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305 c->put_pixels_tab[0][3] = put_pixels16_xy2_altivec; |
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306 c->put_no_rnd_pixels_tab[0][3] = put_no_rnd_pixels16_xy2_altivec; |
2967 | 307 |
2979 | 308 c->gmc1 = gmc1_altivec; |
1092 | 309 |
2979 | 310 c->hadamard8_diff[0] = hadamard8_diff16_altivec; |
311 c->hadamard8_diff[1] = hadamard8_diff8x8_altivec; | |
1949
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312 |
3223 | 313 c->horizontal_compose97i = ff_snow_horizontal_compose97i_altivec; |
314 c->vertical_compose97i = ff_snow_vertical_compose97i_altivec; | |
315 c->inner_add_yblock = ff_snow_inner_add_yblock_altivec; | |
316 | |
3537 | 317 vc1dsp_init_altivec(c, avctx); |
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318 #ifdef CONFIG_ENCODERS |
2979 | 319 if (avctx->dct_algo == FF_DCT_AUTO || |
320 avctx->dct_algo == FF_DCT_ALTIVEC) | |
321 { | |
322 c->fdct = fdct_altivec; | |
323 } | |
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324 #endif //CONFIG_ENCODERS |
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325 |
2778
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326 if (avctx->lowres==0) |
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327 { |
1092 | 328 if ((avctx->idct_algo == FF_IDCT_AUTO) || |
329 (avctx->idct_algo == FF_IDCT_ALTIVEC)) | |
330 { | |
331 c->idct_put = idct_put_altivec; | |
332 c->idct_add = idct_add_altivec; | |
333 #ifndef ALTIVEC_USE_REFERENCE_C_CODE | |
334 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; | |
335 #else /* ALTIVEC_USE_REFERENCE_C_CODE */ | |
336 c->idct_permutation_type = FF_NO_IDCT_PERM; | |
337 #endif /* ALTIVEC_USE_REFERENCE_C_CODE */ | |
338 } | |
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339 } |
2967 | 340 |
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341 #ifdef POWERPC_PERFORMANCE_REPORT |
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342 { |
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343 int i, j; |
1015
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344 for (i = 0 ; i < powerpc_perf_total ; i++) |
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345 { |
2979 | 346 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) |
347 { | |
348 perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL; | |
349 perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL; | |
350 perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL; | |
351 perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL; | |
352 } | |
353 } | |
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AltiVec perf (take 2), plus a couple AltiVec functions by (Romain Dolbeau <dolbeau at irisa dot fr>)
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|
354 } |
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|
355 #endif /* POWERPC_PERFORMANCE_REPORT */ |
638
0012f75c92bb
altivec build tidyup patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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356 } else |
1024
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357 #endif /* HAVE_ALTIVEC */ |
638
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358 { |
828
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359 // Non-AltiVec PPC optimisations |
ace3ccd18dd2
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360 |
ace3ccd18dd2
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361 // ... pending ... |
638
0012f75c92bb
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362 } |
0012f75c92bb
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363 } |