Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 11887:c432b63b345e libavcodec
psdec: Factorize iid/icc/ipd/opd parameter bitstream reading.
author | alexc |
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date | Sat, 19 Jun 2010 23:53:21 +0000 |
parents | 50415a8f1451 |
children | 3cd4cd0509cd |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org> |
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5 * |
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6 * This file is part of FFmpeg. |
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7 * |
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8 * FFmpeg is free software; you can redistribute it and/or |
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9 * modify it under the terms of the GNU Lesser General Public |
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10 * License as published by the Free Software Foundation; either |
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11 * version 2.1 of the License, or (at your option) any later version. |
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12 * |
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13 * FFmpeg is distributed in the hope that it will be useful, |
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 * Lesser General Public License for more details. |
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17 * |
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18 * You should have received a copy of the GNU Lesser General Public |
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19 * License along with FFmpeg; if not, write to the Free Software |
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20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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21 */ |
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22 |
6763 | 23 #include "libavcodec/dsputil.h" |
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24 |
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25 #include "dsputil_ppc.h" |
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26 |
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27 #include "dsputil_altivec.h" |
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28 |
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30 |
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31 int mm_support(void) |
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32 { |
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33 int result = 0; |
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35 if (has_altivec()) { |
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36 result |= FF_MM_ALTIVEC; |
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37 } |
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38 #endif /* result */ |
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39 return result; |
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40 } |
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41 |
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43 unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total]; |
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44 /* list below must match enum in dsputil_ppc.h */ |
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45 static unsigned char* perfname[] = { |
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46 "ff_fft_calc_altivec", |
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47 "gmc1_altivec", |
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48 "dct_unquantize_h263_altivec", |
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49 "fdct_altivec", |
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50 "idct_add_altivec", |
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51 "idct_put_altivec", |
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52 "put_pixels16_altivec", |
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53 "avg_pixels16_altivec", |
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54 "avg_pixels8_altivec", |
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55 "put_pixels8_xy2_altivec", |
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56 "put_no_rnd_pixels8_xy2_altivec", |
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57 "put_pixels16_xy2_altivec", |
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58 "put_no_rnd_pixels16_xy2_altivec", |
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59 "hadamard8_diff8x8_altivec", |
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60 "hadamard8_diff16_altivec", |
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61 "avg_pixels8_xy2_altivec", |
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62 "clear_blocks_dcbz32_ppc", |
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63 "clear_blocks_dcbz128_ppc", |
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64 "put_h264_chroma_mc8_altivec", |
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65 "avg_h264_chroma_mc8_altivec", |
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66 "put_h264_qpel16_h_lowpass_altivec", |
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67 "avg_h264_qpel16_h_lowpass_altivec", |
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68 "put_h264_qpel16_v_lowpass_altivec", |
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69 "avg_h264_qpel16_v_lowpass_altivec", |
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70 "put_h264_qpel16_hv_lowpass_altivec", |
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71 "avg_h264_qpel16_hv_lowpass_altivec", |
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72 "" |
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73 }; |
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74 #include <stdio.h> |
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75 #endif |
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76 |
8590 | 77 #if CONFIG_POWERPC_PERF |
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78 void powerpc_display_perf_report(void) |
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79 { |
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80 int i, j; |
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81 av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n"); |
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82 for(i = 0 ; i < powerpc_perf_total ; i++) { |
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83 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) { |
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84 if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0) |
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85 av_log(NULL, AV_LOG_INFO, |
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86 " Function \"%s\" (pmc%d):\n\tmin: %"PRIu64"\n\tmax: %"PRIu64"\n\tavg: %1.2lf (%"PRIu64")\n", |
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87 perfname[i], |
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88 j+1, |
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89 perfdata[j][i][powerpc_data_min], |
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90 perfdata[j][i][powerpc_data_max], |
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91 (double)perfdata[j][i][powerpc_data_sum] / |
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92 (double)perfdata[j][i][powerpc_data_num], |
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93 perfdata[j][i][powerpc_data_num]); |
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94 } |
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95 } |
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96 } |
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97 #endif /* CONFIG_POWERPC_PERF */ |
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98 |
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99 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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100 /* |
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101 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a |
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102 cache line size not equal to 32 bytes. |
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103 Fortunately all processor used by Apple up to at least the 7450 (aka second |
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104 generation G4) use 32 bytes cache line. |
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105 This is due to the use of the 'dcbz' instruction. It simply clear to zero a |
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106 single cache line, so you need to know the cache line size to use it ! |
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107 It's absurd, but it's fast... |
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108 |
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109 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line |
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110 size: 128 bytes. Oups. |
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111 The semantic of dcbz was changed, it always clear 32 bytes. so the function |
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112 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl, |
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113 which is defined to clear a cache line (as dcbz before). So we still can |
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114 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required. |
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115 |
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116 see <http://developer.apple.com/technotes/tn/tn2087.html> |
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117 and <http://developer.apple.com/technotes/tn/tn2086.html> |
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118 */ |
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119 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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120 { |
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121 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1); |
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122 register int misal = ((unsigned long)blocks & 0x00000010); |
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123 register int i = 0; |
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124 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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125 #if 1 |
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126 if (misal) { |
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127 ((unsigned long*)blocks)[0] = 0L; |
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128 ((unsigned long*)blocks)[1] = 0L; |
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129 ((unsigned long*)blocks)[2] = 0L; |
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130 ((unsigned long*)blocks)[3] = 0L; |
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131 i += 16; |
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132 } |
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133 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) { |
8031 | 134 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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135 } |
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136 if (misal) { |
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137 ((unsigned long*)blocks)[188] = 0L; |
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138 ((unsigned long*)blocks)[189] = 0L; |
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139 ((unsigned long*)blocks)[190] = 0L; |
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140 ((unsigned long*)blocks)[191] = 0L; |
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141 i += 16; |
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142 } |
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143 #else |
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144 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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145 #endif |
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146 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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147 } |
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148 |
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149 /* same as above, when dcbzl clear a whole 128B cache line |
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150 i.e. the PPC970 aka G5 */ |
8590 | 151 #if HAVE_DCBZL |
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152 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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153 { |
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154 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1); |
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155 register int misal = ((unsigned long)blocks & 0x0000007f); |
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156 register int i = 0; |
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157 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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158 #if 1 |
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159 if (misal) { |
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160 // we could probably also optimize this case, |
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161 // but there's not much point as the machines |
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162 // aren't available yet (2003-06-26) |
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163 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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164 } |
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165 else |
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166 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
8031 | 167 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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168 } |
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169 #else |
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170 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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171 #endif |
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172 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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173 } |
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174 #else |
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175 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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176 { |
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177 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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178 } |
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179 #endif |
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180 |
8590 | 181 #if HAVE_DCBZL |
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182 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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183 /* update 24/06/2003 : replace dcbz by dcbzl to get |
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184 the intended effect (Apple "fixed" dcbz) |
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185 unfortunately this cannot be used unless the assembler |
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186 knows about dcbzl ... */ |
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187 static long check_dcbzl_effect(void) |
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188 { |
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189 register char *fakedata = av_malloc(1024); |
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190 register char *fakedata_middle; |
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191 register long zero = 0; |
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192 register long i = 0; |
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193 long count = 0; |
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194 |
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195 if (!fakedata) { |
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196 return 0L; |
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197 } |
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198 |
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199 fakedata_middle = (fakedata + 512); |
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200 |
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201 memset(fakedata, 0xFF, 1024); |
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202 |
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203 /* below the constraint "b" seems to mean "Address base register" |
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204 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */ |
8031 | 205 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero)); |
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206 |
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207 for (i = 0; i < 1024 ; i ++) { |
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208 if (fakedata[i] == (char)0) |
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209 count++; |
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210 } |
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211 |
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212 av_free(fakedata); |
2967 | 213 |
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214 return count; |
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215 } |
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216 #else |
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217 static long check_dcbzl_effect(void) |
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218 { |
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219 return 0; |
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220 } |
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221 #endif |
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222 |
4003 | 223 static void prefetch_ppc(void *mem, int stride, int h) |
224 { | |
225 register const uint8_t *p = mem; | |
226 do { | |
8031 | 227 __asm__ volatile ("dcbt 0,%0" : : "r" (p)); |
4003 | 228 p+= stride; |
229 } while(--h); | |
230 } | |
231 | |
1092 | 232 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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233 { |
5749 | 234 // Common optimizations whether AltiVec is available or not |
4003 | 235 c->prefetch = prefetch_ppc; |
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236 switch (check_dcbzl_effect()) { |
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237 case 32: |
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238 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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239 break; |
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240 case 128: |
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241 c->clear_blocks = clear_blocks_dcbz128_ppc; |
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242 break; |
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243 default: |
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244 break; |
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245 } |
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246 |
8590 | 247 #if HAVE_ALTIVEC |
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248 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx); |
2967 | 249 |
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250 if (has_altivec()) { |
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251 mm_flags |= FF_MM_ALTIVEC; |
2967 | 252 |
3547 | 253 dsputil_init_altivec(c, avctx); |
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254 if(CONFIG_VC1_DECODER) |
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255 vc1dsp_init_altivec(c, avctx); |
3581 | 256 float_init_altivec(c, avctx); |
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257 int_init_altivec(c, avctx); |
2979 | 258 c->gmc1 = gmc1_altivec; |
1092 | 259 |
8590 | 260 #if CONFIG_ENCODERS |
2979 | 261 if (avctx->dct_algo == FF_DCT_AUTO || |
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262 avctx->dct_algo == FF_DCT_ALTIVEC) { |
2979 | 263 c->fdct = fdct_altivec; |
264 } | |
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265 #endif //CONFIG_ENCODERS |
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266 |
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267 if (avctx->lowres==0) { |
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268 if ((avctx->idct_algo == FF_IDCT_AUTO) || |
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269 (avctx->idct_algo == FF_IDCT_ALTIVEC)) { |
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270 c->idct_put = idct_put_altivec; |
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271 c->idct_add = idct_add_altivec; |
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272 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; |
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273 }else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) && |
9711 | 274 avctx->idct_algo==FF_IDCT_VP3){ |
275 c->idct_put = ff_vp3_idct_put_altivec; | |
276 c->idct_add = ff_vp3_idct_add_altivec; | |
277 c->idct = ff_vp3_idct_altivec; | |
278 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; | |
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279 } |
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280 } |
2967 | 281 |
8590 | 282 #if CONFIG_POWERPC_PERF |
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283 { |
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284 int i, j; |
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285 for (i = 0 ; i < powerpc_perf_total ; i++) { |
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286 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) { |
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287 perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL; |
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288 perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL; |
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289 perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL; |
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290 perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL; |
7334 | 291 } |
292 } | |
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293 } |
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294 #endif /* CONFIG_POWERPC_PERF */ |
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295 } |
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296 #endif /* HAVE_ALTIVEC */ |
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297 } |