Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 7263:fc843d00867c libavcodec
exploit mdct symmetry
2% faster vorbis on conroe, k8. 7% on celeron.
author | lorenm |
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date | Sun, 13 Jul 2008 15:03:58 +0000 |
parents | f7cbb7733146 |
children | a8a79f5385f6 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org> |
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5 * |
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6 * This file is part of FFmpeg. |
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7 * |
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8 * FFmpeg is free software; you can redistribute it and/or |
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9 * modify it under the terms of the GNU Lesser General Public |
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10 * License as published by the Free Software Foundation; either |
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11 * version 2.1 of the License, or (at your option) any later version. |
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12 * |
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13 * FFmpeg is distributed in the hope that it will be useful, |
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 * Lesser General Public License for more details. |
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17 * |
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18 * You should have received a copy of the GNU Lesser General Public |
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19 * License along with FFmpeg; if not, write to the Free Software |
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20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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21 */ |
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22 |
6763 | 23 #include "libavcodec/dsputil.h" |
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24 |
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25 #include "dsputil_ppc.h" |
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26 |
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27 #ifdef HAVE_ALTIVEC |
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28 #include "dsputil_altivec.h" |
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29 |
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30 extern void fdct_altivec(int16_t *block); |
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31 extern void gmc1_altivec(uint8_t *dst, uint8_t *src, int stride, int h, |
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32 int x16, int y16, int rounder); |
1092 | 33 extern void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block); |
34 extern void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block); | |
3547 | 35 |
36 void dsputil_h264_init_ppc(DSPContext* c, AVCodecContext *avctx); | |
3532 | 37 |
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38 void dsputil_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3542 | 39 void vc1dsp_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3547 | 40 void snow_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3581 | 41 void float_init_altivec(DSPContext* c, AVCodecContext *avctx); |
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42 void int_init_altivec(DSPContext* c, AVCodecContext *avctx); |
3532 | 43 |
44 #endif | |
3223 | 45 |
4197 | 46 int mm_flags = 0; |
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47 |
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48 int mm_support(void) |
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49 { |
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50 int result = 0; |
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51 #ifdef HAVE_ALTIVEC |
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52 if (has_altivec()) { |
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53 result |= MM_ALTIVEC; |
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54 } |
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55 #endif /* result */ |
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56 return result; |
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57 } |
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58 |
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59 #ifdef CONFIG_POWERPC_PERF |
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60 unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total]; |
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61 /* list below must match enum in dsputil_ppc.h */ |
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62 static unsigned char* perfname[] = { |
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63 "ff_fft_calc_altivec", |
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64 "gmc1_altivec", |
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65 "dct_unquantize_h263_altivec", |
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66 "fdct_altivec", |
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67 "idct_add_altivec", |
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68 "idct_put_altivec", |
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69 "put_pixels16_altivec", |
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70 "avg_pixels16_altivec", |
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71 "avg_pixels8_altivec", |
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72 "put_pixels8_xy2_altivec", |
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73 "put_no_rnd_pixels8_xy2_altivec", |
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74 "put_pixels16_xy2_altivec", |
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75 "put_no_rnd_pixels16_xy2_altivec", |
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76 "hadamard8_diff8x8_altivec", |
1951
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77 "hadamard8_diff16_altivec", |
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78 "avg_pixels8_xy2_altivec", |
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79 "clear_blocks_dcbz32_ppc", |
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80 "clear_blocks_dcbz128_ppc", |
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81 "put_h264_chroma_mc8_altivec", |
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82 "avg_h264_chroma_mc8_altivec", |
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83 "put_h264_qpel16_h_lowpass_altivec", |
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84 "avg_h264_qpel16_h_lowpass_altivec", |
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85 "put_h264_qpel16_v_lowpass_altivec", |
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86 "avg_h264_qpel16_v_lowpass_altivec", |
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87 "put_h264_qpel16_hv_lowpass_altivec", |
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88 "avg_h264_qpel16_hv_lowpass_altivec", |
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89 "" |
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90 }; |
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91 #include <stdio.h> |
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92 #endif |
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93 |
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94 #ifdef CONFIG_POWERPC_PERF |
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95 void powerpc_display_perf_report(void) |
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96 { |
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97 int i, j; |
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98 av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n"); |
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99 for(i = 0 ; i < powerpc_perf_total ; i++) |
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100 { |
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101 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) |
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102 { |
2979 | 103 if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0) |
104 av_log(NULL, AV_LOG_INFO, | |
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105 " Function \"%s\" (pmc%d):\n\tmin: %"PRIu64"\n\tmax: %"PRIu64"\n\tavg: %1.2lf (%"PRIu64")\n", |
2979 | 106 perfname[i], |
107 j+1, | |
108 perfdata[j][i][powerpc_data_min], | |
109 perfdata[j][i][powerpc_data_max], | |
110 (double)perfdata[j][i][powerpc_data_sum] / | |
111 (double)perfdata[j][i][powerpc_data_num], | |
112 perfdata[j][i][powerpc_data_num]); | |
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113 } |
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114 } |
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115 } |
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116 #endif /* CONFIG_POWERPC_PERF */ |
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117 |
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118 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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119 /* |
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120 clear_blocks_dcbz32_ppc will not work properly |
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121 on PowerPC processors with a cache line size |
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122 not equal to 32 bytes. |
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123 Fortunately all processor used by Apple up to |
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124 at least the 7450 (aka second generation G4) |
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125 use 32 bytes cache line. |
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126 This is due to the use of the 'dcbz' instruction. |
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127 It simply clear to zero a single cache line, |
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128 so you need to know the cache line size to use it ! |
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129 It's absurd, but it's fast... |
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130 |
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131 update 24/06/2003 : Apple released yesterday the G5, |
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132 with a PPC970. cache line size : 128 bytes. Oups. |
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133 The semantic of dcbz was changed, it always clear |
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134 32 bytes. so the function below will work, but will |
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135 be slow. So I fixed check_dcbz_effect to use dcbzl, |
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136 which is defined to clear a cache line (as dcbz before). |
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137 So we still can distinguish, and use dcbz (32 bytes) |
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138 or dcbzl (one cache line) as required. |
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139 |
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140 see <http://developer.apple.com/technotes/tn/tn2087.html> |
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141 and <http://developer.apple.com/technotes/tn/tn2086.html> |
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142 */ |
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143 void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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144 { |
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145 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1); |
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146 register int misal = ((unsigned long)blocks & 0x00000010); |
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147 register int i = 0; |
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148 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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149 #if 1 |
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150 if (misal) { |
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151 ((unsigned long*)blocks)[0] = 0L; |
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152 ((unsigned long*)blocks)[1] = 0L; |
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153 ((unsigned long*)blocks)[2] = 0L; |
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154 ((unsigned long*)blocks)[3] = 0L; |
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155 i += 16; |
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156 } |
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157 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) { |
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158 asm volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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159 } |
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160 if (misal) { |
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161 ((unsigned long*)blocks)[188] = 0L; |
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162 ((unsigned long*)blocks)[189] = 0L; |
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163 ((unsigned long*)blocks)[190] = 0L; |
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164 ((unsigned long*)blocks)[191] = 0L; |
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165 i += 16; |
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166 } |
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167 #else |
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168 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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169 #endif |
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170 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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171 } |
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172 |
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173 /* same as above, when dcbzl clear a whole 128B cache line |
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174 i.e. the PPC970 aka G5 */ |
3949 | 175 #ifdef HAVE_DCBZL |
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176 void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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177 { |
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178 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1); |
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179 register int misal = ((unsigned long)blocks & 0x0000007f); |
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180 register int i = 0; |
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181 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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182 #if 1 |
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183 if (misal) { |
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184 // we could probably also optimize this case, |
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185 // but there's not much point as the machines |
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186 // aren't available yet (2003-06-26) |
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187 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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188 } |
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189 else |
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190 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
2979 | 191 asm volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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192 } |
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193 #else |
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194 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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195 #endif |
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196 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1); |
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197 } |
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198 #else |
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199 void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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200 { |
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201 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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202 } |
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203 #endif |
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204 |
3949 | 205 #ifdef HAVE_DCBZL |
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206 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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207 /* update 24/06/2003 : replace dcbz by dcbzl to get |
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208 the intended effect (Apple "fixed" dcbz) |
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209 unfortunately this cannot be used unless the assembler |
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210 knows about dcbzl ... */ |
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211 long check_dcbzl_effect(void) |
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212 { |
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213 register char *fakedata = av_malloc(1024); |
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214 register char *fakedata_middle; |
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215 register long zero = 0; |
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216 register long i = 0; |
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217 long count = 0; |
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218 |
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219 if (!fakedata) |
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220 { |
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221 return 0L; |
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222 } |
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223 |
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224 fakedata_middle = (fakedata + 512); |
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225 |
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226 memset(fakedata, 0xFF, 1024); |
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227 |
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228 /* below the constraint "b" seems to mean "Address base register" |
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229 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */ |
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230 asm volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero)); |
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231 |
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232 for (i = 0; i < 1024 ; i ++) |
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233 { |
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234 if (fakedata[i] == (char)0) |
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235 count++; |
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236 } |
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237 |
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238 av_free(fakedata); |
2967 | 239 |
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240 return count; |
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241 } |
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242 #else |
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243 long check_dcbzl_effect(void) |
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244 { |
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245 return 0; |
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246 } |
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247 #endif |
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248 |
4003 | 249 static void prefetch_ppc(void *mem, int stride, int h) |
250 { | |
251 register const uint8_t *p = mem; | |
252 do { | |
253 asm volatile ("dcbt 0,%0" : : "r" (p)); | |
254 p+= stride; | |
255 } while(--h); | |
256 } | |
257 | |
1092 | 258 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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259 { |
5749 | 260 // Common optimizations whether AltiVec is available or not |
4003 | 261 c->prefetch = prefetch_ppc; |
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262 switch (check_dcbzl_effect()) { |
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263 case 32: |
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264 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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265 break; |
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266 case 128: |
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267 c->clear_blocks = clear_blocks_dcbz128_ppc; |
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268 break; |
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269 default: |
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270 break; |
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271 } |
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272 |
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273 #ifdef HAVE_ALTIVEC |
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274 if(ENABLE_H264_DECODER) dsputil_h264_init_ppc(c, avctx); |
2967 | 275 |
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276 if (has_altivec()) { |
4197 | 277 mm_flags |= MM_ALTIVEC; |
2967 | 278 |
3547 | 279 dsputil_init_altivec(c, avctx); |
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280 if(ENABLE_SNOW_DECODER) snow_init_altivec(c, avctx); |
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281 if(ENABLE_VC1_DECODER || ENABLE_WMV3_DECODER) |
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282 vc1dsp_init_altivec(c, avctx); |
3581 | 283 float_init_altivec(c, avctx); |
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284 int_init_altivec(c, avctx); |
2979 | 285 c->gmc1 = gmc1_altivec; |
1092 | 286 |
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287 #ifdef CONFIG_ENCODERS |
2979 | 288 if (avctx->dct_algo == FF_DCT_AUTO || |
289 avctx->dct_algo == FF_DCT_ALTIVEC) | |
290 { | |
291 c->fdct = fdct_altivec; | |
292 } | |
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293 #endif //CONFIG_ENCODERS |
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294 |
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295 if (avctx->lowres==0) |
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296 { |
1092 | 297 if ((avctx->idct_algo == FF_IDCT_AUTO) || |
298 (avctx->idct_algo == FF_IDCT_ALTIVEC)) | |
299 { | |
300 c->idct_put = idct_put_altivec; | |
301 c->idct_add = idct_add_altivec; | |
302 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; | |
303 } | |
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304 } |
2967 | 305 |
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306 #ifdef CONFIG_POWERPC_PERF |
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307 { |
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308 int i, j; |
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309 for (i = 0 ; i < powerpc_perf_total ; i++) |
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310 { |
2979 | 311 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) |
312 { | |
313 perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL; | |
314 perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL; | |
315 perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL; | |
316 perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL; | |
317 } | |
318 } | |
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319 } |
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320 #endif /* CONFIG_POWERPC_PERF */ |
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321 } |
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322 #endif /* HAVE_ALTIVEC */ |
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323 } |