Mercurial > mplayer.hg
annotate vidix/drivers/nvidia_vid.c @ 11073:0c633f49231d
added a few more device ids
author | faust3 |
---|---|
date | Fri, 10 Oct 2003 07:12:37 +0000 |
parents | 3da6b1de1c33 |
children | 14aea5a85ba1 |
rev | line source |
---|---|
10954 | 1 /* |
2 nvidia_vid - VIDIX based video driver for NVIDIA chips | |
3 Copyrights 2003 Sascha Sommer. This file is based on sources from | |
4 RIVATV (rivatv.sf.net) | |
5 Licence: GPL | |
6 WARNING: THIS DRIVER IS IN BETTA STAGE | |
7 | |
8 multi buffer support, TNT2 fixes and experimental yv12 support by Dmitry Baryshkov | |
9 */ | |
10 | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <inttypes.h> | |
17 #include <unistd.h> | |
18 | |
19 | |
20 #include "../vidix.h" | |
21 #include "../fourcc.h" | |
22 #include "../../libdha/libdha.h" | |
23 #include "../../libdha/pci_ids.h" | |
24 #include "../../libdha/pci_names.h" | |
25 #include "../../config.h" | |
26 #include "../../bswap.h" | |
27 | |
28 | |
29 pciinfo_t pci_info; | |
30 | |
31 | |
32 #define MAX_FRAMES 3 | |
33 #define NV04_BES_SIZE 1024*2000*4 | |
34 | |
35 | |
36 static vidix_capability_t nvidia_cap = { | |
37 "NVIDIA RIVA OVERLAY DRIVER", | |
38 "Sascha Sommer <saschasommer@freenet.de>", | |
39 TYPE_OUTPUT, | |
40 { 0, 0, 0, 0 }, | |
10957
4d4d0c1c7142
according to xfree cvs maximum overlay size is only 2046x2046
atmos4
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41 2046, |
4d4d0c1c7142
according to xfree cvs maximum overlay size is only 2046x2046
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42 2046, |
10954 | 43 4, |
44 4, | |
45 -1, | |
46 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
47 VENDOR_NVIDIA2, | |
48 -1, | |
49 { 0, 0, 0, 0 } | |
50 }; | |
51 | |
52 | |
53 unsigned int vixGetVersion(void){ | |
54 return(VIDIX_VERSION); | |
55 } | |
56 | |
57 | |
58 #define NV_ARCH_03 0x03 | |
59 #define NV_ARCH_04 0x04 | |
60 #define NV_ARCH_10 0x10 | |
61 #define NV_ARCH_20 0x20 | |
62 #define NV_ARCH_30 0x30 | |
63 | |
64 struct nvidia_cards { | |
65 unsigned short chip_id; | |
66 unsigned short arch; | |
67 }; | |
68 | |
69 | |
70 static struct nvidia_cards nvidia_card_ids[] = { | |
11073 | 71 /*NV03*/ |
10954 | 72 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, |
11073 | 73 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, |
74 /*NV04*/ | |
75 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
76 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, | |
77 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
78 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
79 {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04}, | |
80 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, | |
10954 | 81 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, |
11073 | 82 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, |
83 {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04}, | |
84 {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04}, | |
10954 | 85 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, |
11073 | 86 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, |
87 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
10954 | 88 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, |
89 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
11073 | 90 /*NV10*/ |
91 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, | |
92 {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10}, | |
93 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, | |
94 {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10}, | |
95 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, | |
96 {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10}, | |
97 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10}, | |
98 {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10}, | |
99 {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10}, | |
100 {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10}, | |
101 {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10}, | |
102 {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10}, | |
103 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, | |
104 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, | |
105 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, | |
106 {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, | |
107 {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10}, | |
108 {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10}, | |
109 /*NV20*/ | |
110 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
111 {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20}, | |
112 {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20}, | |
113 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20}, | |
114 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20}, | |
115 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20}, | |
10954 | 116 }; |
117 | |
118 | |
119 static int find_chip(unsigned chip_id){ | |
120 unsigned i; | |
121 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
122 { | |
123 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
124 } | |
125 return -1; | |
126 } | |
127 | |
128 int vixProbe(int verbose, int force){ | |
129 pciinfo_t lst[MAX_PCI_DEVICES]; | |
130 unsigned i,num_pci; | |
131 int err; | |
132 | |
133 if (force) | |
134 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
135 err = pci_scan(lst,&num_pci); | |
136 if(err){ | |
137 printf("[nvidia_vid] Error occured during pci scan: %s\n",strerror(err)); | |
138 return err; | |
139 } | |
140 else { | |
141 err = ENXIO; | |
142 for(i=0; i < num_pci; i++){ | |
143 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
144 int idx; | |
145 const char *dname; | |
146 idx = find_chip(lst[i].device); | |
147 if(idx == -1) | |
148 continue; | |
149 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
150 dname = dname ? dname : "Unknown chip"; | |
151 printf("[nvidia_vid] Found chip: %s\n", dname); | |
152 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
153 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
154 continue; | |
155 } | |
156 nvidia_cap.device_id = lst[i].device; | |
157 err = 0; | |
158 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
159 break; | |
160 } | |
161 } | |
162 } | |
163 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
164 return err; | |
165 } | |
166 | |
167 | |
168 | |
169 | |
170 /* | |
171 * PCI-Memory IO access macros. | |
172 */ | |
173 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
174 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
175 | |
176 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
177 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
178 | |
179 #ifndef USE_RMW_CYCLES | |
180 /* | |
181 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
182 */ | |
183 | |
184 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
185 | |
186 #undef VID_WR08 | |
187 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
188 #undef VID_RD08 | |
189 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
190 | |
191 #undef VID_WR32 | |
192 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
193 #undef VID_RD32 | |
194 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
195 #endif /* USE_RMW_CYCLES */ | |
196 | |
197 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
198 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
199 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
200 | |
201 | |
202 | |
203 | |
204 | |
205 | |
206 struct rivatv_chip { | |
207 volatile uint32_t *PMC; /* general control */ | |
208 volatile uint32_t *PME; /* multimedia port */ | |
209 volatile uint32_t *PFB; /* framebuffer control */ | |
210 volatile uint32_t *PVIDEO; /* overlay control */ | |
211 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
212 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
213 volatile uint32_t *PRAMIN; /* instance memory */ | |
214 volatile uint32_t *PRAMHT; /* hash table */ | |
215 volatile uint32_t *PRAMFC; /* fifo context table */ | |
216 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
217 volatile uint32_t *PFIFO; /* fifo control region */ | |
218 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
219 volatile uint32_t *PGRAPH; /* graphics engine */ | |
220 | |
221 unsigned long fbsize; /* framebuffer size */ | |
222 int arch; /* compatible NV_ARCH_XX define */ | |
223 int realarch; /* real architecture */ | |
224 void (* lock) (struct rivatv_chip *, int); | |
225 }; | |
226 typedef struct rivatv_chip rivatv_chip; | |
227 | |
228 | |
229 struct rivatv_info { | |
230 unsigned int colorkey; /* saved xv colorkey*/ | |
231 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
232 unsigned int depth; | |
233 unsigned int format; | |
234 unsigned int pitch; | |
235 unsigned int width,height; | |
236 unsigned int d_width,d_height; /*scaled width && height*/ | |
237 unsigned int wx,wy; /*window x && y*/ | |
238 unsigned int screen_x; /*screen width*/ | |
239 unsigned long buffer_size; /* size of the image buffer */ | |
240 struct rivatv_chip chip; /* NV architecture structure */ | |
241 void* video_base; /* virtual address of control region */ | |
242 void* control_base; /* virtual address of fb region */ | |
243 unsigned long picture_base; /* direct pointer to video picture */ | |
244 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
245 // struct rivatv_dma dma; /* DMA structure */ | |
246 unsigned int next_frame; | |
247 unsigned int num_frames; /* number of buffers */ | |
248 }; | |
249 typedef struct rivatv_info rivatv_info; | |
250 | |
251 //framebuffer size funcs | |
252 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
253 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
254 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
255 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
256 /* SDRAM 128 ZX. */ | |
257 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
258 } | |
259 else { | |
260 return 1024 * 1024 * 8; | |
261 } | |
262 } | |
263 else { | |
264 /* SGRAM 128. */ | |
265 switch (chip->PFB[0x00000000] & 0x00000003) { | |
266 case 0: | |
267 return 1024 * 1024 * 8; | |
268 break; | |
269 case 2: | |
270 return 1024 * 1024 * 4; | |
271 break; | |
272 default: | |
273 return 1024 * 1024 * 2; | |
274 break; | |
275 } | |
276 } | |
277 } | |
278 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
279 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
280 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
281 + 1024 * 1024 * 2; | |
282 } else { | |
283 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
284 case 0: | |
285 return 1024 * 1024 * 32; | |
286 break; | |
287 case 1: | |
288 return 1024 * 1024 * 4; | |
289 break; | |
290 case 2: | |
291 return 1024 * 1024 * 8; | |
292 break; | |
293 case 3: | |
294 default: | |
295 return 1024 * 1024 * 16; | |
296 break; | |
297 } | |
298 } | |
299 } | |
300 | |
301 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
302 return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 1024; | |
303 } | |
304 | |
305 //lock funcs | |
306 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
307 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
308 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
309 } | |
310 | |
311 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
312 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
313 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
314 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
315 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
316 } | |
317 | |
318 | |
319 | |
320 | |
321 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
322 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
323 uint32_t reg; | |
324 | |
325 /* switch off interrupts once for a while */ | |
326 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
327 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
328 | |
329 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
330 | |
331 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
332 | |
333 if ((reg & 0x10100010) != 0x10100010) { | |
334 printf("PVIDEO and PFB disabled, enabling...\n"); | |
335 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
336 } | |
337 | |
338 /* save the current colorkey */ | |
339 switch (info->chip.arch ) { | |
340 case NV_ARCH_10: | |
341 case NV_ARCH_20: | |
342 case NV_ARCH_30: | |
343 /* NV_PVIDEO_COLOR_KEY */ | |
344 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
345 break; | |
346 case NV_ARCH_03: | |
347 case NV_ARCH_04: | |
348 /* NV_PVIDEO_KEY */ | |
349 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
350 break; | |
351 } | |
352 | |
353 | |
354 /* re-enable interrupts again */ | |
355 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
356 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
357 } | |
358 | |
359 /* Stop overlay video. */ | |
360 void rivatv_overlay_stop (struct rivatv_info *info) { | |
361 switch (info->chip.arch ) { | |
362 case NV_ARCH_10: | |
363 case NV_ARCH_20: | |
364 case NV_ARCH_30: | |
365 /* NV_PVIDEO_COLOR_KEY */ | |
366 /* Xv-Extension-Hack: Restore previously saved value. */ | |
367 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
368 /* NV_PVIDEO_STOP */ | |
369 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
370 /* NV_PVIDEO_BUFFER */ | |
371 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
372 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
373 VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); | |
374 break; | |
375 case NV_ARCH_03: | |
376 case NV_ARCH_04: | |
377 /* NV_PVIDEO_KEY */ | |
378 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
379 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
380 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
381 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
382 VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); | |
383 /* NV_PVIDEO_OE_STATE */ | |
384 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
385 /* NV_PVIDEO_SU_STATE */ | |
386 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
387 /* NV_PVIDEO_RM_STATE */ | |
388 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
389 break; | |
390 } | |
391 } | |
392 | |
393 /* Get pan offset of the physical screen. */ | |
394 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
395 uint32_t pan; | |
396 info->chip.lock (&info->chip, 0); | |
397 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
398 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
399 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
400 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
401 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
402 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
403 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
404 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
405 return pan << 2; | |
406 } | |
407 | |
408 /* Compute and set colorkey depending on the colour depth. */ | |
409 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
410 uint32_t r, g, b, key = 0; | |
411 r = (chromakey & 0x00FF0000) >> 16; | |
412 g = (chromakey & 0x0000FF00) >> 8; | |
413 b = chromakey & 0x000000FF; | |
414 switch (info->depth) { | |
415 case 15: | |
416 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); | |
417 break; | |
418 case 16: | |
419 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); | |
420 break; | |
421 case 24: | |
422 key = chromakey & 0x00FFFFFF; | |
423 break; | |
424 case 32: | |
425 key = chromakey; | |
426 break; | |
427 default: | |
428 /* THINKME: Possible to pass a colour index for 8 bpp ? */ | |
429 printf ("invalid color depth: %d bpp\n", info->depth); | |
430 break; | |
431 } | |
432 switch (info->chip.arch) { | |
433 case NV_ARCH_10: | |
434 case NV_ARCH_20: | |
435 case NV_ARCH_30: | |
436 VID_WR32 (info->chip.PVIDEO, 0xB00, key); | |
437 break; | |
438 case NV_ARCH_03: | |
439 case NV_ARCH_04: | |
440 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
441 break; | |
442 } | |
443 } | |
444 | |
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445 static void nv_waitidle(struct rivatv_info *info ){ |
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446 while (info->chip.PGRAPH[0x1C0] & 1) {} |
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447 } |
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448 |
10954 | 449 |
450 /* Start overlay video. */ | |
451 void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
452 uint32_t base, size, offset, xscale, yscale, pan,bpp, pitch0=0; | |
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453 int x=8, y=8; |
10954 | 454 int lwidth=info->d_width, lheight=info->d_height; |
455 int bps; | |
456 | |
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457 size = info->buffer_size; |
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458 base = info->picture_offset; |
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459 offset = bufno*size; |
10954 | 460 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ |
461 info->chip.lock (&info->chip, 0); | |
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462 nv_waitidle(info); |
10954 | 463 switch (info->chip.arch) { |
464 case NV_ARCH_03: | |
465 pitch0 = info->chip.PGRAPH[0x00000650/4]; | |
466 break; | |
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467 case NV_ARCH_04: |
10954 | 468 case NV_ARCH_10: |
469 case NV_ARCH_20: | |
470 case NV_ARCH_30: | |
471 pitch0 = info->chip.PGRAPH[0x00000670/4]; | |
472 break; | |
473 } | |
474 VID_WR08(info->chip.PCIO, 0x03D4, 0x28); | |
475 bpp = VID_RD08(info->chip.PCIO,0x03D5); | |
476 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? | |
477 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16 | |
478 else info->depth = bpp*8; | |
479 if(!bpp)printf("[nvidia_vid] error invalid bpp\n"); | |
480 else | |
481 { | |
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482 // printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); |
10954 | 483 info->screen_x = pitch0/bpp; |
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484 bps = info->screen_x * ((info->depth+1)/8); |
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485 /* get pan offset of the physical screen */ |
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486 pan = rivatv_overlay_pan (info); |
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487 /* adjust window position depending on the pan offset */ |
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488 x = info->wx - (pan % bps) * 8 / info->depth; |
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489 y = info->wy - (pan / bps); |
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490 /* adjust negative output window variables */ |
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491 if (x < 0) { |
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492 lwidth = info->d_width + x; |
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493 offset += (-x * info->width / info->d_width) << 1; |
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494 // offset += (-window->x * port->vld_width / window->width) << 1; |
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495 x = 0; |
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496 } |
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497 if (y < 0) { |
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498 lheight = info->d_height + y; |
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499 offset += (-y * info->height / info->d_height * info->width) << 1; |
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500 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; |
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501 y = 0; |
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502 } |
10954 | 503 |
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504 |
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505 |
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506 |
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507 |
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508 |
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509 } |
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510 |
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511 |
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512 |
10954 | 513 |
514 switch (info->chip.arch) { | |
515 case NV_ARCH_10: | |
516 case NV_ARCH_20: | |
517 case NV_ARCH_30: | |
518 | |
519 /* NV_PVIDEO_BASE */ | |
520 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base); | |
521 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); | |
522 /* NV_PVIDEO_LIMIT */ | |
523 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + size - 1); | |
524 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); | |
525 | |
526 /* extra code for NV20 && NV30 architectures */ | |
527 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { | |
528 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base); | |
529 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); | |
530 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + size - 1); | |
531 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); | |
532 } | |
533 | |
534 /* NV_PVIDEO_LUMINANCE */ | |
535 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000); | |
536 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
537 /* NV_PVIDEO_CHROMINANCE */ | |
538 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000); | |
539 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
540 | |
541 /* NV_PVIDEO_OFFSET */ | |
542 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, offset + 0); | |
543 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); | |
544 /* NV_PVIDEO_SIZE_IN */ | |
545 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
546 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
547 /* NV_PVIDEO_POINT_IN */ | |
548 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
549 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
550 /* NV_PVIDEO_DS_DX_RATIO */ | |
551 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
552 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
553 /* NV_PVIDEO_DT_DY_RATIO */ | |
554 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
555 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
556 | |
557 /* NV_PVIDEO_POINT_OUT */ | |
558 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
559 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
560 /* NV_PVIDEO_SIZE_OUT */ | |
561 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
562 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
563 | |
564 /* NV_PVIDEO_FORMAT */ | |
565 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, (info->pitch << 0) | 0x00100000|(((info->format==IMGFMT_YV12)?1:0))<<16); | |
566 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
567 | |
568 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
569 VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); | |
570 /* NV_PVIDEO_STOP */ | |
571 VID_AND32 (info->chip.PVIDEO, 0x704, 0xFFFFFFEE); | |
572 /* NV_PVIDEO_BUFFER */ | |
573 VID_OR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); | |
574 break; | |
575 | |
576 case NV_ARCH_03: | |
577 case NV_ARCH_04: | |
578 | |
579 | |
580 /* NV_PVIDEO_OE_STATE */ | |
581 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
582 /* NV_PVIDEO_SU_STATE */ | |
583 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
584 /* NV_PVIDEO_RM_STATE */ | |
585 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
586 | |
587 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
588 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
589 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
590 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
591 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
592 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
593 | |
594 /* NV_PVIDEO_WINDOW_START */ | |
595 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
596 /* NV_PVIDEO_WINDOW_SIZE */ | |
597 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
598 /* NV_PVIDEO_STEP_SIZE */ | |
599 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
600 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
601 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
602 | |
603 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
604 VID_WR32 (info->chip.PVIDEO, 0x280, 0x69); | |
605 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
606 VID_WR32 (info->chip.PVIDEO, 0x284, 0x3e); | |
607 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
608 VID_WR32 (info->chip.PVIDEO, 0x288, 0x89); | |
609 /* NV_PVIDEO_CSC_ADJUST */ | |
610 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
611 | |
612 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
613 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
614 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
615 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*rivatv 0x110 */ | |
616 | |
617 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
618 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
619 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
620 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
621 | |
622 /* NV_PVIDEO_BUFF0_OFFSET */ | |
623 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
624 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
625 | |
626 | |
627 | |
628 | |
629 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
630 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
631 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ | |
632 | |
633 VID_WR32 (info->chip.PVIDEO, 0x244, (info->format==IMGFMT_YUY2)?0x111:0x011); | |
634 /* NV_PVIDEO_SU_STATE */ | |
635 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
636 break; | |
637 } | |
638 /*set colorkey*/ | |
639 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
640 | |
641 } | |
642 | |
643 | |
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644 |
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645 |
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646 |
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647 |
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648 |
10954 | 649 static rivatv_info* info; |
650 | |
651 | |
652 | |
653 | |
654 int vixInit(void){ | |
655 int mtrr; | |
656 info = (rivatv_info*)calloc(1,sizeof(rivatv_info)); | |
657 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
658 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
659 printf("[nvidia_vid] arch %x register base %x\n",info->chip.arch,(unsigned int)info->control_base); | |
660 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
661 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
662 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
663 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
664 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
665 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
666 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
667 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
668 /* setup chip specific functions */ | |
669 switch (info->chip.arch) { | |
670 case NV_ARCH_03: | |
671 info->chip.lock = rivatv_lock_nv03; | |
672 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
673 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
674 break; | |
675 case NV_ARCH_04: | |
676 info->chip.lock = rivatv_lock_nv04; | |
677 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
678 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
679 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
680 break; | |
681 case NV_ARCH_10: | |
682 case NV_ARCH_20: | |
683 case NV_ARCH_30: | |
684 info->chip.lock = rivatv_lock_nv04; | |
685 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
686 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
687 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
688 break; | |
689 } | |
690 switch (info->chip.arch) { | |
691 case NV_ARCH_03: | |
692 { | |
693 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
694 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
695 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
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696 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); |
10954 | 697 info->picture_base = (uint32_t) info->video_base + info->picture_offset; |
698 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
699 break; | |
700 } | |
701 case NV_ARCH_04: | |
702 case NV_ARCH_10: | |
703 case NV_ARCH_20: | |
704 case NV_ARCH_30: | |
705 { | |
706 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
707 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
708 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
709 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
710 break; | |
711 } | |
712 } | |
713 | |
714 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
715 | |
716 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
717 printf("[nvidia_vid]: unable to setup MTRR: %s\n", strerror(mtrr)); | |
718 else | |
719 printf("[nvidia_vid]: MTRR set up\n"); | |
720 | |
721 /*get some info about the screen dimension and depth*/ | |
722 { | |
723 uint32_t bpp=0,pitch0=0; | |
724 info->chip.lock (&info->chip, 0); | |
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725 nv_waitidle(info); |
10954 | 726 switch (info->chip.arch) { |
727 case NV_ARCH_03: | |
728 pitch0 = info->chip.PGRAPH[0x00000650/4]; | |
729 break; | |
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730 case NV_ARCH_04: |
10954 | 731 case NV_ARCH_10: |
732 case NV_ARCH_20: | |
733 case NV_ARCH_30: | |
734 pitch0 = info->chip.PGRAPH[0x00000670/4]; | |
735 break; | |
736 } | |
737 VID_WR08(info->chip.PCIO, 0x03D4, 0x28); | |
738 bpp = VID_RD08(info->chip.PCIO,0x03D5); | |
739 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? | |
740 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16 | |
741 else info->depth = bpp*8; | |
742 if(!bpp)printf("[nvidia_vid] error invalid bpp\n"); | |
743 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); | |
744 } | |
745 | |
746 rivatv_enable_PMEDIA(info); | |
747 info->next_frame = 0; | |
748 return 0; | |
749 } | |
750 | |
751 void vixDestroy(void){ | |
752 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); | |
753 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
754 free(info); | |
755 } | |
756 | |
757 int vixGetCapability(vidix_capability_t *to){ | |
758 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); | |
759 return 0; | |
760 } | |
761 | |
762 inline static int is_supported_fourcc(uint32_t fourcc) | |
763 { | |
764 if (fourcc == IMGFMT_UYVY || | |
765 (fourcc == IMGFMT_YUY2 && info->chip.arch <= NV_ARCH_04) || | |
766 (fourcc == IMGFMT_YV12 && info->chip.arch >= NV_ARCH_10)) | |
767 return 1; | |
768 else | |
769 return 0; | |
770 } | |
771 | |
772 int vixQueryFourcc(vidix_fourcc_t *to){ | |
773 if(is_supported_fourcc(to->fourcc)){ | |
774 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
775 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
776 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
777 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
778 VID_DEPTH_32BPP; | |
779 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
780 return 0; | |
781 } | |
782 else to->depth = to->flags = 0; | |
783 return ENOSYS; | |
784 } | |
785 | |
786 int vixConfigPlayback(vidix_playback_t *vinfo){ | |
787 uint32_t i; | |
788 printf("called %s\n", __FUNCTION__); | |
789 if (! is_supported_fourcc(vinfo->fourcc)) | |
790 return ENOSYS; | |
791 | |
792 info->width = vinfo->src.w; | |
793 info->height = vinfo->src.h; | |
794 | |
795 info->d_width = vinfo->dest.w; | |
796 info->d_height = vinfo->dest.h; | |
797 info->wx = vinfo->dest.x; | |
798 info->wy = vinfo->dest.y; | |
799 info->format = vinfo->fourcc; | |
800 | |
801 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
802 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
803 | |
804 | |
805 vinfo->dga_addr=(void*)(info->picture_base); | |
806 | |
807 switch (vinfo->fourcc) | |
808 { | |
809 case IMGFMT_YUY2: | |
810 case IMGFMT_UYVY: | |
811 | |
812 vinfo->dest.pitch.y = 2; | |
813 vinfo->dest.pitch.u = 0; | |
814 vinfo->dest.pitch.v = 0; | |
815 | |
816 vinfo->offset.y = 0; | |
817 vinfo->offset.v = 0; | |
818 vinfo->offset.u = 0; | |
819 | |
820 info->pitch = info->width << 1; | |
821 vinfo->frame_size = info->pitch * info->height; | |
822 break; | |
823 case IMGFMT_YV12: | |
824 vinfo->dest.pitch.y = 1; | |
825 vinfo->dest.pitch.u = 1; | |
826 vinfo->dest.pitch.v = 1; | |
827 | |
828 vinfo->offset.y = 0; | |
829 vinfo->offset.v = (info->width) * info->height; | |
830 vinfo->offset.u = vinfo->offset.v * 5 / 4; | |
831 | |
832 info->pitch = info->width + (info->width >> 1); | |
833 vinfo->frame_size = info->pitch * info->height; | |
834 break; | |
835 } | |
836 info->buffer_size = vinfo->frame_size; | |
837 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
838 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
839 // vinfo->num_frames = 1; | |
840 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
841 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
842 return 0; | |
843 } | |
844 | |
845 int vixPlaybackOn(void){ | |
846 rivatv_overlay_start(info,info->next_frame); | |
847 return 0; | |
848 } | |
849 | |
850 int vixPlaybackOff(void){ | |
851 rivatv_overlay_stop(info); | |
852 return 0; | |
853 } | |
854 | |
855 int vixSetGrKeys( const vidix_grkey_t * grkey){ | |
856 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
857 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
858 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
859 return 0; | |
860 } | |
861 | |
862 int vixPlaybackFrameSelect(unsigned int frame){ | |
863 // printf("selecting buffer %d\n", frame); | |
864 rivatv_overlay_start(info, frame); | |
865 if (info->num_frames >= 1) | |
866 info->next_frame = (frame+1)%info->num_frames; | |
867 return 0; | |
868 } |