Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3096:15abd9121737
ao_plugin.c and plugin headers added
author | anders |
---|---|
date | Sat, 24 Nov 2001 05:24:06 +0000 |
parents | 7eba9b3ac5a7 |
children | 60c2510ab0ae |
rev | line source |
---|---|
2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3066 | 7 * BES YUV video overlay driver for Radeon cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
2870 | 15 */ |
16 | |
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Direct YV12 support!!! But only in black and white mode :(
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17 #define RADEON_VID_VERSION "0.9.9.1" |
2951 | 18 |
2870 | 19 /* |
20 It's entirely possible this major conflicts with something else | |
21 mknod /dev/radeon_vid c 178 0 | |
22 */ | |
23 | |
24 /* | |
25 TODO: | |
26 OV0_COLOUR_CNTL brightness saturation | |
27 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? | |
28 OV0_GRAPHICS_KEY_CLR color key | |
29 OV0_AUTO_FLIP_CNTL | |
30 OV0_FILTER_CNTL | |
31 OV0_VIDEO_KEY_CLR | |
32 OV0_KEY_CNTL | |
33 | |
34 BPP should be known | |
35 */ | |
36 | |
37 #include <linux/config.h> | |
38 #include <linux/version.h> | |
39 #include <linux/module.h> | |
40 #include <linux/types.h> | |
41 #include <linux/kernel.h> | |
42 #include <linux/sched.h> | |
43 #include <linux/mm.h> | |
44 #include <linux/string.h> | |
45 #include <linux/errno.h> | |
46 #include <linux/slab.h> | |
47 #include <linux/pci.h> | |
48 #include <linux/ioport.h> | |
49 #include <linux/init.h> | |
50 | |
51 #include "radeon_vid.h" | |
52 #include "radeon.h" | |
53 | |
54 #ifdef CONFIG_MTRR | |
55 #include <asm/mtrr.h> | |
56 #endif | |
57 | |
58 #include <asm/uaccess.h> | |
59 #include <asm/system.h> | |
60 #include <asm/io.h> | |
61 | |
62 #define TRUE 1 | |
63 #define FALSE 0 | |
64 | |
65 #define RADEON_VID_MAJOR 178 | |
66 | |
67 | |
68 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
2951 | 69 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); |
2965 | 70 #ifdef MODULE_LICENSE |
2870 | 71 MODULE_LICENSE("GPL"); |
2965 | 72 #endif |
2870 | 73 |
74 typedef struct bes_registers_s | |
75 { | |
76 /* base address of yuv framebuffer */ | |
77 uint32_t yuv_base; | |
78 uint32_t fourcc; | |
79 /* YUV BES registers */ | |
80 uint32_t reg_load_cntl; | |
81 uint32_t h_inc; | |
82 uint32_t step_by; | |
83 uint32_t y_x_start; | |
84 uint32_t y_x_end; | |
85 uint32_t v_inc; | |
86 uint32_t p1_blank_lines_at_top; | |
3019 | 87 uint32_t p23_blank_lines_at_top; |
2870 | 88 uint32_t vid_buf_pitch0_value; |
2944 | 89 uint32_t vid_buf_pitch1_value; |
2870 | 90 uint32_t p1_x_start_end; |
91 uint32_t p2_x_start_end; | |
92 uint32_t p3_x_start_end; | |
93 uint32_t vid_buf0_base_adrs; | |
94 /* These ones are for auto flip: maybe in the future */ | |
95 uint32_t vid_buf1_base_adrs; | |
96 uint32_t vid_buf2_base_adrs; | |
97 uint32_t vid_buf3_base_adrs; | |
98 uint32_t vid_buf4_base_adrs; | |
99 uint32_t vid_buf5_base_adrs; | |
100 | |
101 uint32_t p1_v_accum_init; | |
102 uint32_t p1_h_accum_init; | |
3019 | 103 uint32_t p23_v_accum_init; |
2870 | 104 uint32_t p23_h_accum_init; |
105 uint32_t scale_cntl; | |
106 uint32_t exclusive_horz; | |
107 uint32_t auto_flip_cntl; | |
108 uint32_t filter_cntl; | |
109 uint32_t colour_cntl; | |
110 uint32_t graphics_key_msk; | |
111 uint32_t graphics_key_clr; | |
112 uint32_t key_cntl; | |
113 uint32_t test; | |
114 } bes_registers_t; | |
115 | |
116 typedef struct video_registers_s | |
117 { | |
118 uint32_t name; | |
119 uint32_t value; | |
120 }video_registers_t; | |
121 | |
122 static bes_registers_t besr; | |
123 static video_registers_t vregs[] = | |
124 { | |
125 { OV0_REG_LOAD_CNTL, 0 }, | |
126 { OV0_H_INC, 0 }, | |
127 { OV0_STEP_BY, 0 }, | |
128 { OV0_Y_X_START, 0 }, | |
129 { OV0_Y_X_END, 0 }, | |
130 { OV0_V_INC, 0 }, | |
131 { OV0_P1_BLANK_LINES_AT_TOP, 0 }, | |
3019 | 132 { OV0_P23_BLANK_LINES_AT_TOP, 0 }, |
2870 | 133 { OV0_VID_BUF_PITCH0_VALUE, 0 }, |
2944 | 134 { OV0_VID_BUF_PITCH1_VALUE, 0 }, |
2870 | 135 { OV0_P1_X_START_END, 0 }, |
136 { OV0_P2_X_START_END, 0 }, | |
137 { OV0_P3_X_START_END, 0 }, | |
138 { OV0_VID_BUF0_BASE_ADRS, 0 }, | |
139 { OV0_VID_BUF1_BASE_ADRS, 0 }, | |
140 { OV0_VID_BUF2_BASE_ADRS, 0 }, | |
141 { OV0_VID_BUF3_BASE_ADRS, 0 }, | |
142 { OV0_VID_BUF4_BASE_ADRS, 0 }, | |
143 { OV0_VID_BUF5_BASE_ADRS, 0 }, | |
144 { OV0_P1_V_ACCUM_INIT, 0 }, | |
145 { OV0_P1_H_ACCUM_INIT, 0 }, | |
3019 | 146 { OV0_P23_V_ACCUM_INIT, 0 }, |
2870 | 147 { OV0_P23_H_ACCUM_INIT, 0 }, |
148 { OV0_SCALE_CNTL, 0 }, | |
149 { OV0_EXCLUSIVE_HORZ, 0 }, | |
150 { OV0_AUTO_FLIP_CNTL, 0 }, | |
151 { OV0_FILTER_CNTL, 0 }, | |
152 { OV0_COLOUR_CNTL, 0 }, | |
153 { OV0_GRAPHICS_KEY_MSK, 0 }, | |
154 { OV0_GRAPHICS_KEY_CLR, 0 }, | |
155 { OV0_KEY_CNTL, 0 }, | |
156 { OV0_TEST, 0 } | |
157 }; | |
158 | |
159 static uint32_t radeon_vid_in_use = 0; | |
160 | |
161 static uint8_t *radeon_mmio_base = 0; | |
162 static uint32_t radeon_mem_base = 0; | |
3019 | 163 static int32_t radeon_overlay_off = 0; |
2870 | 164 |
165 static uint32_t radeon_ram_size = 0; | |
166 | |
167 //static struct video_window radeon_win; | |
168 static mga_vid_config_t radeon_config; | |
169 | |
2951 | 170 #undef DEBUG |
2870 | 171 #if DEBUG |
172 #define RTRACE printk | |
173 #else | |
174 #define RTRACE(...) ((void)0) | |
175 #endif | |
176 | |
177 | |
178 /* | |
179 * IO macros | |
180 */ | |
181 | |
182 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
183 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
184 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
185 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
186 | |
187 static void radeon_vid_save_state( void ) | |
188 { | |
189 size_t i; | |
190 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
191 vregs[i].value = INREG(vregs[i].name); | |
192 } | |
193 | |
194 static void radeon_vid_restore_state( void ) | |
195 { | |
196 size_t i; | |
197 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
198 OUTREG(vregs[i].name,vregs[i].value); | |
199 } | |
200 | |
201 static void radeon_vid_stop_video( void ) | |
202 { | |
203 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
204 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
205 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
206 OUTREG(OV0_FILTER_CNTL, 0x0000000f); | |
207 /* | |
208 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
209 (saturation << 8) | | |
210 (saturation << 16)); | |
211 OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1); | |
212 OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey); | |
213 */ | |
214 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
215 OUTREG(OV0_TEST, 0); | |
216 } | |
217 | |
218 static void radeon_vid_display_video( void ) | |
219 { | |
220 int bes_flags; | |
2925 | 221 RTRACE("radeon_vid: OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
2951 | 222 RTRACE("radeon_vid: OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs); |
2925 | 223 RTRACE("radeon_vid: OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" |
224 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); | |
2951 | 225 RTRACE("radeon_vid: OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n" |
226 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end); | |
227 RTRACE("radeon_vid: OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n" | |
228 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init); | |
2870 | 229 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
230 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
2965 | 231 |
2870 | 232 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
233 | |
2917 | 234 OUTREG(OV0_DEINTERLACE_PATTERN,0xAAAAAAAA); |
2870 | 235 |
236 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
237 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2965 | 238 |
2870 | 239 OUTREG(OV0_H_INC, besr.h_inc); |
240 OUTREG(OV0_STEP_BY, besr.step_by); | |
241 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
242 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
243 OUTREG(OV0_V_INC, besr.v_inc); | |
244 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
245 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
2944 | 246 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 247 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
248 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
249 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
250 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); | |
251 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
252 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
253 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
254 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
255 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
256 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
257 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
258 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
259 | |
260 bes_flags = SCALER_ENABLE | | |
261 SCALER_DOUBLE_BUFFER | | |
2965 | 262 SCALER_ADAPTIVE_DEINT | |
2870 | 263 SCALER_SMART_SWITCH | |
264 SCALER_HORZ_PICK_NEAREST; | |
265 switch(besr.fourcc) | |
266 { | |
267 case IMGFMT_RGB15: | |
268 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
269 case IMGFMT_RGB16: | |
270 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
271 case IMGFMT_RGB24: | |
272 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
273 case IMGFMT_RGB32: | |
274 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
275 | |
2925 | 276 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
2870 | 277 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
278 case IMGFMT_IYUV: bes_flags |= SCALER_SOURCE_YUV12; break; | |
279 | |
280 case IMGFMT_I420: | |
3019 | 281 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12 | |
282 SCALER_PIX_EXPAND | | |
283 SCALER_Y2R_TEMP; | |
284 break; | |
2870 | 285 case IMGFMT_YUY2: |
286 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
287 } | |
2951 | 288 RTRACE("radeon_vid: OV0: SCALER=%x\n",bes_flags); |
2870 | 289 OUTREG(OV0_SCALE_CNTL, bes_flags); |
290 /* | |
291 TODO: | |
292 brightness: -64 : +63 | |
293 saturation: 0 : 31 | |
294 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
295 (saturation << 8) | | |
296 (saturation << 16)); | |
297 OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16); | |
298 | |
299 */ | |
300 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
301 } | |
302 | |
303 static void radeon_vid_start_video( void ) | |
304 { | |
2925 | 305 radeon_vid_display_video(); |
2870 | 306 } |
307 | |
2951 | 308 #define XXX_SRC_X 0 |
309 #define XXX_SRC_Y 0 | |
2870 | 310 |
2944 | 311 #define XXX_WIDTH config->src_width |
312 #define XXX_HEIGHT config->src_height | |
2870 | 313 |
2951 | 314 #define XXX_DRW_W config->dest_width |
315 #define XXX_DRW_H config->dest_height | |
2925 | 316 |
2870 | 317 static int radeon_vid_init_video( mga_vid_config_t *config ) |
318 { | |
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319 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 320 int is_420; |
2951 | 321 RTRACE("radeon_vid: usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 322 ,(uint32_t)config->version |
2951 | 323 ,(uint32_t)config->format |
2870 | 324 ,(uint32_t)config->card_type |
325 ,(uint32_t)config->ram_size | |
326 ,(uint32_t)config->src_width | |
327 ,(uint32_t)config->src_height | |
328 ,(uint32_t)config->x_org | |
329 ,(uint32_t)config->y_org | |
330 ,(uint32_t)config->dest_width | |
331 ,(uint32_t)config->dest_height | |
332 ,(uint32_t)config->frame_size | |
333 ,(uint32_t)config->num_frames); | |
2917 | 334 radeon_vid_stop_video(); |
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335 left = XXX_SRC_X << 16; |
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336 top = XXX_SRC_Y << 16; |
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337 src_h = config->src_height; |
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338 src_w = config->src_width; |
2870 | 339 switch(config->format) |
340 { | |
341 case IMGFMT_RGB15: | |
342 case IMGFMT_BGR15: | |
343 case IMGFMT_RGB16: | |
344 case IMGFMT_BGR16: | |
345 case IMGFMT_RGB24: | |
346 case IMGFMT_BGR24: | |
347 case IMGFMT_RGB32: | |
348 case IMGFMT_BGR32: | |
349 | |
350 case IMGFMT_YVU9: | |
351 case IMGFMT_IYUV: | |
352 case IMGFMT_UYVY: | |
353 | |
354 case IMGFMT_YV12: | |
355 case IMGFMT_I420: | |
356 case IMGFMT_YUY2: | |
357 break; | |
358 default: | |
359 printk( "radeon_vid: Unsupported pixel format: 0x%X\n",config->format); | |
360 return -1; | |
361 } | |
3019 | 362 is_420 = 0; |
363 if(config->format == IMGFMT_YV12 || config->format == IMGFMT_I420) is_420 = 1; | |
2951 | 364 switch(config->format) |
365 { | |
366 default: | |
367 case IMGFMT_YVU9: | |
368 case IMGFMT_IYUV: | |
369 case IMGFMT_UYVY: | |
370 case IMGFMT_YV12: | |
371 case IMGFMT_I420: | |
372 case IMGFMT_YUY2: | |
373 case IMGFMT_RGB15: | |
374 case IMGFMT_BGR15: | |
375 case IMGFMT_RGB16: | |
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376 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 377 case IMGFMT_RGB24: |
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378 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 379 case IMGFMT_RGB32: |
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380 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 381 } |
382 | |
2870 | 383 besr.fourcc = config->format; |
384 | |
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385 besr.v_inc = (src_h << 20) / XXX_DRW_H; |
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386 h_inc = (src_w << 12) / XXX_DRW_W; |
2944 | 387 step_by = 1; |
2870 | 388 |
2944 | 389 while(h_inc >= (2 << 12)) { |
390 step_by++; | |
391 h_inc >>= 1; | |
2870 | 392 } |
393 | |
394 /* keep everything in 16.16 */ | |
395 | |
3019 | 396 if(is_420) |
397 { | |
398 uint32_t dstPitch,d1line,d2line,d3line; | |
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399 dstPitch = ((src_w + 15) & ~15); /* of luma */ |
3019 | 400 d1line = top * dstPitch; |
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401 d2line = (src_h * dstPitch) + ((top >> 1) * (dstPitch >> 1)); |
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402 d3line = d2line + ((src_h >> 1) * (dstPitch >> 1)); |
3066 | 403 besr.vid_buf0_base_adrs = ((radeon_overlay_off + d1line) & VIF_BUF0_BASE_ADRS_MASK) | VIF_BUF0_PITCH_SEL; |
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404 besr.vid_buf1_base_adrs = ((radeon_overlay_off + d2line) & VIF_BUF1_BASE_ADRS_MASK) | VIF_BUF1_PITCH_SEL; |
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405 besr.vid_buf2_base_adrs = ((radeon_overlay_off + d3line) & VIF_BUF2_BASE_ADRS_MASK) | VIF_BUF2_PITCH_SEL; |
3019 | 406 } |
407 else | |
408 { | |
409 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
410 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0; | |
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411 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 412 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
413 } | |
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414 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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415 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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416 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 417 |
2951 | 418 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 419 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 420 ((tmp << 12) & 0xf0000000); |
2870 | 421 |
2951 | 422 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 423 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 424 ((tmp << 12) & 0x70000000); |
2870 | 425 |
2951 | 426 tmp = (top & 0x0000ffff) + 0x00018000; |
2870 | 427 besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001; |
428 | |
3019 | 429 |
430 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
431 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & 0x01ff8000) | 0x00000001 : 0; | |
432 | |
3047
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433 leftUV = (left >> 17) & 15; |
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434 left = (left >> 16) & 15; |
2944 | 435 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
436 besr.step_by = step_by | (step_by << 8); | |
3020 | 437 besr.y_x_start = (config->x_org+8) | (config->y_org << 16); |
2925 | 438 besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16); |
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439 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
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440 src_h = (src_h + 1) >> 1; |
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441 besr.p23_blank_lines_at_top = is_420 ? P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16):0; |
2870 | 442 besr.vid_buf_pitch0_value = pitch; |
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443 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
2925 | 444 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
445 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); | |
2870 | 446 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" |
2925 | 447 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
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448 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
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449 src_w>>=1; |
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450 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); |
2870 | 451 besr.p3_x_start_end = besr.p2_x_start_end; |
452 return 0; | |
453 } | |
454 | |
455 static void radeon_vid_frame_sel(int frame) | |
456 { | |
3066 | 457 uint32_t off0,off1,off2; |
458 if(frame%2) | |
459 { | |
460 off0 = besr.vid_buf3_base_adrs; | |
461 off1 = besr.vid_buf4_base_adrs; | |
462 off2 = besr.vid_buf5_base_adrs; | |
463 } | |
464 else | |
465 { | |
466 off0 = besr.vid_buf0_base_adrs; | |
467 off1 = besr.vid_buf1_base_adrs; | |
468 off2 = besr.vid_buf2_base_adrs; | |
469 } | |
2917 | 470 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
471 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 472 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
473 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
474 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 475 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 476 } |
477 | |
2951 | 478 static int video_on = 0; |
479 | |
2870 | 480 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
481 { | |
482 int frame; | |
483 | |
484 switch(cmd) | |
485 { | |
486 case MGA_VID_CONFIG: | |
487 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base); | |
488 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base); | |
489 RTRACE( "radeon_vid: Received configuration\n"); | |
490 | |
491 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
492 { | |
493 printk( "radeon_vid: failed copy from userspace\n"); | |
3019 | 494 return -EFAULT; |
2870 | 495 } |
496 if(radeon_config.version != MGA_VID_VERSION){ | |
497 printk( "radeon_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); | |
3019 | 498 return -EFAULT; |
2870 | 499 } |
500 | |
501 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
502 printk( "radeon_vid: illegal frame_size: %d\n",radeon_config.frame_size); | |
3019 | 503 return -EFAULT; |
2870 | 504 } |
505 | |
506 if(radeon_config.num_frames<1 || radeon_config.num_frames>4){ | |
507 printk( "radeon_vid: illegal num_frames: %d\n",radeon_config.num_frames); | |
3019 | 508 return -EFAULT; |
2870 | 509 } |
510 | |
511 /* FIXME: Fake of G400 ;) or would be better G200 ??? */ | |
512 radeon_config.card_type = 0; | |
513 radeon_config.ram_size = radeon_ram_size; | |
3019 | 514 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
515 radeon_overlay_off &= 0xffff0000; | |
516 if(radeon_overlay_off < 0){ | |
517 printk("radeon_vid: not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); | |
518 return -EFAULT; | |
519 } | |
520 RTRACE("radeon_vid: using video overlay at offset %p\n",radeon_overlay_off); | |
2870 | 521 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
522 { | |
523 printk( "radeon_vid: failed copy to userspace\n"); | |
3019 | 524 return -EFAULT; |
2870 | 525 } |
526 return radeon_vid_init_video(&radeon_config); | |
527 break; | |
528 | |
529 case MGA_VID_ON: | |
530 RTRACE( "radeon_vid: Video ON (ioctl)\n"); | |
2925 | 531 radeon_vid_start_video(); |
2951 | 532 video_on = 1; |
2870 | 533 break; |
534 | |
535 case MGA_VID_OFF: | |
536 RTRACE( "radeon_vid: Video OFF (ioctl)\n"); | |
2951 | 537 if(video_on) radeon_vid_stop_video(); |
538 video_on = 0; | |
2870 | 539 break; |
540 | |
541 case MGA_VID_FSEL: | |
542 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
543 { | |
544 printk("radeon_vid: FSEL failed copy from userspace\n"); | |
545 return(-EFAULT); | |
546 } | |
547 radeon_vid_frame_sel(frame); | |
548 break; | |
549 | |
550 default: | |
551 printk( "radeon_vid: Invalid ioctl\n"); | |
552 return (-EINVAL); | |
553 } | |
554 | |
555 return 0; | |
556 } | |
557 | |
558 struct ati_card_id_s | |
559 { | |
560 int id; | |
561 char name[17]; | |
562 }ati_card_ids[]= | |
563 { | |
564 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, | |
565 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
566 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
567 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
568 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
569 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
570 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
571 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
572 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
573 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
574 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
575 }; | |
576 | |
577 static int radeon_vid_config_card(void) | |
578 { | |
579 struct pci_dev *dev = NULL; | |
580 size_t i; | |
581 | |
582 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
583 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
584 break; | |
585 if(dev) | |
586 printk("radeon_vid: Found %s\n",ati_card_ids[i].name); | |
587 else | |
588 { | |
589 printk("radeon_vid: No supported cards found\n"); | |
590 return FALSE; | |
591 } | |
592 | |
593 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
594 radeon_mem_base = dev->resource[0].start; | |
595 | |
596 RTRACE( "radeon_vid: MMIO at 0x%p\n", radeon_mmio_base); | |
597 RTRACE( "radeon_vid: Frame Buffer at 0x%08x\n", radeon_mem_base); | |
598 | |
599 radeon_ram_size = pci_resource_len(dev, 0)/0x100000; | |
600 | |
601 return TRUE; | |
602 } | |
603 | |
604 | |
605 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
606 { | |
607 return -EINVAL; | |
608 } | |
609 | |
610 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
611 { | |
612 return -EINVAL; | |
613 } | |
614 | |
615 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
616 { | |
617 | |
618 RTRACE( "radeon_vid: mapping video memory into userspace\n"); | |
3019 | 619 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 620 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
621 { | |
622 printk( "radeon_vid: error mapping video memory\n"); | |
623 return(-EAGAIN); | |
624 } | |
625 | |
626 return(0); | |
627 } | |
628 | |
629 static int radeon_vid_release(struct inode *inode, struct file *file) | |
630 { | |
631 //Close the window just in case | |
632 radeon_vid_in_use = 0; | |
633 radeon_vid_stop_video(); | |
634 | |
635 MOD_DEC_USE_COUNT; | |
636 return 0; | |
637 } | |
638 | |
639 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
640 { | |
641 return -ESPIPE; | |
642 } | |
643 | |
644 static int radeon_vid_open(struct inode *inode, struct file *file) | |
645 { | |
646 int minor = MINOR(inode->i_rdev); | |
647 | |
648 if(minor != 0) | |
649 return(-ENXIO); | |
650 | |
651 if(radeon_vid_in_use == 1) | |
652 return(-EBUSY); | |
653 | |
654 radeon_vid_in_use = 1; | |
655 MOD_INC_USE_COUNT; | |
656 return(0); | |
657 } | |
658 | |
659 #if LINUX_VERSION_CODE >= 0x020400 | |
660 static struct file_operations radeon_vid_fops = | |
661 { | |
662 llseek: radeon_vid_lseek, | |
663 read: radeon_vid_read, | |
664 write: radeon_vid_write, | |
665 ioctl: radeon_vid_ioctl, | |
666 mmap: radeon_vid_mmap, | |
667 open: radeon_vid_open, | |
668 release: radeon_vid_release | |
669 }; | |
670 #else | |
671 static struct file_operations radeon_vid_fops = | |
672 { | |
673 radeon_vid_lseek, | |
674 radeon_vid_read, | |
675 radeon_vid_write, | |
676 NULL, | |
677 NULL, | |
678 radeon_vid_ioctl, | |
679 radeon_vid_mmap, | |
680 radeon_vid_open, | |
681 NULL, | |
682 radeon_vid_release | |
683 }; | |
684 #endif | |
685 | |
686 /* | |
687 * Main Initialization Function | |
688 */ | |
689 | |
690 | |
691 static int radeon_vid_initialize(void) | |
692 { | |
693 radeon_vid_in_use = 0; | |
694 | |
3066 | 695 printk( "radeon_vid: Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); |
2870 | 696 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
697 { | |
698 printk( "radeon_vid: unable to get major: %d\n", RADEON_VID_MAJOR); | |
699 return -EIO; | |
700 } | |
701 | |
702 if (!radeon_vid_config_card()) | |
703 { | |
704 printk("radeon_vid: can't configure this card\n"); | |
705 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); | |
706 return -EINVAL; | |
707 } | |
708 radeon_vid_save_state(); | |
709 return(0); | |
710 } | |
711 | |
712 int init_module(void) | |
713 { | |
714 return radeon_vid_initialize(); | |
715 } | |
716 | |
717 void cleanup_module(void) | |
718 { | |
719 radeon_vid_restore_state(); | |
720 if(radeon_mmio_base) | |
721 iounmap(radeon_mmio_base); | |
722 | |
723 RTRACE( "radeon_vid: Cleaning up module\n"); | |
724 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); | |
725 } | |
726 |