2870
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1 /*
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2 *
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3 * radeon_vid.c
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4 *
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5 * Copyright (C) 2001 Nick Kurshev
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6 *
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7 * BES YUV Framebuffer driver for Radeon cards
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8 *
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9 * This software has been released under the terms of the GNU Public
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10 * license. See http://www.gnu.org/copyleft/gpl.html for details.
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11 *
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12 * This file is partly based on mga_vid and sis_vid stuff from
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13 * mplayer's package.
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2917
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14 * Also here was used code from CVS of GATOS project and X11 trees.
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15 */
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16
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17 #define RADEON_VID_VERSION "0.9.9"
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18
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19 /*
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20 It's entirely possible this major conflicts with something else
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21 mknod /dev/radeon_vid c 178 0
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22 */
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23
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24 /*
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25 TODO:
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26 OV0_COLOUR_CNTL brightness saturation
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27 SCALER_GAMMA_SEL_BRIGHT gamma correction ???
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28 OV0_GRAPHICS_KEY_CLR color key
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29 OV0_AUTO_FLIP_CNTL
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30 OV0_FILTER_CNTL
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31 OV0_VIDEO_KEY_CLR
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32 OV0_KEY_CNTL
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33
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34 BPP should be known
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35 */
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36
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37 #include <linux/config.h>
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38 #include <linux/version.h>
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39 #include <linux/module.h>
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40 #include <linux/types.h>
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41 #include <linux/kernel.h>
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42 #include <linux/sched.h>
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43 #include <linux/mm.h>
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44 #include <linux/string.h>
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45 #include <linux/errno.h>
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46 #include <linux/slab.h>
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47 #include <linux/pci.h>
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48 #include <linux/ioport.h>
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49 #include <linux/init.h>
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50
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51 #include "radeon_vid.h"
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52 #include "radeon.h"
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53
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54 #ifdef CONFIG_MTRR
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55 #include <asm/mtrr.h>
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56 #endif
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57
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58 #include <asm/uaccess.h>
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59 #include <asm/system.h>
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60 #include <asm/io.h>
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61
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62 #define TRUE 1
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63 #define FALSE 0
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64
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65 #define RADEON_VID_MAJOR 178
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66
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67
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68 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>");
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69 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION);
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70 #ifdef MODULE_LICENSE
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2870
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71 MODULE_LICENSE("GPL");
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72 #endif
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73
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74 typedef struct bes_registers_s
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75 {
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76 /* base address of yuv framebuffer */
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77 uint32_t yuv_base;
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78 uint32_t fourcc;
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79 /* YUV BES registers */
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80 uint32_t reg_load_cntl;
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81 uint32_t h_inc;
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82 uint32_t step_by;
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83 uint32_t y_x_start;
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84 uint32_t y_x_end;
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85 uint32_t v_inc;
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86 uint32_t p1_blank_lines_at_top;
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87 uint32_t p23_blank_lines_at_top;
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88 uint32_t vid_buf_pitch0_value;
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89 uint32_t vid_buf_pitch1_value;
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90 uint32_t p1_x_start_end;
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91 uint32_t p2_x_start_end;
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92 uint32_t p3_x_start_end;
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93 uint32_t vid_buf0_base_adrs;
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94 /* These ones are for auto flip: maybe in the future */
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95 uint32_t vid_buf1_base_adrs;
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96 uint32_t vid_buf2_base_adrs;
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97 uint32_t vid_buf3_base_adrs;
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98 uint32_t vid_buf4_base_adrs;
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99 uint32_t vid_buf5_base_adrs;
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100
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101 uint32_t p1_v_accum_init;
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102 uint32_t p1_h_accum_init;
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103 uint32_t p23_v_accum_init;
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104 uint32_t p23_h_accum_init;
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105 uint32_t scale_cntl;
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106 uint32_t exclusive_horz;
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107 uint32_t auto_flip_cntl;
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108 uint32_t filter_cntl;
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109 uint32_t colour_cntl;
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110 uint32_t graphics_key_msk;
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111 uint32_t graphics_key_clr;
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112 uint32_t key_cntl;
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113 uint32_t test;
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114 } bes_registers_t;
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115
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116 typedef struct video_registers_s
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117 {
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118 uint32_t name;
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119 uint32_t value;
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120 }video_registers_t;
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121
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122 static bes_registers_t besr;
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123 static video_registers_t vregs[] =
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124 {
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125 { OV0_REG_LOAD_CNTL, 0 },
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126 { OV0_H_INC, 0 },
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127 { OV0_STEP_BY, 0 },
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128 { OV0_Y_X_START, 0 },
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129 { OV0_Y_X_END, 0 },
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130 { OV0_V_INC, 0 },
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131 { OV0_P1_BLANK_LINES_AT_TOP, 0 },
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132 { OV0_P23_BLANK_LINES_AT_TOP, 0 },
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133 { OV0_VID_BUF_PITCH0_VALUE, 0 },
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134 { OV0_VID_BUF_PITCH1_VALUE, 0 },
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135 { OV0_P1_X_START_END, 0 },
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136 { OV0_P2_X_START_END, 0 },
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137 { OV0_P3_X_START_END, 0 },
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138 { OV0_VID_BUF0_BASE_ADRS, 0 },
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139 { OV0_VID_BUF1_BASE_ADRS, 0 },
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140 { OV0_VID_BUF2_BASE_ADRS, 0 },
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141 { OV0_VID_BUF3_BASE_ADRS, 0 },
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142 { OV0_VID_BUF4_BASE_ADRS, 0 },
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143 { OV0_VID_BUF5_BASE_ADRS, 0 },
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144 { OV0_P1_V_ACCUM_INIT, 0 },
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145 { OV0_P1_H_ACCUM_INIT, 0 },
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146 { OV0_P23_V_ACCUM_INIT, 0 },
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147 { OV0_P23_H_ACCUM_INIT, 0 },
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148 { OV0_SCALE_CNTL, 0 },
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149 { OV0_EXCLUSIVE_HORZ, 0 },
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150 { OV0_AUTO_FLIP_CNTL, 0 },
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151 { OV0_FILTER_CNTL, 0 },
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152 { OV0_COLOUR_CNTL, 0 },
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153 { OV0_GRAPHICS_KEY_MSK, 0 },
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154 { OV0_GRAPHICS_KEY_CLR, 0 },
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155 { OV0_KEY_CNTL, 0 },
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156 { OV0_TEST, 0 }
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157 };
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158
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159 static uint32_t radeon_vid_in_use = 0;
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160
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161 static uint8_t *radeon_mmio_base = 0;
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162 static uint32_t radeon_mem_base = 0;
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163 static int32_t radeon_overlay_off = 0;
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164
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165 static uint32_t radeon_ram_size = 0;
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166
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167 //static struct video_window radeon_win;
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168 static mga_vid_config_t radeon_config;
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169
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170 #undef DEBUG
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171 #if DEBUG
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172 #define RTRACE printk
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173 #else
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174 #define RTRACE(...) ((void)0)
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175 #endif
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176
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177
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178 /*
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179 * IO macros
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180 */
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181
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182 #define INREG8(addr) readb((radeon_mmio_base)+addr)
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183 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr)
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184 #define INREG(addr) readl((radeon_mmio_base)+addr)
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185 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr)
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186
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187 static void radeon_vid_save_state( void )
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188 {
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189 size_t i;
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190 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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191 vregs[i].value = INREG(vregs[i].name);
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192 }
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193
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194 static void radeon_vid_restore_state( void )
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195 {
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196 size_t i;
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197 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
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198 OUTREG(vregs[i].name,vregs[i].value);
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199 }
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200
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201 static void radeon_vid_stop_video( void )
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202 {
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203 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET);
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204 OUTREG(OV0_EXCLUSIVE_HORZ, 0);
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205 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */
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206 OUTREG(OV0_FILTER_CNTL, 0x0000000f);
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207 /*
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208 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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209 (saturation << 8) |
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210 (saturation << 16));
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211 OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1);
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212 OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey);
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213 */
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214 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE);
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215 OUTREG(OV0_TEST, 0);
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216 }
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217
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218 static void radeon_vid_display_video( void )
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219 {
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220 int bes_flags;
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221 RTRACE("radeon_vid: OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by);
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222 RTRACE("radeon_vid: OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs);
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223 RTRACE("radeon_vid: OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
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224 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value);
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225 RTRACE("radeon_vid: OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n"
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226 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end);
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227 RTRACE("radeon_vid: OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n"
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228 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init);
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229 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
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230 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
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231
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232 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
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233
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234 OUTREG(OV0_DEINTERLACE_PATTERN,0xAAAAAAAA);
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235
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236 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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237 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
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238
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239 OUTREG(OV0_H_INC, besr.h_inc);
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240 OUTREG(OV0_STEP_BY, besr.step_by);
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241 OUTREG(OV0_Y_X_START, besr.y_x_start);
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242 OUTREG(OV0_Y_X_END, besr.y_x_end);
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243 OUTREG(OV0_V_INC, besr.v_inc);
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244 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top);
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245 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value);
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246 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value);
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247 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end);
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248 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end);
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249 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end);
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250 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs);
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251 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs);
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252 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs);
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253 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs);
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254 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs);
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255 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs);
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256 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init);
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257 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init);
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258 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init);
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259
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260 bes_flags = SCALER_ENABLE |
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261 SCALER_DOUBLE_BUFFER |
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262 SCALER_ADAPTIVE_DEINT |
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263 SCALER_SMART_SWITCH |
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264 SCALER_HORZ_PICK_NEAREST;
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265 switch(besr.fourcc)
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266 {
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267 case IMGFMT_RGB15:
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268 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break;
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269 case IMGFMT_RGB16:
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270 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break;
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271 case IMGFMT_RGB24:
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272 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break;
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273 case IMGFMT_RGB32:
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274 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break;
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275
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276 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break;
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277 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break;
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278 case IMGFMT_IYUV: bes_flags |= SCALER_SOURCE_YUV12; break;
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279
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280 case IMGFMT_I420:
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281 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12 |
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282 SCALER_PIX_EXPAND |
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283 SCALER_Y2R_TEMP;
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284 break;
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285 case IMGFMT_YUY2:
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286 default: bes_flags |= SCALER_SOURCE_VYUY422; break;
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287 }
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288 RTRACE("radeon_vid: OV0: SCALER=%x\n",bes_flags);
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289 OUTREG(OV0_SCALE_CNTL, bes_flags);
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290 /*
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291 TODO:
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292 brightness: -64 : +63
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293 saturation: 0 : 31
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294 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) |
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295 (saturation << 8) |
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296 (saturation << 16));
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297 OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16);
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298
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299 */
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300 OUTREG(OV0_REG_LOAD_CNTL, 0);
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301 }
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302
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303 static void radeon_vid_start_video( void )
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304 {
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305 radeon_vid_display_video();
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306 }
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307
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308 #define XXX_SRC_X 0
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309 #define XXX_SRC_Y 0
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310
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311 #define XXX_WIDTH config->src_width
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312 #define XXX_HEIGHT config->src_height
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313
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314 #define XXX_DRW_W config->dest_width
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315 #define XXX_DRW_H config->dest_height
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316
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317 static int radeon_vid_init_video( mga_vid_config_t *config )
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318 {
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319 uint32_t tmp,src_w,pitch,h_inc,step_by,left,leftUV,top;
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320 int is_420;
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321 RTRACE("radeon_vid: usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n"
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322 ,(uint32_t)config->version
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323 ,(uint32_t)config->format
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324 ,(uint32_t)config->card_type
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325 ,(uint32_t)config->ram_size
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326 ,(uint32_t)config->src_width
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327 ,(uint32_t)config->src_height
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328 ,(uint32_t)config->x_org
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329 ,(uint32_t)config->y_org
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330 ,(uint32_t)config->dest_width
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331 ,(uint32_t)config->dest_height
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332 ,(uint32_t)config->frame_size
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333 ,(uint32_t)config->num_frames);
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334 radeon_vid_stop_video();
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335 switch(config->format)
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336 {
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337 case IMGFMT_RGB15:
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338 case IMGFMT_BGR15:
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339 case IMGFMT_RGB16:
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340 case IMGFMT_BGR16:
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341 case IMGFMT_RGB24:
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342 case IMGFMT_BGR24:
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343 case IMGFMT_RGB32:
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344 case IMGFMT_BGR32:
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345
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346 case IMGFMT_YVU9:
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347 case IMGFMT_IYUV:
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348 case IMGFMT_UYVY:
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349
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350 case IMGFMT_YV12:
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351 case IMGFMT_I420:
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352 case IMGFMT_YUY2:
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353 break;
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354 default:
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355 printk( "radeon_vid: Unsupported pixel format: 0x%X\n",config->format);
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356 return -1;
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357 }
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358 is_420 = 0;
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359 if(config->format == IMGFMT_YV12 || config->format == IMGFMT_I420) is_420 = 1;
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360 switch(config->format)
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361 {
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362 default:
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363 case IMGFMT_YVU9:
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364 case IMGFMT_IYUV:
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365 case IMGFMT_UYVY:
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366 case IMGFMT_YV12:
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367 case IMGFMT_I420:
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368 case IMGFMT_YUY2:
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369 case IMGFMT_RGB15:
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370 case IMGFMT_BGR15:
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371 case IMGFMT_RGB16:
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372 case IMGFMT_BGR16: pitch = ((XXX_WIDTH*2) + 15) & ~15; break;
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373 case IMGFMT_RGB24:
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374 case IMGFMT_BGR24: pitch = ((XXX_WIDTH*3) + 15) & ~15; break;
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375 case IMGFMT_RGB32:
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376 case IMGFMT_BGR32: pitch = ((XXX_WIDTH*4) + 15) & ~15; break;
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377 }
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378
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379 left = XXX_SRC_X << 16;
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380 top = XXX_SRC_Y << 16;
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381
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382 besr.fourcc = config->format;
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383
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384 besr.v_inc = (config->src_height << 20) / XXX_DRW_H; /*9c0e0 -> 9c528*/
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385 h_inc = (config->src_width << 12) / XXX_DRW_W;
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386 step_by = 1;
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387
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2944
|
388 while(h_inc >= (2 << 12)) {
|
|
389 step_by++;
|
|
390 h_inc >>= 1;
|
2870
|
391 }
|
|
392
|
|
393 /* keep everything in 16.16 */
|
|
394
|
3019
|
395 if(is_420)
|
|
396 {
|
|
397 uint32_t dstPitch,d1line,d2line,d3line;
|
|
398 dstPitch = (XXX_WIDTH + 31) & ~31; /* of luma */
|
|
399 d1line = top * dstPitch;
|
|
400 d2line = (XXX_HEIGHT * dstPitch) + ((top >> 1) * (dstPitch >> 1));
|
|
401 d3line = d2line + ((XXX_HEIGHT >> 1) * (dstPitch >> 1));
|
|
402 d1line += (left >> 16) & ~15;
|
|
403 d2line += (left >> 17) & ~15;
|
|
404 d3line += (left >> 17) & ~15;
|
|
405 besr.vid_buf0_base_adrs = (radeon_overlay_off + d1line) & 0xfffffff0;
|
|
406 besr.vid_buf1_base_adrs = ((radeon_overlay_off + d2line) & 0xfffffff0) | 0x00000001;
|
|
407 besr.vid_buf2_base_adrs = ((radeon_overlay_off + d3line) & 0xfffffff0) | 0x00000001;
|
|
408 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs;
|
|
409 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs;
|
|
410 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs;
|
|
411 }
|
|
412 else
|
|
413 {
|
|
414 besr.vid_buf0_base_adrs = radeon_overlay_off;
|
|
415 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0;
|
|
416 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
|
|
417 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
|
|
418 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
|
|
419 besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs;
|
|
420 besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
|
|
421 }
|
2870
|
422
|
2951
|
423 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
|
2870
|
424 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
|
2951
|
425 ((tmp << 12) & 0xf0000000);
|
2870
|
426
|
2951
|
427 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
|
2870
|
428 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
|
2951
|
429 ((tmp << 12) & 0x70000000);
|
2870
|
430
|
2951
|
431 tmp = (top & 0x0000ffff) + 0x00018000;
|
2870
|
432 besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001;
|
|
433
|
3019
|
434
|
|
435 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
|
|
436 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & 0x01ff8000) | 0x00000001 : 0;
|
|
437
|
|
438 leftUV = (left >> 17) & 7;
|
2951
|
439 left = (left >> 16) & 7;
|
2944
|
440 besr.h_inc = h_inc | ((h_inc >> 1) << 16);
|
|
441 besr.step_by = step_by | (step_by << 8);
|
2951
|
442 besr.y_x_start = (config->x_org+8) | (config->y_org << 16); /*5c008->5d009*/
|
2925
|
443 besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16);
|
2870
|
444 besr.p1_blank_lines_at_top = 0x00000fff | ((config->src_height - 1) << 16);
|
3019
|
445 besr.p23_blank_lines_at_top = is_420 ? 0x000007ff | ((((config->src_height+1)>>1) - 1) << 16) : 0;
|
2870
|
446 besr.vid_buf_pitch0_value = pitch;
|
3019
|
447 besr.vid_buf_pitch1_value = is_420 ? pitch/2 : pitch;
|
2925
|
448 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by);
|
|
449 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs);
|
2870
|
450 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
|
2925
|
451 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value);
|
2870
|
452 besr.p1_x_start_end = (config->src_width + left - 1) | (left << 16);
|
3019
|
453 src_w=config->src_width >> 1;
|
|
454 besr.p2_x_start_end = (src_w + left - 1) | (leftUV << 16);
|
2870
|
455 besr.p3_x_start_end = besr.p2_x_start_end;
|
|
456 return 0;
|
|
457 }
|
|
458
|
|
459 static void radeon_vid_frame_sel(int frame)
|
|
460 {
|
2917
|
461 uint32_t off;
|
|
462 switch(frame)
|
|
463 {
|
|
464 default:
|
|
465 case 0: off = besr.vid_buf0_base_adrs; break;
|
3019
|
466 case 1: off = besr.vid_buf3_base_adrs; break;
|
|
467 case 2: off = besr.vid_buf0_base_adrs; break;
|
2917
|
468 case 3: off = besr.vid_buf3_base_adrs; break;
|
3019
|
469 case 4: off = besr.vid_buf0_base_adrs; break;
|
|
470 case 5: off = besr.vid_buf3_base_adrs; break;
|
2917
|
471 }
|
|
472 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
|
|
473 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK));
|
|
474 OUTREG(OV0_VID_BUF0_BASE_ADRS, off);
|
|
475 OUTREG(OV0_REG_LOAD_CNTL, 0);
|
2870
|
476 }
|
|
477
|
2951
|
478 static int video_on = 0;
|
|
479
|
2870
|
480 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
|
|
481 {
|
|
482 int frame;
|
|
483
|
|
484 switch(cmd)
|
|
485 {
|
|
486 case MGA_VID_CONFIG:
|
|
487 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base);
|
|
488 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base);
|
|
489 RTRACE( "radeon_vid: Received configuration\n");
|
|
490
|
|
491 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t)))
|
|
492 {
|
|
493 printk( "radeon_vid: failed copy from userspace\n");
|
3019
|
494 return -EFAULT;
|
2870
|
495 }
|
|
496 if(radeon_config.version != MGA_VID_VERSION){
|
|
497 printk( "radeon_vid: incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version);
|
3019
|
498 return -EFAULT;
|
2870
|
499 }
|
|
500
|
|
501 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){
|
|
502 printk( "radeon_vid: illegal frame_size: %d\n",radeon_config.frame_size);
|
3019
|
503 return -EFAULT;
|
2870
|
504 }
|
|
505
|
|
506 if(radeon_config.num_frames<1 || radeon_config.num_frames>4){
|
|
507 printk( "radeon_vid: illegal num_frames: %d\n",radeon_config.num_frames);
|
3019
|
508 return -EFAULT;
|
2870
|
509 }
|
|
510
|
|
511 /* FIXME: Fake of G400 ;) or would be better G200 ??? */
|
|
512 radeon_config.card_type = 0;
|
|
513 radeon_config.ram_size = radeon_ram_size;
|
3019
|
514 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames;
|
|
515 radeon_overlay_off &= 0xffff0000;
|
|
516 if(radeon_overlay_off < 0){
|
|
517 printk("radeon_vid: not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000);
|
|
518 return -EFAULT;
|
|
519 }
|
|
520 RTRACE("radeon_vid: using video overlay at offset %p\n",radeon_overlay_off);
|
2870
|
521 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t)))
|
|
522 {
|
|
523 printk( "radeon_vid: failed copy to userspace\n");
|
3019
|
524 return -EFAULT;
|
2870
|
525 }
|
|
526 return radeon_vid_init_video(&radeon_config);
|
|
527 break;
|
|
528
|
|
529 case MGA_VID_ON:
|
|
530 RTRACE( "radeon_vid: Video ON (ioctl)\n");
|
2925
|
531 radeon_vid_start_video();
|
2951
|
532 video_on = 1;
|
2870
|
533 break;
|
|
534
|
|
535 case MGA_VID_OFF:
|
|
536 RTRACE( "radeon_vid: Video OFF (ioctl)\n");
|
2951
|
537 if(video_on) radeon_vid_stop_video();
|
|
538 video_on = 0;
|
2870
|
539 break;
|
|
540
|
|
541 case MGA_VID_FSEL:
|
|
542 if(copy_from_user(&frame,(int *) arg,sizeof(int)))
|
|
543 {
|
|
544 printk("radeon_vid: FSEL failed copy from userspace\n");
|
|
545 return(-EFAULT);
|
|
546 }
|
|
547 radeon_vid_frame_sel(frame);
|
|
548 break;
|
|
549
|
|
550 default:
|
|
551 printk( "radeon_vid: Invalid ioctl\n");
|
|
552 return (-EINVAL);
|
|
553 }
|
|
554
|
|
555 return 0;
|
|
556 }
|
|
557
|
|
558 struct ati_card_id_s
|
|
559 {
|
|
560 int id;
|
|
561 char name[17];
|
|
562 }ati_card_ids[]=
|
|
563 {
|
|
564 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " },
|
|
565 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " },
|
|
566 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " },
|
|
567 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " },
|
|
568 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " },
|
|
569 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " },
|
|
570 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " },
|
|
571 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " },
|
|
572 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " },
|
|
573 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " },
|
|
574 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " }
|
|
575 };
|
|
576
|
|
577 static int radeon_vid_config_card(void)
|
|
578 {
|
|
579 struct pci_dev *dev = NULL;
|
|
580 size_t i;
|
|
581
|
|
582 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++)
|
|
583 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL)))
|
|
584 break;
|
|
585 if(dev)
|
|
586 printk("radeon_vid: Found %s\n",ati_card_ids[i].name);
|
|
587 else
|
|
588 {
|
|
589 printk("radeon_vid: No supported cards found\n");
|
|
590 return FALSE;
|
|
591 }
|
|
592
|
|
593 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE);
|
|
594 radeon_mem_base = dev->resource[0].start;
|
|
595
|
|
596 RTRACE( "radeon_vid: MMIO at 0x%p\n", radeon_mmio_base);
|
|
597 RTRACE( "radeon_vid: Frame Buffer at 0x%08x\n", radeon_mem_base);
|
|
598
|
|
599 radeon_ram_size = pci_resource_len(dev, 0)/0x100000;
|
|
600
|
|
601 return TRUE;
|
|
602 }
|
|
603
|
|
604
|
|
605 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos)
|
|
606 {
|
|
607 return -EINVAL;
|
|
608 }
|
|
609
|
|
610 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
|
|
611 {
|
|
612 return -EINVAL;
|
|
613 }
|
|
614
|
|
615 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma)
|
|
616 {
|
|
617
|
|
618 RTRACE( "radeon_vid: mapping video memory into userspace\n");
|
3019
|
619 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off,
|
2870
|
620 vma->vm_end - vma->vm_start, vma->vm_page_prot))
|
|
621 {
|
|
622 printk( "radeon_vid: error mapping video memory\n");
|
|
623 return(-EAGAIN);
|
|
624 }
|
|
625
|
|
626 return(0);
|
|
627 }
|
|
628
|
|
629 static int radeon_vid_release(struct inode *inode, struct file *file)
|
|
630 {
|
|
631 //Close the window just in case
|
|
632 radeon_vid_in_use = 0;
|
|
633 radeon_vid_stop_video();
|
|
634
|
|
635 MOD_DEC_USE_COUNT;
|
|
636 return 0;
|
|
637 }
|
|
638
|
|
639 static long long radeon_vid_lseek(struct file *file, long long offset, int origin)
|
|
640 {
|
|
641 return -ESPIPE;
|
|
642 }
|
|
643
|
|
644 static int radeon_vid_open(struct inode *inode, struct file *file)
|
|
645 {
|
|
646 int minor = MINOR(inode->i_rdev);
|
|
647
|
|
648 if(minor != 0)
|
|
649 return(-ENXIO);
|
|
650
|
|
651 if(radeon_vid_in_use == 1)
|
|
652 return(-EBUSY);
|
|
653
|
|
654 radeon_vid_in_use = 1;
|
|
655 MOD_INC_USE_COUNT;
|
|
656 return(0);
|
|
657 }
|
|
658
|
|
659 #if LINUX_VERSION_CODE >= 0x020400
|
|
660 static struct file_operations radeon_vid_fops =
|
|
661 {
|
|
662 llseek: radeon_vid_lseek,
|
|
663 read: radeon_vid_read,
|
|
664 write: radeon_vid_write,
|
|
665 ioctl: radeon_vid_ioctl,
|
|
666 mmap: radeon_vid_mmap,
|
|
667 open: radeon_vid_open,
|
|
668 release: radeon_vid_release
|
|
669 };
|
|
670 #else
|
|
671 static struct file_operations radeon_vid_fops =
|
|
672 {
|
|
673 radeon_vid_lseek,
|
|
674 radeon_vid_read,
|
|
675 radeon_vid_write,
|
|
676 NULL,
|
|
677 NULL,
|
|
678 radeon_vid_ioctl,
|
|
679 radeon_vid_mmap,
|
|
680 radeon_vid_open,
|
|
681 NULL,
|
|
682 radeon_vid_release
|
|
683 };
|
|
684 #endif
|
|
685
|
|
686 /*
|
|
687 * Main Initialization Function
|
|
688 */
|
|
689
|
|
690
|
|
691 static int radeon_vid_initialize(void)
|
|
692 {
|
|
693 radeon_vid_in_use = 0;
|
|
694
|
|
695 RTRACE( "Radeon BES YUV Video interface v0.01 (c) Nick Kurshev\n");
|
|
696 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops))
|
|
697 {
|
|
698 printk( "radeon_vid: unable to get major: %d\n", RADEON_VID_MAJOR);
|
|
699 return -EIO;
|
|
700 }
|
|
701
|
|
702 if (!radeon_vid_config_card())
|
|
703 {
|
|
704 printk("radeon_vid: can't configure this card\n");
|
|
705 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");
|
|
706 return -EINVAL;
|
|
707 }
|
|
708 radeon_vid_save_state();
|
|
709 return(0);
|
|
710 }
|
|
711
|
|
712 int init_module(void)
|
|
713 {
|
|
714 return radeon_vid_initialize();
|
|
715 }
|
|
716
|
|
717 void cleanup_module(void)
|
|
718 {
|
|
719 radeon_vid_restore_state();
|
|
720 if(radeon_mmio_base)
|
|
721 iounmap(radeon_mmio_base);
|
|
722
|
|
723 RTRACE( "radeon_vid: Cleaning up module\n");
|
|
724 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");
|
|
725 }
|
|
726
|