Mercurial > mplayer.hg
annotate vidix/savage_vid.c @ 23057:217694b1c1af
declare variables and functions as static
author | ben |
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date | Sun, 22 Apr 2007 15:39:18 +0000 |
parents | 7973a6935234 |
children | 5366657d357e |
rev | line source |
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22850 | 1 /* |
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2 * VIDIX driver for S3 Savage chipsets. |
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3 * Copyright (C) 2004 Reza Jelveh |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with MPlayer; if not, write to the Free Software |
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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20 * |
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21 * Thanks to Alex Deucher for Support |
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22 */ |
22850 | 23 |
24 #include <errno.h> | |
25 #include <stdio.h> | |
26 #include <stdlib.h> | |
27 #include <string.h> | |
28 #include <inttypes.h> | |
29 #include <unistd.h> | |
30 #include <math.h> | |
31 | |
32 #include "vidix.h" | |
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33 #include "vidixlib.h" |
22850 | 34 #include "fourcc.h" |
22901 | 35 #include "dha.h" |
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36 #include "pci_ids.h" |
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37 #include "pci_names.h" |
22905 | 38 #include "config.h" |
22850 | 39 |
40 #include "savage_regs.h" | |
41 | |
42 | |
43 #define VF_STREAMS_ON 0x0001 | |
44 #define BASE_PAD 0xf | |
45 #define FRAMEBUFFER_SIZE 1024*2000*4 | |
46 /************************************** | |
47 S3 streams processor | |
48 **************************************/ | |
49 | |
50 #define EXT_MISC_CTRL2 0x67 | |
51 | |
52 /* New streams */ | |
53 | |
54 /* CR67[2] = 1 : enable stream 1 */ | |
55 #define ENABLE_STREAM1 0x04 | |
56 /* CR67[1] = 1 : enable stream 2 */ | |
57 #define ENABLE_STREAM2 0x02 | |
58 /* mask to clear CR67[2,1] */ | |
59 #define NO_STREAMS 0xF9 | |
60 /* CR67[3] = 1 : Mem-mapped regs */ | |
61 #define USE_MM_FOR_PRI_STREAM 0x08 | |
62 | |
63 #define HDM_SHIFT 16 | |
64 #define HDSCALE_4 (2 << HDM_SHIFT) | |
65 #define HDSCALE_8 (3 << HDM_SHIFT) | |
66 #define HDSCALE_16 (4 << HDM_SHIFT) | |
67 #define HDSCALE_32 (5 << HDM_SHIFT) | |
68 #define HDSCALE_64 (6 << HDM_SHIFT) | |
69 | |
70 /* Old Streams */ | |
71 | |
72 #define ENABLE_STREAMS_OLD 0x0c | |
73 #define NO_STREAMS_OLD 0xf3 | |
74 /* CR69[0] = 1 : Mem-mapped regs */ | |
75 #define USE_MM_FOR_PRI_STREAM_OLD 0x01 | |
76 | |
23057 | 77 static void SavageStreamsOn(void); |
22850 | 78 |
79 /* | |
80 * There are two different streams engines used in the Savage line. | |
81 * The old engine is in the 3D, 4, Pro, and Twister. | |
82 * The new engine is in the 2000, MX, IX, and Super. | |
83 */ | |
84 | |
85 | |
86 /* streams registers for old engine */ | |
87 #define PSTREAM_CONTROL_REG 0x8180 | |
88 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 | |
89 #define SSTREAM_CONTROL_REG 0x8190 | |
90 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 | |
91 #define SSTREAM_STRETCH_REG 0x8198 | |
92 #define COLOR_ADJUSTMENT_REG 0x819C | |
93 #define BLEND_CONTROL_REG 0x81A0 | |
94 #define PSTREAM_FBADDR0_REG 0x81C0 | |
95 #define PSTREAM_FBADDR1_REG 0x81C4 | |
96 #define PSTREAM_STRIDE_REG 0x81C8 | |
97 #define DOUBLE_BUFFER_REG 0x81CC | |
98 #define SSTREAM_FBADDR0_REG 0x81D0 | |
99 #define SSTREAM_FBADDR1_REG 0x81D4 | |
100 #define SSTREAM_STRIDE_REG 0x81D8 | |
101 #define SSTREAM_VSCALE_REG 0x81E0 | |
102 #define SSTREAM_VINITIAL_REG 0x81E4 | |
103 #define SSTREAM_LINES_REG 0x81E8 | |
104 #define STREAMS_FIFO_REG 0x81EC | |
105 #define PSTREAM_WINDOW_START_REG 0x81F0 | |
106 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 | |
107 #define SSTREAM_WINDOW_START_REG 0x81F8 | |
108 #define SSTREAM_WINDOW_SIZE_REG 0x81FC | |
109 #define FIFO_CONTROL 0x8200 | |
110 #define PSTREAM_FBSIZE_REG 0x8300 | |
111 #define SSTREAM_FBSIZE_REG 0x8304 | |
112 #define SSTREAM_FBADDR2_REG 0x8308 | |
113 | |
114 #define OS_XY(x,y) (((x+1)<<16)|(y+1)) | |
115 #define OS_WH(x,y) (((x-1)<<16)|(y)) | |
116 | |
117 #define PCI_COMMAND_MEM 0x2 | |
118 #define MAX_FRAMES 3 | |
119 /** | |
120 * @brief Information on PCI device. | |
121 */ | |
23057 | 122 static pciinfo_t pci_info; |
22850 | 123 |
23057 | 124 static uint8_t *vio; |
125 static uint8_t mclk_save[3]; | |
22850 | 126 |
127 #define outb(reg,val) OUTPORT8(reg,val) | |
128 #define inb(reg) INPORT8(reg) | |
129 #define outw(reg,val) OUTPORT16(reg,val) | |
130 #define inw(reg) INPORT16(reg) | |
131 #define outl(reg,val) OUTPORT32(reg,val) | |
132 #define inl(reg) INPORT32(reg) | |
133 | |
134 | |
135 /* | |
136 * PCI-Memory IO access macros. | |
137 */ | |
138 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
139 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
140 | |
141 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
142 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
143 | |
144 #ifndef USE_RMW_CYCLES | |
145 /* | |
146 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
147 */ | |
148 | |
149 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
150 | |
151 #undef VID_WR08 | |
152 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
153 #undef VID_RD08 | |
154 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
155 | |
156 #undef VID_WR16 | |
157 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) | |
158 #undef VID_RD16 | |
159 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) | |
160 | |
161 #undef VID_WR32 | |
162 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
163 #undef VID_RD32 | |
164 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
165 #endif /* USE_RMW_CYCLES */ | |
166 | |
167 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
168 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
169 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
170 | |
171 | |
172 /* from x driver */ | |
173 | |
174 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) | |
175 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) | |
176 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) | |
177 | |
178 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) | |
179 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) | |
180 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) | |
181 | |
182 #define INREG(addr) VID_RD32(info->control_base, addr) | |
183 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) | |
184 #define INREG8(addr) VID_RD08(info->control_base, addr) | |
185 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) | |
186 #define INREG16(addr) VID_RD16(info->control_base, addr) | |
187 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) | |
188 | |
189 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) | |
190 | |
191 | |
23057 | 192 static void debugout(unsigned int addr, unsigned int val); |
22850 | 193 |
194 | |
195 struct savage_chip { | |
196 volatile uint32_t *PMC; /* general control */ | |
197 volatile uint32_t *PME; /* multimedia port */ | |
198 volatile uint32_t *PFB; /* framebuffer control */ | |
199 volatile uint32_t *PVIDEO; /* overlay control */ | |
200 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
201 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
202 volatile uint32_t *PRAMIN; /* instance memory */ | |
203 volatile uint32_t *PRAMHT; /* hash table */ | |
204 volatile uint32_t *PRAMFC; /* fifo context table */ | |
205 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
206 volatile uint32_t *PFIFO; /* fifo control region */ | |
207 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
208 volatile uint32_t *PGRAPH; /* graphics engine */ | |
209 | |
210 int arch; /* compatible NV_ARCH_XX define */ | |
211 unsigned long fbsize; /* framebuffer size */ | |
212 void (* lock) (struct savage_chip *, int); | |
213 }; | |
214 typedef struct savage_chip savage_chip; | |
215 | |
216 | |
217 struct savage_info { | |
218 unsigned int use_colorkey; | |
219 unsigned int colorkey; /* saved xv colorkey*/ | |
220 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
221 unsigned int depth; | |
222 unsigned int bpp; | |
223 unsigned int videoFlags; | |
224 unsigned int format; | |
225 unsigned int pitch; | |
226 unsigned int blendBase; | |
227 unsigned int lastKnownPitch; | |
228 unsigned int displayWidth, displayHeight; | |
229 unsigned int brightness,hue,saturation,contrast; | |
230 unsigned int src_w,src_h; | |
231 unsigned int drw_w,drw_h; /*scaled width && height*/ | |
232 unsigned int wx,wy; /*window x && y*/ | |
233 unsigned int screen_x; /*screen width*/ | |
234 unsigned int screen_y; /*screen height*/ | |
235 unsigned long buffer_size; /* size of the image buffer */ | |
236 struct savage_chip chip; /* NV architecture structure */ | |
237 void* video_base; /* virtual address of control region */ | |
238 void* control_base; /* virtual address of fb region */ | |
239 unsigned long picture_base; /* direct pointer to video picture */ | |
240 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
241 // struct savage_dma dma; /* DMA structure */ | |
242 unsigned int cur_frame; | |
243 unsigned int num_frames; /* number of buffers */ | |
244 int bps; /* bytes per line */ | |
245 void (*SavageWaitIdle) (); | |
246 void (*SavageWaitFifo) (int space); | |
247 }; | |
248 typedef struct savage_info savage_info; | |
249 | |
250 | |
251 static savage_info* info; | |
252 | |
253 | |
254 /** | |
255 * @brief Unichrome driver vidix capabilities. | |
256 */ | |
257 static vidix_capability_t savage_cap = { | |
258 "Savage/ProSavage/Twister vidix", | |
259 "Reza Jelveh <reza.jelveh@tuhh.de>", | |
260 TYPE_OUTPUT, | |
261 {0, 0, 0, 0}, | |
262 4096, | |
263 4096, | |
264 4, | |
265 4, | |
266 -1, | |
267 FLAG_UPSCALER | FLAG_DOWNSCALER, | |
268 VENDOR_S3_INC, | |
269 -1, | |
270 {0, 0, 0, 0} | |
271 }; | |
272 | |
273 struct savage_cards { | |
274 unsigned short chip_id; | |
275 unsigned short arch; | |
276 }; | |
277 | |
278 | |
279 static | |
280 unsigned int GetBlendForFourCC( int id ) | |
281 { | |
282 switch( id ) { | |
283 case IMGFMT_YUY2: | |
284 case IMGFMT_YV12: | |
285 case IMGFMT_I420: | |
286 return 1; | |
287 case IMGFMT_Y211: | |
288 return 4; | |
289 case IMGFMT_RGB15: | |
290 return 3; | |
291 case IMGFMT_RGB16: | |
292 return 5; | |
293 default: | |
294 return 0; | |
295 } | |
296 } | |
297 | |
298 /** | |
299 * @brief list of card IDs compliant with the Unichrome driver . | |
300 */ | |
301 static struct savage_cards savage_card_ids[] = { | |
302 /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ | |
303 { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, | |
304 /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ | |
305 { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, | |
306 /*ProSavage DDR*/ | |
307 { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, | |
308 /*[ProSavageDDR P4M266 K] */ | |
309 { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, | |
310 }; | |
311 | |
312 static void SavageSetColorOld(void) | |
313 { | |
314 | |
315 | |
316 if( | |
317 (info->format == IMGFMT_RGB15) || | |
318 (info->format == IMGFMT_RGB16) | |
319 ) | |
320 { | |
321 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
322 } | |
323 else | |
324 { | |
325 /* Change 0..255 into 0..15 */ | |
326 long sat = info->saturation * 16 / 256; | |
327 double hue = info->hue * 0.017453292; | |
328 unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; | |
329 unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; | |
330 | |
331 OUTREG( COLOR_ADJUSTMENT_REG, | |
332 0x80008000 | | |
333 (info->brightness + 128) | | |
334 ((info->contrast & 0xf8) << (12-7)) | | |
335 (hs1 << 16) | | |
336 (hs2 << 24) | |
337 ); | |
338 debugout( COLOR_ADJUSTMENT_REG, | |
339 0x80008000 | | |
340 (info->brightness + 128) | | |
341 ((info->contrast & 0xf8) << (12-7)) | | |
342 (hs1 << 16) | | |
343 (hs2 << 24) | |
344 ); | |
345 | |
346 } | |
347 } | |
348 | |
349 static void SavageSetColorKeyOld(void) | |
350 { | |
351 int red, green, blue; | |
352 | |
353 /* Here, we reset the colorkey and all the controls. */ | |
354 | |
355 red = (info->vidixcolorkey & 0x00FF0000) >> 16; | |
356 green = (info->vidixcolorkey & 0x0000FF00) >> 8; | |
357 blue = info->vidixcolorkey & 0x000000FF; | |
358 | |
359 if( !info->vidixcolorkey ) { | |
360 printf("SavageSetColorKey disabling colorkey\n"); | |
361 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
362 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
363 OUTREG( BLEND_CONTROL_REG, 0 ); | |
364 } | |
365 else { | |
366 switch (info->depth) { | |
367 // FIXME: isnt fixed yet | |
368 case 8: | |
369 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
370 0x37000000 | (info->vidixcolorkey & 0xFF) ); | |
371 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
372 0x00000000 | (info->vidixcolorkey & 0xFF) ); | |
373 break; | |
374 case 15: | |
375 /* 15 bpp 555 */ | |
376 red&=0x1f; | |
377 green&=0x1f; | |
378 blue&=0x1f; | |
379 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
380 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
381 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
382 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
383 break; | |
384 case 16: | |
385 /* 16 bpp 565 */ | |
386 red&=0x1f; | |
387 green&=0x3f; | |
388 blue&=0x1f; | |
389 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
390 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); | |
391 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
392 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); | |
393 break; | |
394 case 24: | |
395 /* 24 bpp 888 */ | |
396 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
397 0x17000000 | (red<<16) | (green<<8) | (blue) ); | |
398 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
399 0x00000000 | (red<<16) | (green<<8) | (blue) ); | |
400 break; | |
401 } | |
402 | |
403 /* We use destination colorkey */ | |
404 OUTREG( BLEND_CONTROL_REG, 0x05000000 ); | |
405 } | |
406 } | |
407 | |
408 | |
409 static void | |
410 SavageDisplayVideoOld(void) | |
411 { | |
412 int vgaCRIndex, vgaCRReg, vgaIOBase; | |
413 unsigned int ssControl; | |
414 int cr92; | |
415 | |
416 | |
417 vgaIOBase = 0x3d0; | |
418 vgaCRIndex = vgaIOBase + 4; | |
419 vgaCRReg = vgaIOBase + 5; | |
420 | |
421 // if( psav->videoFourCC != id ) | |
422 // SavageStreamsOff(pScrn); | |
423 | |
424 if( !info->videoFlags & VF_STREAMS_ON ) | |
425 { | |
426 SavageStreamsOn(); | |
427 // SavageResetVideo(); | |
428 SavageSetColorOld(); | |
429 SavageSetColorKeyOld(); | |
430 } | |
431 | |
432 | |
433 | |
434 | |
435 /* Set surface format. */ | |
436 | |
437 OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
438 | |
439 debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
440 | |
441 /* Calculate horizontal scale factor. */ | |
442 | |
443 //FIXME: enable scaling | |
444 OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); | |
445 // debugout(SSTREAM_STRETCH_REG, 1 << 15); | |
446 | |
447 OUTREG(SSTREAM_LINES_REG, info->src_h ); | |
448 debugout(SSTREAM_LINES_REG, info->src_h ); | |
449 | |
450 | |
451 OUTREG(SSTREAM_VINITIAL_REG, 0 ); | |
452 debugout(SSTREAM_VINITIAL_REG, 0 ); | |
453 /* Calculate vertical scale factor. */ | |
454 | |
455 // OUTREG(SSTREAM_VSCALE_REG, 1 << 15); | |
456 OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
457 debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
458 // OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); | |
459 | |
460 /* Set surface location and stride. */ | |
461 | |
462 OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
463 debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
464 | |
465 OUTREG(SSTREAM_FBADDR1_REG, 0 ); | |
466 debugout(SSTREAM_FBADDR1_REG, 0 ); | |
467 | |
468 OUTREG(SSTREAM_STRIDE_REG, info->pitch ); | |
469 debugout(SSTREAM_STRIDE_REG, info->pitch ); | |
470 | |
471 OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
472 debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
473 OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
474 debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
475 | |
476 | |
477 | |
478 ssControl = 0; | |
479 | |
480 if( info->src_w > (info->drw_w << 1) ) | |
481 { | |
482 /* BUGBUG shouldn't this be >=? */ | |
483 if( info->src_w <= (info->drw_w << 2) ) | |
484 ssControl |= HDSCALE_4; | |
485 else if( info->src_w > (info->drw_w << 3) ) | |
486 ssControl |= HDSCALE_8; | |
487 else if( info->src_w > (info->drw_w << 4) ) | |
488 ssControl |= HDSCALE_16; | |
489 else if( info->src_w > (info->drw_w << 5) ) | |
490 ssControl |= HDSCALE_32; | |
491 else if( info->src_w > (info->drw_w << 6) ) | |
492 ssControl |= HDSCALE_64; | |
493 } | |
494 | |
495 ssControl |= info->src_w; | |
496 ssControl |= (1 << 24); | |
497 | |
498 //FIXME: enable scaling | |
499 OUTREG(SSTREAM_CONTROL_REG, ssControl); | |
500 debugout(SSTREAM_CONTROL_REG, ssControl); | |
501 | |
502 // FIXME: this should actually be enabled | |
503 | |
504 info->pitch = (info->pitch + 7) / 8; | |
505 VGAOUT8(vgaCRIndex, 0x92); | |
506 cr92 = VGAIN8(vgaCRReg); | |
507 VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); | |
508 VGAOUT8(vgaCRIndex, 0x93); | |
509 VGAOUT8(vgaCRReg, info->pitch); | |
510 OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); | |
511 | |
512 | |
513 | |
514 | |
515 } | |
516 | |
517 static void SavageInitStreamsOld(void) | |
518 { | |
519 /*unsigned long jDelta;*/ | |
520 unsigned long format = 0; | |
521 | |
522 /* | |
523 * For the OLD streams engine, several of these registers | |
524 * cannot be touched unless streams are on. Seems backwards to me; | |
525 * I'd want to set 'em up, then cut 'em loose. | |
526 */ | |
527 | |
528 | |
529 /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ | |
530 switch( info->depth ) { | |
531 case 8: format = 0 << 24; break; | |
532 case 15: format = 3 << 24; break; | |
533 case 16: format = 5 << 24; break; | |
534 case 24: format = 7 << 24; break; | |
535 } | |
536 #warning enable this again | |
537 OUTREG(PSTREAM_FBSIZE_REG, | |
538 info->screen_y * info->screen_x * (info->bpp >> 3)); | |
539 | |
540 OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); | |
541 OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); | |
542 OUTREG( PSTREAM_FBADDR1_REG, 0 ); | |
543 /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ | |
544 OUTREG( PSTREAM_CONTROL_REG, format ); | |
545 OUTREG( PSTREAM_FBADDR0_REG, 0 ); | |
546 | |
547 /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ | |
548 | |
549 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
550 OUTREG( SSTREAM_CONTROL_REG, 0 ); | |
551 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
552 OUTREG( SSTREAM_STRETCH_REG, 0 ); | |
553 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
554 OUTREG( BLEND_CONTROL_REG, 1 << 24 ); | |
555 OUTREG( DOUBLE_BUFFER_REG, 0 ); | |
556 OUTREG( SSTREAM_FBADDR0_REG, 0 ); | |
557 OUTREG( SSTREAM_FBADDR1_REG, 0 ); | |
558 OUTREG( SSTREAM_FBADDR2_REG, 0 ); | |
559 OUTREG( SSTREAM_FBSIZE_REG, 0 ); | |
560 OUTREG( SSTREAM_STRIDE_REG, 0 ); | |
561 OUTREG( SSTREAM_VSCALE_REG, 0 ); | |
562 OUTREG( SSTREAM_LINES_REG, 0 ); | |
563 OUTREG( SSTREAM_VINITIAL_REG, 0 ); | |
564 #warning is this needed? | |
565 OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
566 OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); | |
567 | |
568 } | |
569 | |
23057 | 570 static void |
22850 | 571 SavageStreamsOn(void) |
572 { | |
573 unsigned char jStreamsControl; | |
574 unsigned short vgaCRIndex = 0x3d0 + 4; | |
575 unsigned short vgaCRReg = 0x3d0 + 5; | |
576 | |
577 // xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); | |
578 | |
579 /* Sequence stolen from streams.c in M7 NT driver */ | |
580 | |
581 | |
582 enable_app_io (); | |
583 | |
584 /* Unlock extended registers. */ | |
585 | |
586 /* FIXME: it looks like mmaped io is broken with vgaout16 */ | |
587 VGAOUT16(vgaCRIndex, 0x4838 ); | |
588 VGAOUT16(vgaCRIndex, 0xa039); | |
589 VGAOUT16(0x3c4, 0x0608); | |
590 | |
591 | |
592 | |
593 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
594 | |
595 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) | |
596 { | |
597 // SavageInitStreamsNew( pScrn ); | |
598 | |
599 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
600 | |
601 /* Wait for VBLANK. */ | |
602 VerticalRetraceWait(); | |
603 /* Fire up streams! */ | |
604 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
605 /* These values specify brightness, contrast, saturation and hue. */ | |
606 OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); | |
607 OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); | |
608 OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); | |
609 } | |
610 else if (info->chip.arch == S3_SAVAGE2000) | |
611 { | |
612 // SavageInitStreams2000( pScrn ); | |
613 | |
614 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
615 | |
616 /* Wait for VBLANK. */ | |
617 VerticalRetraceWait(); | |
618 /* Fire up streams! */ | |
619 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
620 /* These values specify brightness, contrast, saturation and hue. */ | |
621 OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); | |
622 OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); | |
623 OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); | |
624 OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); | |
625 } | |
626 else | |
627 { | |
628 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; | |
629 | |
630 /* Wait for VBLANK. */ | |
631 | |
632 VerticalRetraceWait(); | |
633 | |
634 /* Fire up streams! */ | |
635 | |
636 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
637 | |
638 SavageInitStreamsOld( ); | |
639 } | |
640 | |
641 /* Wait for VBLANK. */ | |
642 | |
643 VerticalRetraceWait(); | |
644 | |
645 /* Turn on secondary stream TV flicker filter, once we support TV. */ | |
646 | |
647 /* SR70 |= 0x10 */ | |
648 | |
649 info->videoFlags |= VF_STREAMS_ON; | |
650 | |
651 } | |
652 | |
653 | |
654 | |
655 | |
656 static void savage_getscreenproperties(struct savage_info *info){ | |
657 unsigned char bpp=0; | |
658 | |
659 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; | |
660 | |
661 vgaIOBase = 0x3d0; | |
662 vgaCRIndex = vgaIOBase + 4; | |
663 vgaCRReg = vgaIOBase + 5; | |
664 | |
665 | |
666 /* a little reversed from x driver source code */ | |
667 VGAOUT8(vgaCRIndex, 0x67); | |
668 bpp = VGAIN8(vgaCRReg); | |
669 | |
670 | |
671 switch (bpp&0xf0) { | |
672 case 0x00: | |
673 case 0x10: | |
674 info->depth=8; | |
675 info->bpp=8; | |
676 break; | |
677 case 0x20: | |
678 case 0x30: | |
679 info->depth=15; | |
680 info->bpp=16; | |
681 break; | |
682 case 0x40: | |
683 case 0x50: | |
684 info->depth=16; | |
685 info->bpp=16; | |
686 break; | |
687 case 0x70: | |
688 case 0xd0: | |
689 info->depth=24; | |
690 info->bpp=32; | |
691 break; | |
692 | |
693 | |
694 } | |
695 | |
696 | |
697 VGAOUT8(vgaCRIndex, 0x1); | |
698 info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; | |
699 /*get screen height*/ | |
700 /* get first 8 bits in VT_DISPLAY_END*/ | |
701 VGAOUT8(0x03D4, 0x12); | |
702 info->screen_y = VGAIN8(0x03D5); | |
703 VGAOUT8(0x03D4,0x07); | |
704 /* get 9th bit in CRTC_OVERFLOW*/ | |
705 info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; | |
706 /* and the 10th in CRTC_OVERFLOW*/ | |
707 info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; | |
708 ++info->screen_y; | |
709 | |
710 printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); | |
711 } | |
712 | |
713 | |
714 static void SavageStreamsOff(void) | |
715 { | |
716 unsigned char jStreamsControl; | |
717 unsigned short vgaCRIndex = 0x3d0 + 4; | |
718 unsigned short vgaCRReg = 0x3d0 + 5; | |
719 | |
720 | |
721 /* Unlock extended registers. */ | |
722 | |
723 VGAOUT16(vgaCRIndex, 0x4838); | |
724 VGAOUT16(vgaCRIndex, 0xa039); | |
725 VGAOUT16(0x3c4, 0x0608); | |
726 | |
727 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
728 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || | |
729 (info->chip.arch == S3_SUPERSAVAGE) || | |
730 (info->chip.arch == S3_SAVAGE2000) ) | |
731 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; | |
732 else | |
733 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; | |
734 | |
735 /* Wait for VBLANK. */ | |
736 | |
737 VerticalRetraceWait(); | |
738 | |
739 /* Kill streams. */ | |
740 | |
741 VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
742 | |
743 VGAOUT16(vgaCRIndex, 0x0093 ); | |
744 VGAOUT8( vgaCRIndex, 0x92 ); | |
745 VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); | |
746 | |
747 info->videoFlags &= ~VF_STREAMS_ON; | |
748 } | |
749 | |
750 /** | |
751 * @brief Find chip index in Unichrome compliant devices list. | |
752 * | |
753 * @param chip_id PCI device ID. | |
754 * | |
755 * @returns index position in savage_card_ids if successful. | |
756 * -1 if chip_id is not a compliant chipset ID. | |
757 */ | |
758 | |
759 static int find_chip(unsigned chip_id){ | |
760 unsigned i; | |
761 for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) | |
762 { | |
763 if(chip_id == savage_card_ids[i].chip_id)return i; | |
764 } | |
765 return -1; | |
766 } | |
767 | |
768 /** | |
769 * @brief Probe hardware to find some useable chipset. | |
770 * | |
771 * @param verbose specifies verbose level. | |
772 * @param force specifies force mode : driver should ignore | |
773 * device_id (danger but useful for new devices) | |
774 * | |
775 * @returns 0 if it can handle something in PC. | |
776 * a negative error code otherwise. | |
777 */ | |
778 | |
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779 static int savage_probe(int verbose, int force){ |
22850 | 780 pciinfo_t lst[MAX_PCI_DEVICES]; |
781 unsigned i,num_pci; | |
782 int err; | |
783 | |
784 if (force) | |
785 printf("[savage_vid]: warning: forcing not supported yet!\n"); | |
786 err = pci_scan(lst,&num_pci); | |
787 if(err){ | |
788 printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
789 return err; | |
790 } | |
791 else { | |
792 err = ENXIO; | |
793 for(i=0; i < num_pci; i++){ | |
794 if(lst[i].vendor == VENDOR_S3_INC) { | |
795 int idx; | |
796 const char *dname; | |
797 idx = find_chip(lst[i].device); | |
798 if(idx == -1) | |
799 continue; | |
800 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
801 dname = dname ? dname : "Unknown chip"; | |
802 printf("[savage_vid] Found chip: %s\n", dname); | |
803 // FIXME: whats wrong here? | |
804 if ((lst[i].command & PCI_COMMAND_IO ) == 0){ | |
805 printf("[savage_vid] Device is disabled, ignoring\n"); | |
806 continue; | |
807 } | |
808 savage_cap.device_id = lst[i].device; | |
809 err = 0; | |
810 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
811 break; | |
812 } | |
813 } | |
814 } | |
815 if(err && verbose) printf("[savage_vid] Can't find chip\n"); | |
816 return err; | |
817 } | |
818 | |
819 /** | |
820 * @brief Initializes driver. | |
821 * | |
822 * @returns 0 if ok. | |
823 * a negative error code otherwise. | |
824 */ | |
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825 static int |
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826 savage_init (void) |
22850 | 827 { |
828 int mtrr; | |
22868 | 829 unsigned char config1, tmp; |
22850 | 830 |
831 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; | |
832 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; | |
833 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; | |
834 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; | |
835 | |
22868 | 836 int videoRam; |
22850 | 837 |
838 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; | |
839 | |
840 unsigned char val; | |
841 | |
842 vgaIOBase = 0x3d0; | |
843 vgaCRIndex = vgaIOBase + 4; | |
844 vgaCRReg = vgaIOBase + 5; | |
845 | |
846 fprintf(stderr, "vixInit enter \n"); | |
847 // //getc(stdin); | |
848 | |
849 info = calloc(1,sizeof(savage_info)); | |
850 | |
851 | |
852 /* need this if we want direct outb and inb access? */ | |
853 enable_app_io (); | |
854 | |
855 /* 12mb + 32kb ? */ | |
856 /* allocate some space for control registers */ | |
857 info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; | |
858 | |
859 if (info->chip.arch == S3_SAVAGE3D) { | |
860 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); | |
861 } | |
862 else { | |
863 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); | |
864 } | |
865 | |
866 // info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); | |
867 | |
868 // FIXME: enable mmio? | |
869 val = VGAIN8 (0x3c3); | |
870 VGAOUT8 (0x3c3, val | 0x01); | |
871 val = VGAIN8 (0x3cc); | |
872 VGAOUT8 (0x3c2, val | 0x01); | |
873 | |
874 if (info->chip.arch >= S3_SAVAGE4) | |
875 { | |
876 VGAOUT8 (0x3d4, 0x40); | |
877 val = VGAIN8 (0x3d5); | |
878 VGAOUT8 (0x3d5, val | 1); | |
879 } | |
880 | |
881 | |
882 | |
883 /* unprotect CRTC[0-7] */ | |
884 VGAOUT8(vgaCRIndex, 0x11); | |
885 tmp = VGAIN8(vgaCRReg); | |
886 // printf("$########## tmp = %d\n",tmp); | |
887 VGAOUT8(vgaCRReg, tmp & 0x7f); | |
888 | |
889 | |
890 /* unlock extended regs */ | |
891 VGAOUT16(vgaCRIndex, 0x4838); | |
892 VGAOUT16(vgaCRIndex, 0xa039); | |
893 VGAOUT16(0x3c4, 0x0608); | |
894 | |
895 VGAOUT8(vgaCRIndex, 0x40); | |
896 tmp = VGAIN8(vgaCRReg); | |
897 VGAOUT8(vgaCRReg, tmp & ~0x01); | |
898 | |
899 /* unlock sys regs */ | |
900 VGAOUT8(vgaCRIndex, 0x38); | |
901 VGAOUT8(vgaCRReg, 0x48); | |
902 | |
903 /* Unlock system registers. */ | |
904 VGAOUT16(vgaCRIndex, 0x4838); | |
905 | |
906 /* Next go on to detect amount of installed ram */ | |
907 | |
908 VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ | |
909 config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ | |
910 | |
911 | |
912 switch( info->chip.arch ) { | |
913 case S3_SAVAGE3D: | |
914 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; | |
915 break; | |
916 | |
917 case S3_SAVAGE4: | |
918 /* | |
919 * The Savage4 has one ugly special case to consider. On | |
920 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB | |
921 * when it really means 8MB. Why do it the same when you | |
922 * can do it different... | |
923 */ | |
924 VGAOUT8(0x3d4, 0x68); /* memory control 1 */ | |
925 if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) | |
926 RamSavage4[1] = 8; | |
927 | |
928 /*FALLTHROUGH*/ | |
929 | |
930 case S3_SAVAGE2000: | |
931 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; | |
932 break; | |
933 | |
934 case S3_SAVAGE_MX: | |
935 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; | |
936 break; | |
937 | |
938 case S3_PROSAVAGE: | |
939 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; | |
940 break; | |
941 | |
942 default: | |
943 /* How did we get here? */ | |
944 videoRam = 0; | |
945 break; | |
946 } | |
947 | |
948 | |
949 printf("###### videoRam = %d\n",videoRam); | |
950 info->chip.fbsize = videoRam * 1024; | |
951 | |
952 | |
953 /* reset graphics engine to avoid memory corruption */ | |
954 /* VGAOUT8 (0x3d4, 0x66); | |
955 cr66 = VGAIN8 (0x3d5); | |
956 VGAOUT8 (0x3d5, cr66 | 0x02); | |
957 udelay (10000); | |
958 | |
959 VGAOUT8 (0x3d4, 0x66); | |
22868 | 960 VGAOUT8 (0x3d5, cr66 & ~0x02); */ // clear reset flag |
22850 | 961 /* udelay (10000); */ |
962 | |
963 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
964 if (info->chip.arch == S3_SAVAGE3D) { | |
965 info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); | |
966 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
967 } | |
968 else { | |
969 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
970 info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; | |
971 // info->picture_offset = 1024*1024* 4 * 2; | |
972 } | |
22868 | 973 if ( info->video_base == NULL){ |
22850 | 974 printf("errno = %s\n", strerror(errno)); |
975 return -1; | |
976 } | |
977 | |
978 | |
979 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
980 | |
981 if ( info->chip.arch == S3_SAVAGE3D ){ | |
982 mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
983 } | |
984 else{ | |
985 mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
986 } | |
987 | |
988 if (mtrr!= 0) | |
989 printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
990 else | |
991 printf("[savage_vid] MTRR set up\n"); | |
992 | |
993 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
994 | |
995 | |
996 savage_getscreenproperties(info); | |
997 // return -1; | |
998 info->videoFlags = 0; | |
999 | |
1000 SavageStreamsOn(); | |
1001 //getc(stdin); | |
1002 //FIXME ADD | |
1003 return 0; | |
1004 } | |
1005 | |
1006 /** | |
1007 * @brief Destroys driver. | |
1008 */ | |
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1009 static void |
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1010 savage_destroy (void) |
22850 | 1011 { |
1012 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
1013 unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); | |
1014 //FIXME ADD | |
1015 } | |
1016 | |
1017 /** | |
1018 * @brief Get chipset's hardware capabilities. | |
1019 * | |
1020 * @param to Pointer to the vidix_capability_t structure to be filled. | |
1021 * | |
1022 * @returns 0. | |
1023 */ | |
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1024 static int |
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1025 savage_get_caps (vidix_capability_t * to) |
22850 | 1026 { |
1027 memcpy (to, &savage_cap, sizeof (vidix_capability_t)); | |
1028 return 0; | |
1029 } | |
1030 | |
1031 /** | |
1032 * @brief Report if the video FourCC is supported by hardware. | |
1033 * | |
1034 * @param fourcc input image format. | |
1035 * | |
1036 * @returns 1 if the fourcc is supported. | |
1037 * 0 otherwise. | |
1038 */ | |
1039 static int | |
1040 is_supported_fourcc (uint32_t fourcc) | |
1041 { | |
1042 switch (fourcc) | |
1043 { | |
1044 //FIXME: YV12 isnt working properly yet | |
1045 // case IMGFMT_YV12: | |
1046 // case IMGFMT_I420: | |
1047 case IMGFMT_UYVY: | |
1048 case IMGFMT_YVYU: | |
1049 case IMGFMT_YUY2: | |
1050 case IMGFMT_RGB15: | |
1051 case IMGFMT_RGB16: | |
1052 // case IMGFMT_BGR32: | |
1053 return 1; | |
1054 default: | |
1055 return 0; | |
1056 } | |
1057 } | |
1058 | |
1059 /** | |
1060 * @brief Try to configure video memory for given fourcc. | |
1061 * | |
1062 * @param to Pointer to the vidix_fourcc_t structure to be filled. | |
1063 * | |
1064 * @returns 0 if ok. | |
1065 * errno otherwise. | |
1066 */ | |
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1067 static int |
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1068 savage_query_fourcc (vidix_fourcc_t * to) |
22850 | 1069 { |
1070 if (is_supported_fourcc (to->fourcc)) | |
1071 { | |
1072 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1073 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1074 VID_DEPTH_12BPP | VID_DEPTH_15BPP | | |
1075 VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; | |
1076 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
1077 return 0; | |
1078 } | |
1079 else | |
1080 to->depth = to->flags = 0; | |
1081 | |
1082 return ENOSYS; | |
1083 } | |
1084 | |
1085 /** | |
1086 * @brief Get the GrKeys | |
1087 * | |
1088 * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. | |
1089 * | |
1090 * @return 0. | |
1091 */ | |
1092 /*int | |
1093 vixGetGrKeys (vidix_grkey_t * grkey) | |
1094 { | |
1095 | |
1096 // if(info->d_width && info->d_height)savage_overlay_start(info,0); | |
1097 | |
1098 return (0); | |
1099 } | |
1100 * */ | |
1101 | |
1102 /** | |
1103 * @brief Set the GrKeys | |
1104 * | |
1105 * @param grkey Colorkey to be set. | |
1106 * | |
1107 * @return 0. | |
1108 */ | |
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1109 static int |
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1110 savage_set_gkeys (const vidix_grkey_t * grkey) |
22850 | 1111 { |
1112 if (grkey->ckey.op == CKEY_FALSE) | |
1113 { | |
1114 info->use_colorkey = 0; | |
1115 info->vidixcolorkey=0; | |
1116 printf("[savage_vid] colorkeying disabled\n"); | |
1117 } | |
1118 else { | |
1119 info->use_colorkey = 1; | |
1120 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1121 | |
1122 printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1123 } | |
1124 //FIXME: freezes if streams arent enabled | |
1125 SavageSetColorKeyOld(); | |
1126 return (0); | |
1127 } | |
1128 | |
1129 /** | |
1130 * @brief Unichrome driver equalizer capabilities. | |
1131 */ | |
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1132 static vidix_video_eq_t equal = { |
22850 | 1133 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, |
1134 300, 100, 0, 0, 0, 0, 0, 0 | |
1135 }; | |
1136 | |
1137 | |
1138 /** | |
1139 * @brief Get the equalizer capabilities. | |
1140 * | |
1141 * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. | |
1142 * | |
1143 * @return 0. | |
1144 */ | |
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1145 static int |
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1146 savage_get_eq (vidix_video_eq_t * eq) |
22850 | 1147 { |
1148 memcpy (eq, &equal, sizeof (vidix_video_eq_t)); | |
1149 return 0; | |
1150 } | |
1151 | |
1152 /** | |
1153 * @brief Set the equalizer capabilities for color correction | |
1154 * | |
1155 * @param eq equalizer capabilities to be set. | |
1156 * | |
1157 * @return 0. | |
1158 */ | |
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1159 static int |
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1160 savage_set_eq (const vidix_video_eq_t * eq) |
22850 | 1161 { |
1162 return 0; | |
1163 } | |
1164 | |
1165 /** | |
1166 * @brief Configure driver for playback. Driver should prepare BES. | |
1167 * | |
1168 * @param info configuration description for playback. | |
1169 * | |
1170 * @returns 0 in case of success. | |
1171 * -1 otherwise. | |
1172 */ | |
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1173 static int |
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1174 savage_config_playback (vidix_playback_t * vinfo) |
22850 | 1175 { |
1176 int uv_size, swap_uv; | |
1177 unsigned int i; | |
1178 | |
1179 if (!is_supported_fourcc (vinfo->fourcc)) | |
1180 return -1; | |
1181 | |
1182 | |
1183 | |
1184 info->src_w = vinfo->src.w; | |
1185 info->src_h = vinfo->src.h; | |
1186 | |
1187 info->drw_w = vinfo->dest.w; | |
1188 info->drw_h = vinfo->dest.h; | |
1189 | |
1190 info->wx = vinfo->dest.x; | |
1191 info->wy = vinfo->dest.y; | |
1192 info->format = vinfo->fourcc; | |
1193 | |
1194 info->lastKnownPitch = 0; | |
1195 info->brightness = 0; | |
1196 info->contrast = 128; | |
1197 info->saturation = 128; | |
1198 info->hue = 0; | |
1199 | |
1200 | |
1201 vinfo->dga_addr=(void*)(info->picture_base); | |
1202 | |
1203 | |
1204 vinfo->offset.y = 0; | |
1205 vinfo->offset.v = 0; | |
1206 vinfo->offset.u = 0; | |
1207 | |
1208 vinfo->dest.pitch.y = 32; | |
1209 vinfo->dest.pitch.u = 32; | |
1210 vinfo->dest.pitch.v = 32; | |
1211 // vinfo->dest.pitch.u = 0; | |
1212 // vinfo->dest.pitch.v = 0; | |
1213 | |
1214 | |
1215 info->pitch = ((info->src_w << 1) + 15) & ~15; | |
1216 | |
1217 swap_uv = 0; | |
1218 switch (vinfo->fourcc) | |
1219 { | |
1220 case IMGFMT_YUY2: | |
1221 case IMGFMT_UYVY: | |
1222 | |
1223 info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1224 | |
1225 info->pitch = info->src_w << 1; | |
1226 info->pitch = ALIGN_TO (info->src_w << 1, 32); | |
1227 uv_size = 0; | |
1228 break; | |
1229 case IMGFMT_YV12: | |
1230 swap_uv = 1; | |
1231 | |
1232 | |
1233 | |
1234 /* | |
1235 srcPitch = (info->src_w + 3) & ~3; | |
1236 vinfo->offset.u = srcPitch * info->src_h; | |
1237 srcPitch2 = ((info->src_w >> 1) + 3) & ~3; | |
1238 vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; | |
1239 | |
1240 vinfo->dest.pitch.y=srcPitch ; | |
1241 vinfo->dest.pitch.v=srcPitch2 ; | |
1242 vinfo->dest.pitch.u=srcPitch2 ; | |
1243 */ | |
1244 | |
1245 | |
1246 info->pitch = ALIGN_TO (info->src_w, 32); | |
1247 uv_size = (info->pitch >> 1) * (info->src_h >> 1); | |
1248 | |
1249 vinfo->offset.y = 0; | |
1250 vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; | |
1251 vinfo->offset.u = vinfo->offset.v + uv_size; | |
1252 vinfo->frame_size = vinfo->offset.u + uv_size; | |
1253 /* YOffs = info->offset.y; | |
1254 UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); | |
1255 VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); | |
1256 */ | |
1257 // vinfo->offset.y = info->src_w; | |
1258 // vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; | |
1259 // vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; | |
1260 | |
1261 break; | |
1262 } | |
1263 info->pitch |= ((info->pitch >> 1) << 16); | |
1264 | |
1265 vinfo->frame_size = info->pitch * info->src_h; | |
1266 | |
1267 printf("$#### destination pitch = %u\n", info->pitch&0xffff); | |
1268 | |
1269 | |
1270 | |
1271 | |
1272 info->buffer_size = vinfo->frame_size; | |
1273 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1274 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1275 // vinfo->num_frames = 1; | |
1276 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1277 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1278 | |
1279 return 0; | |
1280 } | |
1281 | |
1282 /** | |
1283 * @brief Set playback on : driver should activate BES on this call. | |
1284 * | |
1285 * @return 0. | |
1286 */ | |
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1287 static int |
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1288 savage_playback_on (void) |
22850 | 1289 { |
1290 // FIXME: enable | |
1291 SavageDisplayVideoOld(); | |
1292 //FIXME ADD | |
1293 return 0; | |
1294 } | |
1295 | |
1296 /** | |
1297 * @brief Set playback off : driver should deactivate BES on this call. | |
1298 * | |
1299 * @return 0. | |
1300 */ | |
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1301 static int |
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1302 savage_playback_off (void) |
22850 | 1303 { |
1304 // otherwise we wont disable streams properly in new xorg | |
1305 // FIXME: shouldnt this be enabled? | |
1306 // SavageStreamsOn(); | |
1307 SavageStreamsOff(); | |
1308 // info->vidixcolorkey=0x0; | |
1309 | |
1310 // OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
1311 // SavageSetColorKeyOld(); | |
1312 //FIXME ADD | |
1313 return 0; | |
1314 } | |
1315 | |
23057 | 1316 static void debugout(unsigned int addr, unsigned int val){ |
22850 | 1317 return ; |
1318 switch ( addr ){ | |
1319 case PSTREAM_CONTROL_REG: | |
1320 fprintf(stderr,"PSTREAM_CONTROL_REG"); | |
1321 break; | |
1322 case COL_CHROMA_KEY_CONTROL_REG: | |
1323 fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); | |
1324 break; | |
1325 case SSTREAM_CONTROL_REG: | |
1326 fprintf(stderr,"SSTREAM_CONTROL_REG"); | |
1327 break; | |
1328 case CHROMA_KEY_UPPER_BOUND_REG: | |
1329 fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); | |
1330 break; | |
1331 case SSTREAM_STRETCH_REG: | |
1332 fprintf(stderr,"SSTREAM_STRETCH_REG"); | |
1333 break; | |
1334 case COLOR_ADJUSTMENT_REG: | |
1335 fprintf(stderr,"COLOR_ADJUSTMENT_REG"); | |
1336 break; | |
1337 case BLEND_CONTROL_REG: | |
1338 fprintf(stderr,"BLEND_CONTROL_REG"); | |
1339 break; | |
1340 case PSTREAM_FBADDR0_REG: | |
1341 fprintf(stderr,"PSTREAM_FBADDR0_REG"); | |
1342 break; | |
1343 case PSTREAM_FBADDR1_REG: | |
1344 fprintf(stderr,"PSTREAM_FBADDR1_REG"); | |
1345 break; | |
1346 case PSTREAM_STRIDE_REG: | |
1347 fprintf(stderr,"PSTREAM_STRIDE_REG"); | |
1348 break; | |
1349 case DOUBLE_BUFFER_REG: | |
1350 fprintf(stderr,"DOUBLE_BUFFER_REG"); | |
1351 break; | |
1352 case SSTREAM_FBADDR0_REG: | |
1353 fprintf(stderr,"SSTREAM_FBADDR0_REG"); | |
1354 break; | |
1355 case SSTREAM_FBADDR1_REG: | |
1356 fprintf(stderr,"SSTREAM_FBADDR1_REG"); | |
1357 break; | |
1358 case SSTREAM_STRIDE_REG: | |
1359 fprintf(stderr,"SSTREAM_STRIDE_REG"); | |
1360 break; | |
1361 case SSTREAM_VSCALE_REG: | |
1362 fprintf(stderr,"SSTREAM_VSCALE_REG"); | |
1363 break; | |
1364 case SSTREAM_VINITIAL_REG: | |
1365 fprintf(stderr,"SSTREAM_VINITIAL_REG"); | |
1366 break; | |
1367 case SSTREAM_LINES_REG: | |
1368 fprintf(stderr,"SSTREAM_LINES_REG"); | |
1369 break; | |
1370 case STREAMS_FIFO_REG: | |
1371 fprintf(stderr,"STREAMS_FIFO_REG"); | |
1372 break; | |
1373 case PSTREAM_WINDOW_START_REG: | |
1374 fprintf(stderr,"PSTREAM_WINDOW_START_REG"); | |
1375 break; | |
1376 case PSTREAM_WINDOW_SIZE_REG: | |
1377 fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); | |
1378 break; | |
1379 case SSTREAM_WINDOW_START_REG: | |
1380 fprintf(stderr,"SSTREAM_WINDOW_START_REG"); | |
1381 break; | |
1382 case SSTREAM_WINDOW_SIZE_REG: | |
1383 fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); | |
1384 break; | |
1385 case FIFO_CONTROL: | |
1386 fprintf(stderr,"FIFO_CONTROL"); | |
1387 break; | |
1388 case PSTREAM_FBSIZE_REG: | |
1389 fprintf(stderr,"PSTREAM_FBSIZE_REG"); | |
1390 break; | |
1391 case SSTREAM_FBSIZE_REG: | |
1392 fprintf(stderr,"SSTREAM_FBSIZE_REG"); | |
1393 break; | |
1394 case SSTREAM_FBADDR2_REG: | |
1395 fprintf(stderr,"SSTREAM_FBADDR2_REG"); | |
1396 break; | |
1397 | |
1398 } | |
1399 fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); | |
1400 } | |
1401 | |
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1402 VDXDriver savage_drv = { |
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1403 "savage", |
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1404 NULL, |
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1405 .probe = savage_probe, |
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1406 .get_caps = savage_get_caps, |
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1407 .query_fourcc = savage_query_fourcc, |
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1408 .init = savage_init, |
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1409 .destroy = savage_destroy, |
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1410 .config_playback = savage_config_playback, |
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1411 .playback_on = savage_playback_on, |
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1412 .playback_off = savage_playback_off, |
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1413 .get_eq = savage_get_eq, |
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1414 .set_eq = savage_set_eq, |
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1415 .set_gkey = savage_set_gkeys, |
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1416 }; |