annotate cpudetect.c @ 5681:4efb8ab109b8

vo_mouse_timer_const is optional
author arpi
date Thu, 18 Apr 2002 16:16:14 +0000
parents 35ed5387b804
children 4b18bf35f153
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1 #include "config.h"
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2 #include "cpudetect.h"
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3
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4 CpuCaps gCpuCaps;
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5
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6 #ifdef HAVE_MALLOC_H
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7 #include <malloc.h>
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8 #endif
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9 #include <stdlib.h>
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10
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11 #ifdef ARCH_X86
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12
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13 #include <stdio.h>
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14
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15 #ifdef __FreeBSD__
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16 #include <sys/types.h>
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17 #include <sys/sysctl.h>
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18 #endif
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19
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20 #ifdef __linux__
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21 #include <signal.h>
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22 #endif
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23
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24 //#define X86_FXSR_MAGIC
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25 /* Thanks to the FreeBSD project for some of this cpuid code, and
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26 * help understanding how to use it. Thanks to the Mesa
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27 * team for SSE support detection and more cpu detect code.
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28 */
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29
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30 /* I believe this code works. However, it has only been used on a PII and PIII */
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31
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32 static void check_os_katmai_support( void );
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33
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34 #if 1
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35 // return TRUE if cpuid supported
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36 static int has_cpuid()
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37 {
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38 int a, c;
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39
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40 // code from libavcodec:
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41 __asm__ __volatile__ (
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42 /* See if CPUID instruction is supported ... */
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43 /* ... Get copies of EFLAGS into eax and ecx */
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44 "pushf\n\t"
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45 "popl %0\n\t"
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46 "movl %0, %1\n\t"
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47
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48 /* ... Toggle the ID bit in one copy and store */
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49 /* to the EFLAGS reg */
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50 "xorl $0x200000, %0\n\t"
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51 "push %0\n\t"
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52 "popf\n\t"
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53
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54 /* ... Get the (hopefully modified) EFLAGS */
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55 "pushf\n\t"
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56 "popl %0\n\t"
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57 : "=a" (a), "=c" (c)
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58 :
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59 : "cc"
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60 );
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61
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62 return (a!=c);
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63 }
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64 #endif
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65
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66 static void
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67 do_cpuid(unsigned int ax, unsigned int *p)
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68 {
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69 #if 0
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70 __asm __volatile(
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71 "cpuid;"
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72 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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73 : "0" (ax)
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74 );
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75 #else
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76 // code from libavcodec:
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77 __asm __volatile
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78 ("movl %%ebx, %%esi\n\t"
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79 "cpuid\n\t"
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80 "xchgl %%ebx, %%esi"
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81 : "=a" (p[0]), "=S" (p[1]),
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82 "=c" (p[2]), "=d" (p[3])
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83 : "0" (ax));
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84 #endif
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85
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86 }
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87
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88 void GetCpuCaps( CpuCaps *caps)
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89 {
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90 unsigned int regs[4];
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91 unsigned int regs2[4];
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92
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93 caps->isX86=1;
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94
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95 memset(caps, 0, sizeof(*caps));
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96 if (!has_cpuid()) {
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97 printf("CPUID not supported!???\n");
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98 return;
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99 }
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100 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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101 printf("CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
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102 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
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103 if (regs[0]>=0x00000001)
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104 {
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105 char *tmpstr;
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106
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107 do_cpuid(0x00000001, regs2);
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108
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109 tmpstr=GetCpuFriendlyName(regs, regs2);
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110 printf("CPU: %s ",tmpstr);
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111 free(tmpstr);
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112
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113 caps->cpuType=(regs2[0] >> 8)&0xf;
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114 if(caps->cpuType==0xf){
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115 // use extended family (P4, IA64)
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116 caps->cpuType=8+((regs2[0]>>20)&255);
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117 }
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118 caps->cpuStepping=regs2[0] & 0xf;
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119 printf("(Type: %d, Stepping: %d)\n",
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120 caps->cpuType, caps->cpuStepping);
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121
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122 // general feature flags:
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123 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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124 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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125 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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126 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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127 }
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128 do_cpuid(0x80000000, regs);
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129 if (regs[0]>=0x80000001) {
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130 printf("extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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131 do_cpuid(0x80000001, regs2);
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132 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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133 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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134 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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135 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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136 }
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137 #if 0
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138 printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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139 gCpuCaps.hasMMX,
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140 gCpuCaps.hasMMX2,
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141 gCpuCaps.hasSSE,
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142 gCpuCaps.hasSSE2,
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143 gCpuCaps.has3DNow,
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144 gCpuCaps.has3DNowExt );
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145 #endif
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146
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147 /* FIXME: Does SSE2 need more OS support, too? */
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148 #if defined(__linux__) || defined(__FreeBSD__)
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149 if (caps->hasSSE)
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150 check_os_katmai_support();
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151 if (!caps->hasSSE)
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152 caps->hasSSE2 = 0;
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153 #else
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154 caps->hasSSE=0;
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155 caps->hasSSE2 = 0;
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156 #endif
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157 // caps->has3DNow=1;
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158 // caps->hasMMX2 = 0;
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159 // caps->hasMMX = 0;
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160
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161 #ifndef HAVE_MMX
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162 if(caps->hasMMX) printf("MMX supported but disabled\n");
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163 caps->hasMMX=0;
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164 #endif
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165 #ifndef HAVE_MMX2
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166 if(caps->hasMMX2) printf("MMX2 supported but disabled\n");
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167 caps->hasMMX2=0;
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168 #endif
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169 #ifndef HAVE_SSE
35ed5387b804 dont ignore --disable-mmx, ...
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170 if(caps->hasSSE) printf("SSE supported but disabled\n");
35ed5387b804 dont ignore --disable-mmx, ...
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171 caps->hasSSE=0;
35ed5387b804 dont ignore --disable-mmx, ...
michael
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172 #endif
35ed5387b804 dont ignore --disable-mmx, ...
michael
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173 #ifndef HAVE_SSE2
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174 if(caps->hasSSE2) printf("SSE2 supported but disabled\n");
35ed5387b804 dont ignore --disable-mmx, ...
michael
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175 caps->hasSSE2=0;
35ed5387b804 dont ignore --disable-mmx, ...
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176 #endif
35ed5387b804 dont ignore --disable-mmx, ...
michael
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177 #ifndef HAVE_3DNOW
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178 if(caps->has3DNow) printf("3DNow supported but disabled\n");
35ed5387b804 dont ignore --disable-mmx, ...
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179 caps->has3DNow=0;
35ed5387b804 dont ignore --disable-mmx, ...
michael
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180 #endif
35ed5387b804 dont ignore --disable-mmx, ...
michael
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181 #ifndef HAVE_3DNOWEX
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182 if(caps->has3DNowExt) printf("3DNowExt supported but disabled\n");
35ed5387b804 dont ignore --disable-mmx, ...
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183 caps->has3DNowExt=0;
35ed5387b804 dont ignore --disable-mmx, ...
michael
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184 #endif
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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185 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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186
2301
b4c4c832cce7 Detect and show cpu name.
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187
b4c4c832cce7 Detect and show cpu name.
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188 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
b4c4c832cce7 Detect and show cpu name.
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189 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
b4c4c832cce7 Detect and show cpu name.
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190 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
b4c4c832cce7 Detect and show cpu name.
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191 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
b4c4c832cce7 Detect and show cpu name.
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192 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
b4c4c832cce7 Detect and show cpu name.
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193 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
b4c4c832cce7 Detect and show cpu name.
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194
b4c4c832cce7 Detect and show cpu name.
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195 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
b4c4c832cce7 Detect and show cpu name.
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196 #include "cputable.h" /* get cpuname and cpuvendors */
b4c4c832cce7 Detect and show cpu name.
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197 char vendor[17];
2303
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198 char *retname;
2301
b4c4c832cce7 Detect and show cpu name.
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199 int i;
b4c4c832cce7 Detect and show cpu name.
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200
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6b4952e00ad0 removed warning
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201 if (NULL==(retname=(char*)malloc(256))) {
2303
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202 printf("Error: GetCpuFriendlyName() not enough memory\n");
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203 exit(1);
456e22bfb147 returns a malloc()'ed string instead of an auto char[]
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204 }
456e22bfb147 returns a malloc()'ed string instead of an auto char[]
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205
3837
6659db99f200 warning fix
pl
parents: 3700
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206 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
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207
2301
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208 for(i=0; i<MAX_VENDORS; i++){
b4c4c832cce7 Detect and show cpu name.
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209 if(!strcmp(cpuvendors[i].string,vendor)){
b4c4c832cce7 Detect and show cpu name.
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210 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
2303
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parents: 2301
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211 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
2301
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212 } else {
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213 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
2301
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214 printf("unknown %s CPU:\n",cpuvendors[i].name);
b4c4c832cce7 Detect and show cpu name.
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215 printf("Vendor: %s\n",cpuvendors[i].string);
b4c4c832cce7 Detect and show cpu name.
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216 printf("Type: %d\n",CPUID_TYPE);
b4c4c832cce7 Detect and show cpu name.
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217 printf("Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
b4c4c832cce7 Detect and show cpu name.
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218 printf("Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
b4c4c832cce7 Detect and show cpu name.
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219 printf("Stepping: %d\n",CPUID_STEPPING);
b4c4c832cce7 Detect and show cpu name.
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220 printf("Please send the above info along with the exact CPU name"
b4c4c832cce7 Detect and show cpu name.
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221 "to the MPlayer-Developers, so we can add it to the list!\n");
b4c4c832cce7 Detect and show cpu name.
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222 }
b4c4c832cce7 Detect and show cpu name.
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223 }
b4c4c832cce7 Detect and show cpu name.
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224 }
b4c4c832cce7 Detect and show cpu name.
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225
b4c4c832cce7 Detect and show cpu name.
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226 //printf("Detected CPU: %s\n", retname);
b4c4c832cce7 Detect and show cpu name.
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227 return retname;
b4c4c832cce7 Detect and show cpu name.
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228 }
b4c4c832cce7 Detect and show cpu name.
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229
b4c4c832cce7 Detect and show cpu name.
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230 #undef CPUID_EXTFAMILY
b4c4c832cce7 Detect and show cpu name.
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231 #undef CPUID_EXTMODEL
b4c4c832cce7 Detect and show cpu name.
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232 #undef CPUID_TYPE
b4c4c832cce7 Detect and show cpu name.
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233 #undef CPUID_FAMILY
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234 #undef CPUID_MODEL
b4c4c832cce7 Detect and show cpu name.
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235 #undef CPUID_STEPPING
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236
b4c4c832cce7 Detect and show cpu name.
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237
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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238 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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239 static void sigill_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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240 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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241 printf( "SIGILL, " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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242
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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243 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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244 * instructions are 3 bytes long. We must increment the instruction
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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245 * pointer manually to avoid repeated execution of the offending
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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246 * instruction.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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247 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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248 * If the SIGILL is caused by a divide-by-zero when unmasked
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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249 * exceptions aren't supported, the SIMD FPU status and control
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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250 * word will be restored at the end of the test, so we don't need
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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251 * to worry about doing it here. Besides, we may not be able to...
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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252 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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253 sc.eip += 3;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
254
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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255 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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256 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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257
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
258 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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259 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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260 printf( "SIGFPE, " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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261
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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262 if ( sc.fpstate->magic != 0xffff ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
263 /* Our signal context has the extended FPU state, so reset the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
264 * divide-by-zero exception mask and clear the divide-by-zero
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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265 * exception bit.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
266 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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267 sc.fpstate->mxcsr |= 0x00000200;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
268 sc.fpstate->mxcsr &= 0xfffffffb;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
269 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
270 /* If we ever get here, we're completely hosed.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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271 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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272 printf( "\n\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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273 printf( "SSE enabling test failed badly!" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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274 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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275 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
276 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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277
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
278 /* If we're running on a processor that can do SSE, let's see if we
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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279 * are allowed to or not. This will catch 2.4.0 or later kernels that
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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280 * haven't been configured for a Pentium III but are running on one,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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281 * and RedHat patched 2.2 kernels that have broken exception handling
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
282 * support for user space apps that do SSE.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
283 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
284 static void check_os_katmai_support( void )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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285 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
286 #if defined(__FreeBSD__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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287 int has_sse=0, ret;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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288 size_t len=sizeof(has_sse);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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289
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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290 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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291 if (ret || !has_sse)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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292 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
293
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
294 #elif defined(__linux__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
295 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
296 struct sigaction saved_sigill;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
297 struct sigaction saved_sigfpe;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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298
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
299 /* Save the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
300 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
301 sigaction( SIGILL, NULL, &saved_sigill );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
302 sigaction( SIGFPE, NULL, &saved_sigfpe );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
303
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
304 signal( SIGILL, (void (*)(int))sigill_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
305 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
306
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
307 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
308 * supports the extended FPU save and restore required for SSE. If
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
309 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
310 * doesn't support Streaming SIMD Exceptions, even if the processor
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
311 * does.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
312 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
313 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
314 printf( "Testing OS support for SSE... " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
315
2272
c26a9eff0993 cpu detection fixed
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diff changeset
316 // __asm __volatile ("xorps %%xmm0, %%xmm0");
c26a9eff0993 cpu detection fixed
arpi
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diff changeset
317 __asm __volatile ("xorps %xmm0, %xmm0");
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
318
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
319 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
320 printf( "yes.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
321 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
322 printf( "no!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
323 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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324 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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325
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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326 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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327 * it supports unmasked SIMD FPU exceptions. If we unmask the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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328 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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329 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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330 * as expected, we're okay but we need to clean up after it.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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331 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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332 * Are we being too stringent in our requirement that the OS support
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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333 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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334 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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335 * doesn't even support them. We at least know the user-space SSE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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336 * support is good in kernels that do support unmasked exceptions,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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337 * and therefore to be safe I'm going to leave this test in here.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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338 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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339 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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340 printf( "Testing OS support for SSE unmasked exceptions... " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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341
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c26a9eff0993 cpu detection fixed
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342 // test_os_katmai_exception_support();
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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343
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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344 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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345 printf( "yes.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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346 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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347 printf( "no!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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348 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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349 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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350
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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351 /* Restore the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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352 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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353 sigaction( SIGILL, &saved_sigill, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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354 sigaction( SIGFPE, &saved_sigfpe, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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355
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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356 /* If we've gotten to here and the XMM CPUID bit is still set, we're
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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357 * safe to go ahead and hook out the SSE code throughout Mesa.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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358 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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359 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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360 printf( "Tests of OS support for SSE passed.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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361 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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362 printf( "Tests of OS support for SSE failed!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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363 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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364 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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365 /* We can't use POSIX signal handling to test the availability of
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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366 * SSE, so we disable it by default.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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367 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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368 printf( "Cannot test OS support for SSE, disabling to be safe.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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369 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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370 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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371 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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372 /* Do nothing on other platforms for now.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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373 */
3850
ca9cc0aaacc7 fix for qnx
alex
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374 printf( "Not testing OS support for SSE, leaving disabled.\n" );
2268
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arpi
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375 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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376 #endif /* __linux__ */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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377 }
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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378 #else /* ARCH_X86 */
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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379
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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380 void GetCpuCaps( CpuCaps *caps)
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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381 {
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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382 caps->cpuType=0;
3403
c4ca766a2d05 added cpuStepping to CpuCaps struct (needed win32.c)
alex
parents: 3146
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383 caps->cpuStepping=0;
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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384 caps->hasMMX=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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385 caps->hasMMX2=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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386 caps->has3DNow=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
387 caps->has3DNowExt=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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388 caps->hasSSE=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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389 caps->hasSSE2=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
390 caps->isX86=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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391 }
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
392 #endif /* !ARCH_X86 */