annotate cpudetect.c @ 2288:dac462a0ac8c

final fix?
author arpi
date Fri, 19 Oct 2001 14:02:12 +0000
parents 0c5fea3a0b91
children b4c4c832cce7
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1 #include "config.h"
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2 #include "cpudetect.h"
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3
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4 #ifdef ARCH_X86
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5
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6 #include <stdio.h>
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7
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8 #ifdef __FreeBSD__
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9 #include <sys/types.h>
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10 #include <sys/sysctl.h>
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11 #endif
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12
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13 #ifdef __linux__
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14 #include <signal.h>
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15 #endif
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16
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17 //#define X86_FXSR_MAGIC
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18 /* Thanks to the FreeBSD project for some of this cpuid code, and
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19 * help understanding how to use it. Thanks to the Mesa
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20 * team for SSE support detection and more cpu detect code.
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21 */
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22
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23 /* I believe this code works. However, it has only been used on a PII and PIII */
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24
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25 CpuCaps gCpuCaps;
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26 static void check_os_katmai_support( void );
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27
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28 #if 1
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29 // return TRUE if cpuid supported
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30 static int has_cpuid()
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31 {
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32 int a, c;
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33
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34 // code from libavcodec:
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35 __asm__ __volatile__ (
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36 /* See if CPUID instruction is supported ... */
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37 /* ... Get copies of EFLAGS into eax and ecx */
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38 "pushf\n\t"
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39 "popl %0\n\t"
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40 "movl %0, %1\n\t"
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41
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42 /* ... Toggle the ID bit in one copy and store */
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43 /* to the EFLAGS reg */
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44 "xorl $0x200000, %0\n\t"
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45 "push %0\n\t"
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46 "popf\n\t"
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47
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48 /* ... Get the (hopefully modified) EFLAGS */
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49 "pushf\n\t"
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50 "popl %0\n\t"
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51 : "=a" (a), "=c" (c)
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52 :
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53 : "cc"
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54 );
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55
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56 return (a!=c);
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57 }
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58 #endif
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59
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60 static void
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61 do_cpuid(unsigned int ax, unsigned int *p)
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62 {
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63 #if 0
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64 __asm __volatile(
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65 "cpuid;"
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66 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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67 : "0" (ax)
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68 );
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69 #else
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70 // code from libavcodec:
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71 __asm __volatile
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72 ("movl %%ebx, %%esi\n\t"
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73 "cpuid\n\t"
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74 "xchgl %%ebx, %%esi"
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75 : "=a" (p[0]), "=S" (p[1]),
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76 "=c" (p[2]), "=d" (p[3])
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77 : "0" (ax));
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78 #endif
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79
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80 }
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81
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82
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83 void GetCpuCaps( CpuCaps *caps)
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84 {
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85 unsigned int regs[4];
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86 unsigned int regs2[4];
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87
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88 bzero(caps, sizeof(*caps));
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89 if (!has_cpuid()) {
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90 printf("CPUID not supported!???\n");
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91 return;
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92 }
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93 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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94 printf("CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",&regs[1],&regs[3],&regs[2],regs[0]);
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95 if (regs[0]>=0x00000001)
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96 {
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97 do_cpuid(0x00000001, regs2);
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98 caps->cpuType=(regs2[0] >> 8)&0xf;
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99 if(caps->cpuType==0xf){
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100 // use extended family (P4, IA64)
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101 caps->cpuType=8+((regs2[0]>>20)&255);
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102 }
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103
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104 // general feature flags:
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105 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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106 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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107 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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108 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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109 }
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110 do_cpuid(0x80000000, regs);
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111 if (regs[0]>=0x80000001) {
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112 printf("extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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113 do_cpuid(0x80000001, regs2);
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114 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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115 caps->hasMMX2 = (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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116 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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117 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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118 }
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119 #if 0
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120 printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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121 gCpuCaps.hasMMX,
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122 gCpuCaps.hasMMX2,
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123 gCpuCaps.hasSSE,
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124 gCpuCaps.hasSSE2,
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125 gCpuCaps.has3DNow,
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126 gCpuCaps.has3DNowExt );
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127 #endif
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128
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129 /* FIXME: Does SSE2 need more OS support, too? */
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130 #if defined(__linux__) || defined(__FreeBSD__)
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131 if (caps->hasSSE)
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132 check_os_katmai_support();
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133 if (!caps->hasSSE)
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134 caps->hasSSE2 = 0;
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135 #else
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136 caps->hasSSE=0;
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137 caps->hasSSE2 = 0;
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138 #endif
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139
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140
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141 }
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142
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143 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
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144 static void sigill_handler_sse( int signal, struct sigcontext sc )
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145 {
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146 printf( "SIGILL, " );
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147
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148 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
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149 * instructions are 3 bytes long. We must increment the instruction
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150 * pointer manually to avoid repeated execution of the offending
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151 * instruction.
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152 *
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153 * If the SIGILL is caused by a divide-by-zero when unmasked
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154 * exceptions aren't supported, the SIMD FPU status and control
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155 * word will be restored at the end of the test, so we don't need
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156 * to worry about doing it here. Besides, we may not be able to...
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157 */
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158 sc.eip += 3;
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159
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160 gCpuCaps.hasSSE=0;
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161 }
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162
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163 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
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164 {
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165 printf( "SIGFPE, " );
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166
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167 if ( sc.fpstate->magic != 0xffff ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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168 /* Our signal context has the extended FPU state, so reset the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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169 * divide-by-zero exception mask and clear the divide-by-zero
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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170 * exception bit.
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171 */
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172 sc.fpstate->mxcsr |= 0x00000200;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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173 sc.fpstate->mxcsr &= 0xfffffffb;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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174 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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175 /* If we ever get here, we're completely hosed.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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176 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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177 printf( "\n\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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178 printf( "SSE enabling test failed badly!" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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179 }
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180 }
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181 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
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182
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183 /* If we're running on a processor that can do SSE, let's see if we
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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184 * are allowed to or not. This will catch 2.4.0 or later kernels that
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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185 * haven't been configured for a Pentium III but are running on one,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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186 * and RedHat patched 2.2 kernels that have broken exception handling
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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187 * support for user space apps that do SSE.
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188 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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189 static void check_os_katmai_support( void )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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190 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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191 #if defined(__FreeBSD__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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192 int has_sse=0, ret;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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193 size_t len=sizeof(has_sse);
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194
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195 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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196 if (ret || !has_sse)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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197 gCpuCaps.hasSSE=0;
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198
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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199 #elif defined(__linux__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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200 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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201 struct sigaction saved_sigill;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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202 struct sigaction saved_sigfpe;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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203
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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204 /* Save the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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205 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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206 sigaction( SIGILL, NULL, &saved_sigill );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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207 sigaction( SIGFPE, NULL, &saved_sigfpe );
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208
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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209 signal( SIGILL, (void (*)(int))sigill_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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210 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
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211
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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212 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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213 * supports the extended FPU save and restore required for SSE. If
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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214 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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215 * doesn't support Streaming SIMD Exceptions, even if the processor
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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216 * does.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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217 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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218 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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219 printf( "Testing OS support for SSE... " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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220
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221 // __asm __volatile ("xorps %%xmm0, %%xmm0");
c26a9eff0993 cpu detection fixed
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222 __asm __volatile ("xorps %xmm0, %xmm0");
2268
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223
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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224 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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225 printf( "yes.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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226 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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227 printf( "no!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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228 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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229 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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230
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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231 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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232 * it supports unmasked SIMD FPU exceptions. If we unmask the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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233 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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234 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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235 * as expected, we're okay but we need to clean up after it.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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236 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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237 * Are we being too stringent in our requirement that the OS support
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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238 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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239 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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240 * doesn't even support them. We at least know the user-space SSE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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241 * support is good in kernels that do support unmasked exceptions,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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242 * and therefore to be safe I'm going to leave this test in here.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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243 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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244 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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245 printf( "Testing OS support for SSE unmasked exceptions... " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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246
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247 // test_os_katmai_exception_support();
2268
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248
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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249 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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250 printf( "yes.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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251 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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252 printf( "no!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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253 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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254 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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255
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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256 /* Restore the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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257 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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258 sigaction( SIGILL, &saved_sigill, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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259 sigaction( SIGFPE, &saved_sigfpe, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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260
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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261 /* If we've gotten to here and the XMM CPUID bit is still set, we're
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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262 * safe to go ahead and hook out the SSE code throughout Mesa.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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263 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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264 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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265 printf( "Tests of OS support for SSE passed.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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266 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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267 printf( "Tests of OS support for SSE failed!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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268 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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269 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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270 /* We can't use POSIX signal handling to test the availability of
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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271 * SSE, so we disable it by default.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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272 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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273 printf( "Cannot test OS support for SSE, disabling to be safe.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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274 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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275 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
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276 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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277 /* Do nothing on other platforms for now.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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278 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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279 message( "Not testing OS support for SSE, leaving disabled.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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280 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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281 #endif /* __linux__ */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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282 }
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283 #endif /* ARCH_X86 */