annotate cpudetect.c @ 3413:6236baa23bde

-ac a52 implemented
author arpi
date Sun, 09 Dec 2001 19:24:02 +0000
parents c4ca766a2d05
children 91f801a94a59
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1 #include "config.h"
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2 #include "cpudetect.h"
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3
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4 CpuCaps gCpuCaps;
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5
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6 #ifdef ARCH_X86
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7
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8 #include <stdio.h>
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9
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10 #ifdef __FreeBSD__
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11 #include <sys/types.h>
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12 #include <sys/sysctl.h>
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13 #endif
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14
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15 #ifdef __linux__
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16 #include <signal.h>
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17 #endif
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18
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19 //#define X86_FXSR_MAGIC
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20 /* Thanks to the FreeBSD project for some of this cpuid code, and
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21 * help understanding how to use it. Thanks to the Mesa
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22 * team for SSE support detection and more cpu detect code.
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23 */
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24
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25 /* I believe this code works. However, it has only been used on a PII and PIII */
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26
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27 static void check_os_katmai_support( void );
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28
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29 #if 1
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30 // return TRUE if cpuid supported
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31 static int has_cpuid()
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32 {
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33 int a, c;
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34
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35 // code from libavcodec:
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36 __asm__ __volatile__ (
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37 /* See if CPUID instruction is supported ... */
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38 /* ... Get copies of EFLAGS into eax and ecx */
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39 "pushf\n\t"
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40 "popl %0\n\t"
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41 "movl %0, %1\n\t"
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42
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43 /* ... Toggle the ID bit in one copy and store */
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44 /* to the EFLAGS reg */
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45 "xorl $0x200000, %0\n\t"
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46 "push %0\n\t"
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47 "popf\n\t"
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48
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49 /* ... Get the (hopefully modified) EFLAGS */
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50 "pushf\n\t"
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51 "popl %0\n\t"
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52 : "=a" (a), "=c" (c)
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53 :
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54 : "cc"
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55 );
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56
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57 return (a!=c);
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58 }
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59 #endif
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60
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61 static void
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62 do_cpuid(unsigned int ax, unsigned int *p)
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63 {
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64 #if 0
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65 __asm __volatile(
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66 "cpuid;"
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67 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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68 : "0" (ax)
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69 );
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70 #else
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71 // code from libavcodec:
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72 __asm __volatile
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73 ("movl %%ebx, %%esi\n\t"
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74 "cpuid\n\t"
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75 "xchgl %%ebx, %%esi"
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76 : "=a" (p[0]), "=S" (p[1]),
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77 "=c" (p[2]), "=d" (p[3])
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78 : "0" (ax));
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79 #endif
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80
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81 }
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82
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83 void GetCpuCaps( CpuCaps *caps)
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84 {
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85 unsigned int regs[4];
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86 unsigned int regs2[4];
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87
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88 caps->isX86=1;
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89
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90 bzero(caps, sizeof(*caps));
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91 if (!has_cpuid()) {
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92 printf("CPUID not supported!???\n");
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93 return;
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94 }
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95 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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96 printf("CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",&regs[1],&regs[3],&regs[2],regs[0]);
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97 if (regs[0]>=0x00000001)
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98 {
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99 char *tmpstr;
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100
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101 do_cpuid(0x00000001, regs2);
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102
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103 tmpstr=GetCpuFriendlyName(regs, regs2);
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104 printf("CPU: %s ",tmpstr);
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105 free(tmpstr);
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106
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107 caps->cpuType=(regs2[0] >> 8)&0xf;
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108 if(caps->cpuType==0xf){
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109 // use extended family (P4, IA64)
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110 caps->cpuType=8+((regs2[0]>>20)&255);
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111 }
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112 caps->cpuStepping=regs2[0] & 0xf;
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113 printf("(Type: %d, Stepping: %d)\n",
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114 caps->cpuType, caps->cpuStepping);
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115
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116 // general feature flags:
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117 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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118 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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119 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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120 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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121 }
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122 do_cpuid(0x80000000, regs);
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123 if (regs[0]>=0x80000001) {
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124 printf("extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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125 do_cpuid(0x80000001, regs2);
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126 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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127 caps->hasMMX2 = (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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128 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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129 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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130 }
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131 #if 0
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132 printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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133 gCpuCaps.hasMMX,
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134 gCpuCaps.hasMMX2,
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135 gCpuCaps.hasSSE,
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136 gCpuCaps.hasSSE2,
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137 gCpuCaps.has3DNow,
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138 gCpuCaps.has3DNowExt );
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139 #endif
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140
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141 /* FIXME: Does SSE2 need more OS support, too? */
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142 #if defined(__linux__) || defined(__FreeBSD__)
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143 if (caps->hasSSE)
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144 check_os_katmai_support();
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145 if (!caps->hasSSE)
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146 caps->hasSSE2 = 0;
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147 #else
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148 caps->hasSSE=0;
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149 caps->hasSSE2 = 0;
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150 #endif
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151 // caps->has3DNow=1;
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152 // caps->hasMMX2 = 0;
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153 // caps->hasMMX = 0;
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154
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155 }
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156
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157
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158 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
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159 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
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160 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
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161 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
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162 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
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163 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
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164
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165 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
b4c4c832cce7 Detect and show cpu name.
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166 #include "cputable.h" /* get cpuname and cpuvendors */
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167 char vendor[17];
2303
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parents: 2301
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168 char *retname;
2301
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169 int i;
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170
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171 if (NULL==(retname=(char*)malloc(256))) {
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172 printf("Error: GetCpuFriendlyName() not enough memory\n");
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173 exit(1);
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174 }
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175
2301
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176 sprintf(vendor,"%.4s%.4s%.4s",&regs[1],&regs[3],&regs[2]);
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177
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178 for(i=0; i<MAX_VENDORS; i++){
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179 if(!strcmp(cpuvendors[i].string,vendor)){
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180 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
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181 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
2301
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182 } else {
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183 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
2301
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184 printf("unknown %s CPU:\n",cpuvendors[i].name);
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185 printf("Vendor: %s\n",cpuvendors[i].string);
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186 printf("Type: %d\n",CPUID_TYPE);
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187 printf("Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
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188 printf("Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
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189 printf("Stepping: %d\n",CPUID_STEPPING);
b4c4c832cce7 Detect and show cpu name.
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190 printf("Please send the above info along with the exact CPU name"
b4c4c832cce7 Detect and show cpu name.
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191 "to the MPlayer-Developers, so we can add it to the list!\n");
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192 }
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193 }
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194 }
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195
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196 //printf("Detected CPU: %s\n", retname);
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197 return retname;
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198 }
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199
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200 #undef CPUID_EXTFAMILY
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201 #undef CPUID_EXTMODEL
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202 #undef CPUID_TYPE
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203 #undef CPUID_FAMILY
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204 #undef CPUID_MODEL
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205 #undef CPUID_STEPPING
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206
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207
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208 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
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209 static void sigill_handler_sse( int signal, struct sigcontext sc )
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210 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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211 printf( "SIGILL, " );
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212
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213 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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214 * instructions are 3 bytes long. We must increment the instruction
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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215 * pointer manually to avoid repeated execution of the offending
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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216 * instruction.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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217 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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218 * If the SIGILL is caused by a divide-by-zero when unmasked
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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219 * exceptions aren't supported, the SIMD FPU status and control
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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220 * word will be restored at the end of the test, so we don't need
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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221 * to worry about doing it here. Besides, we may not be able to...
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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222 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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223 sc.eip += 3;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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224
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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225 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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226 }
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arpi
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227
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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228 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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229 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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230 printf( "SIGFPE, " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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231
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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232 if ( sc.fpstate->magic != 0xffff ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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233 /* Our signal context has the extended FPU state, so reset the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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234 * divide-by-zero exception mask and clear the divide-by-zero
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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235 * exception bit.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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236 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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237 sc.fpstate->mxcsr |= 0x00000200;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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238 sc.fpstate->mxcsr &= 0xfffffffb;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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239 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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240 /* If we ever get here, we're completely hosed.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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241 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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242 printf( "\n\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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243 printf( "SSE enabling test failed badly!" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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244 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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245 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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246 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
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247
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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248 /* If we're running on a processor that can do SSE, let's see if we
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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249 * are allowed to or not. This will catch 2.4.0 or later kernels that
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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250 * haven't been configured for a Pentium III but are running on one,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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251 * and RedHat patched 2.2 kernels that have broken exception handling
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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252 * support for user space apps that do SSE.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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253 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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254 static void check_os_katmai_support( void )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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255 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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256 #if defined(__FreeBSD__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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257 int has_sse=0, ret;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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258 size_t len=sizeof(has_sse);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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259
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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260 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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261 if (ret || !has_sse)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
262 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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263
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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264 #elif defined(__linux__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
265 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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266 struct sigaction saved_sigill;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
267 struct sigaction saved_sigfpe;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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269 /* Save the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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270 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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271 sigaction( SIGILL, NULL, &saved_sigill );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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272 sigaction( SIGFPE, NULL, &saved_sigfpe );
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arpi
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273
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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274 signal( SIGILL, (void (*)(int))sigill_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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275 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
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arpi
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276
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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277 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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278 * supports the extended FPU save and restore required for SSE. If
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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279 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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280 * doesn't support Streaming SIMD Exceptions, even if the processor
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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281 * does.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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282 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
283 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
284 printf( "Testing OS support for SSE... " );
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285
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286 // __asm __volatile ("xorps %%xmm0, %%xmm0");
c26a9eff0993 cpu detection fixed
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287 __asm __volatile ("xorps %xmm0, %xmm0");
2268
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288
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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289 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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290 printf( "yes.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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291 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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292 printf( "no!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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293 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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294 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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295
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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296 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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297 * it supports unmasked SIMD FPU exceptions. If we unmask the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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298 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
299 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
300 * as expected, we're okay but we need to clean up after it.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
301 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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302 * Are we being too stringent in our requirement that the OS support
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
303 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
304 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
305 * doesn't even support them. We at least know the user-space SSE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
306 * support is good in kernels that do support unmasked exceptions,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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307 * and therefore to be safe I'm going to leave this test in here.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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308 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
309 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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310 printf( "Testing OS support for SSE unmasked exceptions... " );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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311
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312 // test_os_katmai_exception_support();
2268
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313
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
314 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
315 printf( "yes.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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316 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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317 printf( "no!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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318 }
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arpi
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319 }
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arpi
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320
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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321 /* Restore the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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322 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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323 sigaction( SIGILL, &saved_sigill, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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324 sigaction( SIGFPE, &saved_sigfpe, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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325
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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326 /* If we've gotten to here and the XMM CPUID bit is still set, we're
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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327 * safe to go ahead and hook out the SSE code throughout Mesa.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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328 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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329 if ( gCpuCaps.hasSSE ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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330 printf( "Tests of OS support for SSE passed.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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331 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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332 printf( "Tests of OS support for SSE failed!\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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333 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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334 #else
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arpi
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335 /* We can't use POSIX signal handling to test the availability of
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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336 * SSE, so we disable it by default.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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337 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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338 printf( "Cannot test OS support for SSE, disabling to be safe.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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339 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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340 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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341 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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342 /* Do nothing on other platforms for now.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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343 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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344 message( "Not testing OS support for SSE, leaving disabled.\n" );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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345 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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346 #endif /* __linux__ */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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347 }
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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348 #else /* ARCH_X86 */
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michael
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349
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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350 void GetCpuCaps( CpuCaps *caps)
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michael
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351 {
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michael
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352 caps->cpuType=0;
3403
c4ca766a2d05 added cpuStepping to CpuCaps struct (needed win32.c)
alex
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353 caps->cpuStepping=0;
3146
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michael
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354 caps->hasMMX=0;
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michael
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355 caps->hasMMX2=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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356 caps->has3DNow=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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357 caps->has3DNowExt=0;
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michael
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358 caps->hasSSE=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
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359 caps->hasSSE2=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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360 caps->isX86=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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361 }
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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362 #endif /* !ARCH_X86 */