Mercurial > mplayer.hg
annotate vidix/savage_vid.c @ 25944:8a1c062707ff
Do not uselessly erase background, OpenGL will take care of drawing everything.
author | reimar |
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date | Sun, 10 Feb 2008 19:47:54 +0000 |
parents | 110952f312cc |
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rev | line source |
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22850 | 1 /* |
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2 * VIDIX driver for S3 Savage chipsets. |
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3 * Copyright (C) 2004 Reza Jelveh |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with MPlayer; if not, write to the Free Software |
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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20 * |
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21 * Thanks to Alex Deucher for Support |
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22 */ |
22850 | 23 |
24 #include <errno.h> | |
25 #include <stdio.h> | |
26 #include <stdlib.h> | |
27 #include <string.h> | |
28 #include <inttypes.h> | |
29 #include <unistd.h> | |
30 #include <math.h> | |
31 | |
32 #include "vidix.h" | |
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33 #include "vidixlib.h" |
22850 | 34 #include "fourcc.h" |
22901 | 35 #include "dha.h" |
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36 #include "pci_ids.h" |
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37 #include "pci_names.h" |
22905 | 38 #include "config.h" |
22850 | 39 |
40 #include "savage_regs.h" | |
41 | |
42 | |
43 #define VF_STREAMS_ON 0x0001 | |
44 #define BASE_PAD 0xf | |
45 #define FRAMEBUFFER_SIZE 1024*2000*4 | |
46 /************************************** | |
47 S3 streams processor | |
48 **************************************/ | |
49 | |
50 #define EXT_MISC_CTRL2 0x67 | |
51 | |
52 /* New streams */ | |
53 | |
54 /* CR67[2] = 1 : enable stream 1 */ | |
55 #define ENABLE_STREAM1 0x04 | |
56 /* CR67[1] = 1 : enable stream 2 */ | |
57 #define ENABLE_STREAM2 0x02 | |
58 /* mask to clear CR67[2,1] */ | |
59 #define NO_STREAMS 0xF9 | |
60 /* CR67[3] = 1 : Mem-mapped regs */ | |
61 #define USE_MM_FOR_PRI_STREAM 0x08 | |
62 | |
63 #define HDM_SHIFT 16 | |
64 #define HDSCALE_4 (2 << HDM_SHIFT) | |
65 #define HDSCALE_8 (3 << HDM_SHIFT) | |
66 #define HDSCALE_16 (4 << HDM_SHIFT) | |
67 #define HDSCALE_32 (5 << HDM_SHIFT) | |
68 #define HDSCALE_64 (6 << HDM_SHIFT) | |
69 | |
70 /* Old Streams */ | |
71 | |
72 #define ENABLE_STREAMS_OLD 0x0c | |
73 #define NO_STREAMS_OLD 0xf3 | |
74 /* CR69[0] = 1 : Mem-mapped regs */ | |
75 #define USE_MM_FOR_PRI_STREAM_OLD 0x01 | |
76 | |
23057 | 77 static void SavageStreamsOn(void); |
22850 | 78 |
79 /* | |
80 * There are two different streams engines used in the Savage line. | |
81 * The old engine is in the 3D, 4, Pro, and Twister. | |
82 * The new engine is in the 2000, MX, IX, and Super. | |
83 */ | |
84 | |
85 | |
86 /* streams registers for old engine */ | |
87 #define PSTREAM_CONTROL_REG 0x8180 | |
88 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 | |
89 #define SSTREAM_CONTROL_REG 0x8190 | |
90 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 | |
91 #define SSTREAM_STRETCH_REG 0x8198 | |
92 #define COLOR_ADJUSTMENT_REG 0x819C | |
93 #define BLEND_CONTROL_REG 0x81A0 | |
94 #define PSTREAM_FBADDR0_REG 0x81C0 | |
95 #define PSTREAM_FBADDR1_REG 0x81C4 | |
96 #define PSTREAM_STRIDE_REG 0x81C8 | |
97 #define DOUBLE_BUFFER_REG 0x81CC | |
98 #define SSTREAM_FBADDR0_REG 0x81D0 | |
99 #define SSTREAM_FBADDR1_REG 0x81D4 | |
100 #define SSTREAM_STRIDE_REG 0x81D8 | |
101 #define SSTREAM_VSCALE_REG 0x81E0 | |
102 #define SSTREAM_VINITIAL_REG 0x81E4 | |
103 #define SSTREAM_LINES_REG 0x81E8 | |
104 #define STREAMS_FIFO_REG 0x81EC | |
105 #define PSTREAM_WINDOW_START_REG 0x81F0 | |
106 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 | |
107 #define SSTREAM_WINDOW_START_REG 0x81F8 | |
108 #define SSTREAM_WINDOW_SIZE_REG 0x81FC | |
109 #define FIFO_CONTROL 0x8200 | |
110 #define PSTREAM_FBSIZE_REG 0x8300 | |
111 #define SSTREAM_FBSIZE_REG 0x8304 | |
112 #define SSTREAM_FBADDR2_REG 0x8308 | |
113 | |
114 #define OS_XY(x,y) (((x+1)<<16)|(y+1)) | |
115 #define OS_WH(x,y) (((x-1)<<16)|(y)) | |
116 | |
117 #define PCI_COMMAND_MEM 0x2 | |
118 #define MAX_FRAMES 3 | |
119 /** | |
120 * @brief Information on PCI device. | |
121 */ | |
23057 | 122 static pciinfo_t pci_info; |
22850 | 123 |
124 #define outb(reg,val) OUTPORT8(reg,val) | |
125 #define inb(reg) INPORT8(reg) | |
126 #define outw(reg,val) OUTPORT16(reg,val) | |
127 #define inw(reg) INPORT16(reg) | |
128 #define outl(reg,val) OUTPORT32(reg,val) | |
129 #define inl(reg) INPORT32(reg) | |
130 | |
131 | |
132 /* | |
133 * PCI-Memory IO access macros. | |
134 */ | |
135 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
136 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
137 | |
138 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
139 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
140 | |
141 #ifndef USE_RMW_CYCLES | |
142 /* | |
143 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
144 */ | |
145 | |
146 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
147 | |
148 #undef VID_WR08 | |
149 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
150 #undef VID_RD08 | |
151 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
152 | |
153 #undef VID_WR16 | |
154 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) | |
155 #undef VID_RD16 | |
156 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) | |
157 | |
158 #undef VID_WR32 | |
159 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
160 #undef VID_RD32 | |
161 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
162 #endif /* USE_RMW_CYCLES */ | |
163 | |
164 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
165 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
166 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
167 | |
168 | |
169 /* from x driver */ | |
170 | |
171 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) | |
172 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) | |
173 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) | |
174 | |
175 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) | |
176 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) | |
177 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) | |
178 | |
179 #define INREG(addr) VID_RD32(info->control_base, addr) | |
180 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) | |
181 #define INREG8(addr) VID_RD08(info->control_base, addr) | |
182 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) | |
183 #define INREG16(addr) VID_RD16(info->control_base, addr) | |
184 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) | |
185 | |
186 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) | |
187 | |
188 | |
23057 | 189 static void debugout(unsigned int addr, unsigned int val); |
22850 | 190 |
191 | |
192 struct savage_chip { | |
193 volatile uint32_t *PMC; /* general control */ | |
194 volatile uint32_t *PME; /* multimedia port */ | |
195 volatile uint32_t *PFB; /* framebuffer control */ | |
196 volatile uint32_t *PVIDEO; /* overlay control */ | |
197 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
198 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
199 volatile uint32_t *PRAMIN; /* instance memory */ | |
200 volatile uint32_t *PRAMHT; /* hash table */ | |
201 volatile uint32_t *PRAMFC; /* fifo context table */ | |
202 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
203 volatile uint32_t *PFIFO; /* fifo control region */ | |
204 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
205 volatile uint32_t *PGRAPH; /* graphics engine */ | |
206 | |
207 int arch; /* compatible NV_ARCH_XX define */ | |
208 unsigned long fbsize; /* framebuffer size */ | |
209 void (* lock) (struct savage_chip *, int); | |
210 }; | |
211 typedef struct savage_chip savage_chip; | |
212 | |
213 | |
214 struct savage_info { | |
215 unsigned int use_colorkey; | |
216 unsigned int colorkey; /* saved xv colorkey*/ | |
217 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
218 unsigned int depth; | |
219 unsigned int bpp; | |
220 unsigned int videoFlags; | |
221 unsigned int format; | |
222 unsigned int pitch; | |
223 unsigned int blendBase; | |
224 unsigned int lastKnownPitch; | |
225 unsigned int displayWidth, displayHeight; | |
226 unsigned int brightness,hue,saturation,contrast; | |
227 unsigned int src_w,src_h; | |
228 unsigned int drw_w,drw_h; /*scaled width && height*/ | |
229 unsigned int wx,wy; /*window x && y*/ | |
230 unsigned int screen_x; /*screen width*/ | |
231 unsigned int screen_y; /*screen height*/ | |
25370 | 232 unsigned long frame_size; /* frame size */ |
22850 | 233 struct savage_chip chip; /* NV architecture structure */ |
234 void* video_base; /* virtual address of control region */ | |
235 void* control_base; /* virtual address of fb region */ | |
236 unsigned long picture_base; /* direct pointer to video picture */ | |
237 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
238 // struct savage_dma dma; /* DMA structure */ | |
239 unsigned int num_frames; /* number of buffers */ | |
240 int bps; /* bytes per line */ | |
241 void (*SavageWaitIdle) (); | |
242 void (*SavageWaitFifo) (int space); | |
243 }; | |
244 typedef struct savage_info savage_info; | |
245 | |
246 | |
247 static savage_info* info; | |
248 | |
249 | |
250 /** | |
251 * @brief Unichrome driver vidix capabilities. | |
252 */ | |
253 static vidix_capability_t savage_cap = { | |
254 "Savage/ProSavage/Twister vidix", | |
255 "Reza Jelveh <reza.jelveh@tuhh.de>", | |
256 TYPE_OUTPUT, | |
257 {0, 0, 0, 0}, | |
258 4096, | |
259 4096, | |
260 4, | |
261 4, | |
262 -1, | |
263 FLAG_UPSCALER | FLAG_DOWNSCALER, | |
264 VENDOR_S3_INC, | |
265 -1, | |
266 {0, 0, 0, 0} | |
267 }; | |
268 | |
269 struct savage_cards { | |
270 unsigned short chip_id; | |
271 unsigned short arch; | |
272 }; | |
273 | |
274 | |
275 static | |
276 unsigned int GetBlendForFourCC( int id ) | |
277 { | |
278 switch( id ) { | |
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279 case IMGFMT_UYVY: |
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280 return 0; |
22850 | 281 case IMGFMT_YUY2: |
282 return 1; | |
283 case IMGFMT_Y211: | |
284 return 4; | |
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285 case IMGFMT_BGR15: |
22850 | 286 return 3; |
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287 case IMGFMT_BGR16: |
22850 | 288 return 5; |
25368 | 289 case IMGFMT_BGR24: |
290 return 6; | |
291 case IMGFMT_BGR32: | |
292 return 7; | |
22850 | 293 default: |
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294 return 1; |
22850 | 295 } |
296 } | |
297 | |
298 /** | |
299 * @brief list of card IDs compliant with the Unichrome driver . | |
300 */ | |
301 static struct savage_cards savage_card_ids[] = { | |
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302 /* Savage3D */ |
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303 { DEVICE_S3_INC_86C794_SAVAGE_3D, S3_SAVAGE3D }, |
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304 { DEVICE_S3_INC_86C390_SAVAGE_3D_MV, S3_SAVAGE3D }, |
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305 /* Savage4 */ |
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306 { DEVICE_S3_INC_SAVAGE_4, S3_SAVAGE4 }, |
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307 { DEVICE_S3_INC_SAVAGE_42, S3_SAVAGE4 }, |
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308 /* SavageMX */ |
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309 { DEVICE_S3_INC_86C270_294_SAVAGE_MX_MV, S3_SAVAGE_MX }, |
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310 { DEVICE_S3_INC_82C270_294_SAVAGE_MX, S3_SAVAGE_MX }, |
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311 { DEVICE_S3_INC_86C270_294_SAVAGE_IX_MV, S3_SAVAGE_MX }, |
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312 /* SuperSavage */ |
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313 { DEVICE_S3_INC_SUPERSAVAGE_MX_128, S3_SUPERSAVAGE }, |
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314 { DEVICE_S3_INC_SUPERSAVAGE_MX_64, S3_SUPERSAVAGE }, |
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315 { DEVICE_S3_INC_SUPERSAVAGE_MX_64C, S3_SUPERSAVAGE }, |
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316 { DEVICE_S3_INC_SUPERSAVAGE_IX_128_SDR, S3_SUPERSAVAGE }, |
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317 { DEVICE_S3_INC_SUPERSAVAGE_IX_128_DDR, S3_SUPERSAVAGE }, |
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318 { DEVICE_S3_INC_SUPERSAVAGE_IX_64_SDR, S3_SUPERSAVAGE }, |
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319 { DEVICE_S3_INC_SUPERSAVAGE_IX_64_DDR, S3_SUPERSAVAGE }, |
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320 { DEVICE_S3_INC_SUPERSAVAGE_IX_C_SDR, S3_SUPERSAVAGE }, |
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321 { DEVICE_S3_INC_SUPERSAVAGE_IX_C_DDR, S3_SUPERSAVAGE }, |
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322 /* ProSavage */ |
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323 { DEVICE_S3_INC_PROSAVAGE_PM133, S3_PROSAVAGE }, |
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324 { DEVICE_S3_INC_PROSAVAGE_KM133, S3_PROSAVAGE }, |
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325 { DEVICE_S3_INC_86C380_PROSAVAGEDDR_K4M266, S3_PROSAVAGE }, |
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326 { DEVICE_S3_INC_VT8636A_PROSAVAGE_KN133, S3_PROSAVAGE }, |
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327 { DEVICE_S3_INC_VT8751_PROSAVAGEDDR_P4M266, S3_PROSAVAGE }, |
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328 { DEVICE_S3_INC_VT8375_PROSAVAGE8_KM266_KL266, S3_PROSAVAGE }, |
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329 /* Savage2000 */ |
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330 { DEVICE_S3_INC_86C410_SAVAGE_2000, S3_SAVAGE2000 }, |
22850 | 331 }; |
332 | |
333 static void SavageSetColorOld(void) | |
334 { | |
335 | |
336 | |
337 if( | |
25367 | 338 (info->format == IMGFMT_BGR15) || |
339 (info->format == IMGFMT_BGR16) | |
22850 | 340 ) |
341 { | |
342 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
343 } | |
344 else | |
345 { | |
346 /* Change 0..255 into 0..15 */ | |
347 long sat = info->saturation * 16 / 256; | |
348 double hue = info->hue * 0.017453292; | |
349 unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; | |
350 unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; | |
351 | |
352 OUTREG( COLOR_ADJUSTMENT_REG, | |
353 0x80008000 | | |
354 (info->brightness + 128) | | |
355 ((info->contrast & 0xf8) << (12-7)) | | |
356 (hs1 << 16) | | |
357 (hs2 << 24) | |
358 ); | |
359 debugout( COLOR_ADJUSTMENT_REG, | |
360 0x80008000 | | |
361 (info->brightness + 128) | | |
362 ((info->contrast & 0xf8) << (12-7)) | | |
363 (hs1 << 16) | | |
364 (hs2 << 24) | |
365 ); | |
366 | |
367 } | |
368 } | |
369 | |
370 static void SavageSetColorKeyOld(void) | |
371 { | |
372 int red, green, blue; | |
373 | |
374 /* Here, we reset the colorkey and all the controls. */ | |
375 | |
376 red = (info->vidixcolorkey & 0x00FF0000) >> 16; | |
377 green = (info->vidixcolorkey & 0x0000FF00) >> 8; | |
378 blue = info->vidixcolorkey & 0x000000FF; | |
379 | |
380 if( !info->vidixcolorkey ) { | |
381 printf("SavageSetColorKey disabling colorkey\n"); | |
382 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
383 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
384 OUTREG( BLEND_CONTROL_REG, 0 ); | |
385 } | |
386 else { | |
387 switch (info->depth) { | |
388 // FIXME: isnt fixed yet | |
389 case 8: | |
390 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
391 0x37000000 | (info->vidixcolorkey & 0xFF) ); | |
392 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
393 0x00000000 | (info->vidixcolorkey & 0xFF) ); | |
394 break; | |
395 case 15: | |
396 /* 15 bpp 555 */ | |
397 red&=0x1f; | |
398 green&=0x1f; | |
399 blue&=0x1f; | |
400 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
401 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
402 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
403 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
404 break; | |
405 case 16: | |
406 /* 16 bpp 565 */ | |
407 red&=0x1f; | |
408 green&=0x3f; | |
409 blue&=0x1f; | |
410 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
411 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); | |
412 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
413 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); | |
414 break; | |
415 case 24: | |
416 /* 24 bpp 888 */ | |
417 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
418 0x17000000 | (red<<16) | (green<<8) | (blue) ); | |
419 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
420 0x00000000 | (red<<16) | (green<<8) | (blue) ); | |
421 break; | |
422 } | |
423 | |
424 /* We use destination colorkey */ | |
425 OUTREG( BLEND_CONTROL_REG, 0x05000000 ); | |
426 } | |
427 } | |
428 | |
429 | |
430 static void | |
431 SavageDisplayVideoOld(void) | |
432 { | |
433 int vgaCRIndex, vgaCRReg, vgaIOBase; | |
434 unsigned int ssControl; | |
435 int cr92; | |
436 | |
437 | |
438 vgaIOBase = 0x3d0; | |
439 vgaCRIndex = vgaIOBase + 4; | |
440 vgaCRReg = vgaIOBase + 5; | |
441 | |
442 // if( psav->videoFourCC != id ) | |
443 // SavageStreamsOff(pScrn); | |
444 | |
445 if( !info->videoFlags & VF_STREAMS_ON ) | |
446 { | |
447 SavageStreamsOn(); | |
448 // SavageResetVideo(); | |
449 SavageSetColorOld(); | |
450 SavageSetColorKeyOld(); | |
451 } | |
452 | |
453 | |
454 | |
455 | |
456 /* Calculate horizontal scale factor. */ | |
457 | |
458 //FIXME: enable scaling | |
459 OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); | |
460 // debugout(SSTREAM_STRETCH_REG, 1 << 15); | |
461 | |
462 OUTREG(SSTREAM_LINES_REG, info->src_h ); | |
463 debugout(SSTREAM_LINES_REG, info->src_h ); | |
464 | |
465 | |
466 OUTREG(SSTREAM_VINITIAL_REG, 0 ); | |
467 debugout(SSTREAM_VINITIAL_REG, 0 ); | |
468 /* Calculate vertical scale factor. */ | |
469 | |
470 // OUTREG(SSTREAM_VSCALE_REG, 1 << 15); | |
471 OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
472 debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
473 // OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); | |
474 | |
475 /* Set surface location and stride. */ | |
476 | |
477 OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
478 debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
479 | |
480 OUTREG(SSTREAM_FBADDR1_REG, 0 ); | |
481 debugout(SSTREAM_FBADDR1_REG, 0 ); | |
482 | |
483 OUTREG(SSTREAM_STRIDE_REG, info->pitch ); | |
484 debugout(SSTREAM_STRIDE_REG, info->pitch ); | |
485 | |
486 OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
487 debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
488 OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
489 debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
490 | |
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491 /* Set surface format and adjust scaling */ |
22850 | 492 |
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493 ssControl = GetBlendForFourCC(info->format) << 24 | info->src_w; |
22850 | 494 |
495 if( info->src_w > (info->drw_w << 1) ) | |
496 { | |
497 /* BUGBUG shouldn't this be >=? */ | |
498 if( info->src_w <= (info->drw_w << 2) ) | |
499 ssControl |= HDSCALE_4; | |
500 else if( info->src_w > (info->drw_w << 3) ) | |
501 ssControl |= HDSCALE_8; | |
502 else if( info->src_w > (info->drw_w << 4) ) | |
503 ssControl |= HDSCALE_16; | |
504 else if( info->src_w > (info->drw_w << 5) ) | |
505 ssControl |= HDSCALE_32; | |
506 else if( info->src_w > (info->drw_w << 6) ) | |
507 ssControl |= HDSCALE_64; | |
508 } | |
509 | |
510 OUTREG(SSTREAM_CONTROL_REG, ssControl); | |
511 debugout(SSTREAM_CONTROL_REG, ssControl); | |
512 | |
513 // FIXME: this should actually be enabled | |
514 | |
515 info->pitch = (info->pitch + 7) / 8; | |
516 VGAOUT8(vgaCRIndex, 0x92); | |
517 cr92 = VGAIN8(vgaCRReg); | |
518 VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); | |
519 VGAOUT8(vgaCRIndex, 0x93); | |
520 VGAOUT8(vgaCRReg, info->pitch); | |
521 OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); | |
522 | |
523 | |
524 | |
525 | |
526 } | |
527 | |
528 static void SavageInitStreamsOld(void) | |
529 { | |
530 /*unsigned long jDelta;*/ | |
531 unsigned long format = 0; | |
532 | |
533 /* | |
534 * For the OLD streams engine, several of these registers | |
535 * cannot be touched unless streams are on. Seems backwards to me; | |
536 * I'd want to set 'em up, then cut 'em loose. | |
537 */ | |
538 | |
539 | |
540 /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ | |
541 switch( info->depth ) { | |
542 case 8: format = 0 << 24; break; | |
543 case 15: format = 3 << 24; break; | |
544 case 16: format = 5 << 24; break; | |
545 case 24: format = 7 << 24; break; | |
546 } | |
25860 | 547 /* FIXME: enable this again */ |
22850 | 548 OUTREG(PSTREAM_FBSIZE_REG, |
549 info->screen_y * info->screen_x * (info->bpp >> 3)); | |
550 | |
551 OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); | |
552 OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); | |
553 OUTREG( PSTREAM_FBADDR1_REG, 0 ); | |
554 /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ | |
555 OUTREG( PSTREAM_CONTROL_REG, format ); | |
556 OUTREG( PSTREAM_FBADDR0_REG, 0 ); | |
557 | |
558 /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ | |
559 | |
560 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
561 OUTREG( SSTREAM_CONTROL_REG, 0 ); | |
562 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
563 OUTREG( SSTREAM_STRETCH_REG, 0 ); | |
564 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
565 OUTREG( BLEND_CONTROL_REG, 1 << 24 ); | |
566 OUTREG( DOUBLE_BUFFER_REG, 0 ); | |
567 OUTREG( SSTREAM_FBADDR0_REG, 0 ); | |
568 OUTREG( SSTREAM_FBADDR1_REG, 0 ); | |
569 OUTREG( SSTREAM_FBADDR2_REG, 0 ); | |
570 OUTREG( SSTREAM_FBSIZE_REG, 0 ); | |
571 OUTREG( SSTREAM_STRIDE_REG, 0 ); | |
572 OUTREG( SSTREAM_VSCALE_REG, 0 ); | |
573 OUTREG( SSTREAM_LINES_REG, 0 ); | |
574 OUTREG( SSTREAM_VINITIAL_REG, 0 ); | |
25860 | 575 /* FIXME: Is this needed? */ |
22850 | 576 OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); |
577 OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); | |
578 | |
579 } | |
580 | |
23057 | 581 static void |
22850 | 582 SavageStreamsOn(void) |
583 { | |
584 unsigned char jStreamsControl; | |
585 unsigned short vgaCRIndex = 0x3d0 + 4; | |
586 unsigned short vgaCRReg = 0x3d0 + 5; | |
587 | |
588 // xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); | |
589 | |
590 /* Sequence stolen from streams.c in M7 NT driver */ | |
591 | |
592 | |
593 enable_app_io (); | |
594 | |
595 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
596 | |
597 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) | |
598 { | |
599 // SavageInitStreamsNew( pScrn ); | |
600 | |
601 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
602 | |
603 /* Wait for VBLANK. */ | |
604 VerticalRetraceWait(); | |
605 /* Fire up streams! */ | |
606 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
607 /* These values specify brightness, contrast, saturation and hue. */ | |
608 OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); | |
609 OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); | |
610 OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); | |
611 } | |
612 else if (info->chip.arch == S3_SAVAGE2000) | |
613 { | |
614 // SavageInitStreams2000( pScrn ); | |
615 | |
616 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
617 | |
618 /* Wait for VBLANK. */ | |
619 VerticalRetraceWait(); | |
620 /* Fire up streams! */ | |
621 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
622 /* These values specify brightness, contrast, saturation and hue. */ | |
623 OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); | |
624 OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); | |
625 OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); | |
626 OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); | |
627 } | |
628 else | |
629 { | |
630 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; | |
631 | |
632 /* Wait for VBLANK. */ | |
633 | |
634 VerticalRetraceWait(); | |
635 | |
636 /* Fire up streams! */ | |
637 | |
638 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
639 | |
640 SavageInitStreamsOld( ); | |
641 } | |
642 | |
643 /* Wait for VBLANK. */ | |
644 | |
645 VerticalRetraceWait(); | |
646 | |
647 /* Turn on secondary stream TV flicker filter, once we support TV. */ | |
648 | |
649 /* SR70 |= 0x10 */ | |
650 | |
651 info->videoFlags |= VF_STREAMS_ON; | |
652 | |
653 } | |
654 | |
655 | |
656 | |
657 | |
658 static void savage_getscreenproperties(struct savage_info *info){ | |
659 unsigned char bpp=0; | |
660 | |
661 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; | |
662 | |
663 vgaIOBase = 0x3d0; | |
664 vgaCRIndex = vgaIOBase + 4; | |
665 vgaCRReg = vgaIOBase + 5; | |
666 | |
667 | |
668 /* a little reversed from x driver source code */ | |
669 VGAOUT8(vgaCRIndex, 0x67); | |
670 bpp = VGAIN8(vgaCRReg); | |
671 | |
672 | |
673 switch (bpp&0xf0) { | |
674 case 0x00: | |
675 case 0x10: | |
676 info->depth=8; | |
677 info->bpp=8; | |
678 break; | |
679 case 0x20: | |
680 case 0x30: | |
681 info->depth=15; | |
682 info->bpp=16; | |
683 break; | |
684 case 0x40: | |
685 case 0x50: | |
686 info->depth=16; | |
687 info->bpp=16; | |
688 break; | |
689 case 0x70: | |
690 case 0xd0: | |
691 info->depth=24; | |
692 info->bpp=32; | |
693 break; | |
694 | |
695 | |
696 } | |
697 | |
698 | |
699 VGAOUT8(vgaCRIndex, 0x1); | |
700 info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; | |
701 /*get screen height*/ | |
702 /* get first 8 bits in VT_DISPLAY_END*/ | |
703 VGAOUT8(0x03D4, 0x12); | |
704 info->screen_y = VGAIN8(0x03D5); | |
705 VGAOUT8(0x03D4,0x07); | |
706 /* get 9th bit in CRTC_OVERFLOW*/ | |
707 info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; | |
708 /* and the 10th in CRTC_OVERFLOW*/ | |
709 info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; | |
710 ++info->screen_y; | |
711 | |
712 printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); | |
713 } | |
714 | |
715 | |
716 static void SavageStreamsOff(void) | |
717 { | |
718 unsigned char jStreamsControl; | |
719 unsigned short vgaCRIndex = 0x3d0 + 4; | |
720 unsigned short vgaCRReg = 0x3d0 + 5; | |
721 | |
722 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
723 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || | |
724 (info->chip.arch == S3_SUPERSAVAGE) || | |
725 (info->chip.arch == S3_SAVAGE2000) ) | |
726 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; | |
727 else | |
728 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; | |
729 | |
730 /* Wait for VBLANK. */ | |
731 | |
732 VerticalRetraceWait(); | |
733 | |
734 /* Kill streams. */ | |
735 | |
736 VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
737 | |
738 VGAOUT16(vgaCRIndex, 0x0093 ); | |
739 VGAOUT8( vgaCRIndex, 0x92 ); | |
740 VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); | |
741 | |
742 info->videoFlags &= ~VF_STREAMS_ON; | |
743 } | |
744 | |
745 /** | |
746 * @brief Find chip index in Unichrome compliant devices list. | |
747 * | |
748 * @param chip_id PCI device ID. | |
749 * | |
750 * @returns index position in savage_card_ids if successful. | |
751 * -1 if chip_id is not a compliant chipset ID. | |
752 */ | |
753 | |
754 static int find_chip(unsigned chip_id){ | |
755 unsigned i; | |
756 for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) | |
757 { | |
758 if(chip_id == savage_card_ids[i].chip_id)return i; | |
759 } | |
760 return -1; | |
761 } | |
762 | |
763 /** | |
764 * @brief Probe hardware to find some useable chipset. | |
765 * | |
766 * @param verbose specifies verbose level. | |
767 * @param force specifies force mode : driver should ignore | |
768 * device_id (danger but useful for new devices) | |
769 * | |
770 * @returns 0 if it can handle something in PC. | |
771 * a negative error code otherwise. | |
772 */ | |
773 | |
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774 static int savage_probe(int verbose, int force){ |
22850 | 775 pciinfo_t lst[MAX_PCI_DEVICES]; |
776 unsigned i,num_pci; | |
777 int err; | |
778 | |
779 if (force) | |
780 printf("[savage_vid]: warning: forcing not supported yet!\n"); | |
781 err = pci_scan(lst,&num_pci); | |
782 if(err){ | |
783 printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
784 return err; | |
785 } | |
786 else { | |
787 err = ENXIO; | |
788 for(i=0; i < num_pci; i++){ | |
789 if(lst[i].vendor == VENDOR_S3_INC) { | |
790 int idx; | |
791 const char *dname; | |
792 idx = find_chip(lst[i].device); | |
793 if(idx == -1) | |
794 continue; | |
795 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
796 dname = dname ? dname : "Unknown chip"; | |
797 printf("[savage_vid] Found chip: %s\n", dname); | |
798 // FIXME: whats wrong here? | |
799 if ((lst[i].command & PCI_COMMAND_IO ) == 0){ | |
800 printf("[savage_vid] Device is disabled, ignoring\n"); | |
801 continue; | |
802 } | |
803 savage_cap.device_id = lst[i].device; | |
804 err = 0; | |
805 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
806 break; | |
807 } | |
808 } | |
809 } | |
810 if(err && verbose) printf("[savage_vid] Can't find chip\n"); | |
811 return err; | |
812 } | |
813 | |
814 /** | |
815 * @brief Initializes driver. | |
816 * | |
817 * @returns 0 if ok. | |
818 * a negative error code otherwise. | |
819 */ | |
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820 static int |
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821 savage_init (void) |
22850 | 822 { |
823 int mtrr; | |
22868 | 824 unsigned char config1, tmp; |
22850 | 825 |
826 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; | |
827 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; | |
828 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; | |
829 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; | |
830 | |
22868 | 831 int videoRam; |
22850 | 832 |
833 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; | |
834 | |
835 unsigned char val; | |
836 | |
837 vgaIOBase = 0x3d0; | |
838 vgaCRIndex = vgaIOBase + 4; | |
839 vgaCRReg = vgaIOBase + 5; | |
840 | |
841 fprintf(stderr, "vixInit enter \n"); | |
842 // //getc(stdin); | |
843 | |
844 info = calloc(1,sizeof(savage_info)); | |
845 | |
846 | |
847 /* need this if we want direct outb and inb access? */ | |
848 enable_app_io (); | |
849 | |
850 /* 12mb + 32kb ? */ | |
851 /* allocate some space for control registers */ | |
852 info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; | |
853 | |
854 if (info->chip.arch == S3_SAVAGE3D) { | |
855 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); | |
856 } | |
857 else { | |
858 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); | |
859 } | |
860 | |
861 // info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); | |
862 | |
25370 | 863 /* switch to vga registers */ |
22850 | 864 val = VGAIN8 (0x3c3); |
865 VGAOUT8 (0x3c3, val | 0x01); | |
866 val = VGAIN8 (0x3cc); | |
867 VGAOUT8 (0x3c2, val | 0x01); | |
868 | |
869 /* unprotect CRTC[0-7] */ | |
870 VGAOUT8(vgaCRIndex, 0x11); | |
871 tmp = VGAIN8(vgaCRReg); | |
872 // printf("$########## tmp = %d\n",tmp); | |
873 VGAOUT8(vgaCRReg, tmp & 0x7f); | |
874 | |
875 | |
876 /* unlock extended regs */ | |
877 VGAOUT16(vgaCRIndex, 0x4838); | |
878 VGAOUT16(vgaCRIndex, 0xa039); | |
879 VGAOUT16(0x3c4, 0x0608); | |
880 | |
881 /* Next go on to detect amount of installed ram */ | |
882 | |
883 VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ | |
884 config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ | |
885 | |
886 | |
887 switch( info->chip.arch ) { | |
888 case S3_SAVAGE3D: | |
889 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; | |
890 break; | |
891 | |
892 case S3_SAVAGE4: | |
893 /* | |
894 * The Savage4 has one ugly special case to consider. On | |
895 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB | |
896 * when it really means 8MB. Why do it the same when you | |
897 * can do it different... | |
898 */ | |
899 VGAOUT8(0x3d4, 0x68); /* memory control 1 */ | |
900 if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) | |
901 RamSavage4[1] = 8; | |
902 | |
903 /*FALLTHROUGH*/ | |
904 | |
905 case S3_SAVAGE2000: | |
906 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; | |
907 break; | |
908 | |
909 case S3_SAVAGE_MX: | |
910 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; | |
911 break; | |
912 | |
913 case S3_PROSAVAGE: | |
914 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; | |
915 break; | |
916 | |
917 default: | |
918 /* How did we get here? */ | |
919 videoRam = 0; | |
920 break; | |
921 } | |
922 | |
923 | |
924 printf("###### videoRam = %d\n",videoRam); | |
925 info->chip.fbsize = videoRam * 1024; | |
926 | |
927 | |
928 /* reset graphics engine to avoid memory corruption */ | |
929 /* VGAOUT8 (0x3d4, 0x66); | |
930 cr66 = VGAIN8 (0x3d5); | |
931 VGAOUT8 (0x3d5, cr66 | 0x02); | |
932 udelay (10000); | |
933 | |
934 VGAOUT8 (0x3d4, 0x66); | |
22868 | 935 VGAOUT8 (0x3d5, cr66 & ~0x02); */ // clear reset flag |
22850 | 936 /* udelay (10000); */ |
937 | |
938 if ( info->chip.arch == S3_SAVAGE3D ){ | |
939 mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
940 } | |
941 else{ | |
942 mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
943 } | |
944 | |
945 if (mtrr!= 0) | |
946 printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
947 else | |
948 printf("[savage_vid] MTRR set up\n"); | |
949 | |
950 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
951 | |
952 | |
953 savage_getscreenproperties(info); | |
954 // return -1; | |
955 info->videoFlags = 0; | |
956 | |
957 SavageStreamsOn(); | |
958 //getc(stdin); | |
959 //FIXME ADD | |
960 return 0; | |
961 } | |
962 | |
963 /** | |
964 * @brief Destroys driver. | |
965 */ | |
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967 savage_destroy (void) |
22850 | 968 { |
969 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
970 unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); | |
971 //FIXME ADD | |
972 } | |
973 | |
974 /** | |
975 * @brief Get chipset's hardware capabilities. | |
976 * | |
977 * @param to Pointer to the vidix_capability_t structure to be filled. | |
978 * | |
979 * @returns 0. | |
980 */ | |
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981 static int |
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982 savage_get_caps (vidix_capability_t * to) |
22850 | 983 { |
984 memcpy (to, &savage_cap, sizeof (vidix_capability_t)); | |
985 return 0; | |
986 } | |
987 | |
988 /** | |
989 * @brief Report if the video FourCC is supported by hardware. | |
990 * | |
991 * @param fourcc input image format. | |
992 * | |
993 * @returns 1 if the fourcc is supported. | |
994 * 0 otherwise. | |
995 */ | |
996 static int | |
997 is_supported_fourcc (uint32_t fourcc) | |
998 { | |
999 switch (fourcc) | |
1000 { | |
1001 //FIXME: YV12 isnt working properly yet | |
1002 // case IMGFMT_YV12: | |
1003 // case IMGFMT_I420: | |
1004 case IMGFMT_UYVY: | |
1005 case IMGFMT_YUY2: | |
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1006 case IMGFMT_Y211: |
22850 | 1007 case IMGFMT_RGB15: |
1008 case IMGFMT_RGB16: | |
25368 | 1009 case IMGFMT_BGR24: |
1010 case IMGFMT_BGR32: | |
22850 | 1011 return 1; |
1012 default: | |
1013 return 0; | |
1014 } | |
1015 } | |
1016 | |
1017 /** | |
1018 * @brief Try to configure video memory for given fourcc. | |
1019 * | |
1020 * @param to Pointer to the vidix_fourcc_t structure to be filled. | |
1021 * | |
1022 * @returns 0 if ok. | |
1023 * errno otherwise. | |
1024 */ | |
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1025 static int |
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1026 savage_query_fourcc (vidix_fourcc_t * to) |
22850 | 1027 { |
1028 if (is_supported_fourcc (to->fourcc)) | |
1029 { | |
23060 | 1030 to->depth = VID_DEPTH_ALL; |
22850 | 1031 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
1032 return 0; | |
1033 } | |
1034 else | |
1035 to->depth = to->flags = 0; | |
1036 | |
1037 return ENOSYS; | |
1038 } | |
1039 | |
1040 /** | |
1041 * @brief Get the GrKeys | |
1042 * | |
1043 * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. | |
1044 * | |
1045 * @return 0. | |
1046 */ | |
1047 /*int | |
1048 vixGetGrKeys (vidix_grkey_t * grkey) | |
1049 { | |
1050 | |
1051 // if(info->d_width && info->d_height)savage_overlay_start(info,0); | |
1052 | |
1053 return (0); | |
1054 } | |
1055 * */ | |
1056 | |
1057 /** | |
1058 * @brief Set the GrKeys | |
1059 * | |
1060 * @param grkey Colorkey to be set. | |
1061 * | |
1062 * @return 0. | |
1063 */ | |
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1065 savage_set_gkeys (const vidix_grkey_t * grkey) |
22850 | 1066 { |
1067 if (grkey->ckey.op == CKEY_FALSE) | |
1068 { | |
1069 info->use_colorkey = 0; | |
1070 info->vidixcolorkey=0; | |
1071 printf("[savage_vid] colorkeying disabled\n"); | |
1072 } | |
1073 else { | |
1074 info->use_colorkey = 1; | |
1075 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1076 | |
1077 printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1078 } | |
1079 //FIXME: freezes if streams arent enabled | |
1080 SavageSetColorKeyOld(); | |
1081 return (0); | |
1082 } | |
1083 | |
1084 /** | |
1085 * @brief Unichrome driver equalizer capabilities. | |
1086 */ | |
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1087 static vidix_video_eq_t equal = { |
22850 | 1088 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, |
1089 300, 100, 0, 0, 0, 0, 0, 0 | |
1090 }; | |
1091 | |
1092 | |
1093 /** | |
1094 * @brief Get the equalizer capabilities. | |
1095 * | |
1096 * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. | |
1097 * | |
1098 * @return 0. | |
1099 */ | |
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1100 static int |
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1101 savage_get_eq (vidix_video_eq_t * eq) |
22850 | 1102 { |
1103 memcpy (eq, &equal, sizeof (vidix_video_eq_t)); | |
1104 return 0; | |
1105 } | |
1106 | |
1107 /** | |
1108 * @brief Set the equalizer capabilities for color correction | |
1109 * | |
1110 * @param eq equalizer capabilities to be set. | |
1111 * | |
1112 * @return 0. | |
1113 */ | |
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1114 static int |
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1115 savage_set_eq (const vidix_video_eq_t * eq) |
22850 | 1116 { |
1117 return 0; | |
1118 } | |
1119 | |
1120 /** | |
1121 * @brief Configure driver for playback. Driver should prepare BES. | |
1122 * | |
1123 * @param info configuration description for playback. | |
1124 * | |
1125 * @returns 0 in case of success. | |
1126 * -1 otherwise. | |
1127 */ | |
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1128 static int |
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1129 savage_config_playback (vidix_playback_t * vinfo) |
22850 | 1130 { |
25370 | 1131 unsigned int i, bpp; |
22850 | 1132 |
1133 if (!is_supported_fourcc (vinfo->fourcc)) | |
1134 return -1; | |
1135 | |
1136 | |
1137 | |
1138 info->src_w = vinfo->src.w; | |
1139 info->src_h = vinfo->src.h; | |
1140 | |
1141 info->drw_w = vinfo->dest.w; | |
1142 info->drw_h = vinfo->dest.h; | |
1143 | |
1144 info->wx = vinfo->dest.x; | |
1145 info->wy = vinfo->dest.y; | |
1146 info->format = vinfo->fourcc; | |
1147 | |
1148 info->lastKnownPitch = 0; | |
1149 info->brightness = 0; | |
1150 info->contrast = 128; | |
1151 info->saturation = 128; | |
1152 info->hue = 0; | |
1153 | |
1154 vinfo->offset.y = 0; | |
1155 vinfo->offset.v = 0; | |
1156 vinfo->offset.u = 0; | |
1157 | |
1158 vinfo->dest.pitch.y = 32; | |
1159 vinfo->dest.pitch.u = 32; | |
1160 vinfo->dest.pitch.v = 32; | |
1161 // vinfo->dest.pitch.u = 0; | |
1162 // vinfo->dest.pitch.v = 0; | |
1163 | |
1164 | |
1165 info->pitch = ((info->src_w << 1) + 15) & ~15; | |
1166 | |
1167 switch (vinfo->fourcc) | |
1168 { | |
25370 | 1169 case IMGFMT_Y211: |
1170 bpp = 1; | |
1171 break; | |
1172 case IMGFMT_BGR24: | |
1173 bpp = 3; | |
1174 break; | |
1175 case IMGFMT_BGR32: | |
1176 bpp = 4; | |
1177 break; | |
1178 default: | |
1179 bpp = 2; | |
1180 break; | |
1181 } | |
22850 | 1182 |
25370 | 1183 info->pitch = ((info->src_w * bpp) + 15) & ~15; |
1184 info->pitch |= ((info->pitch / bpp) << 16); | |
1185 printf("$#### destination pitch = %u\n", info->pitch & 0xffff); | |
1186 | |
1187 vinfo->frame_size = (info->pitch & 0xffff) * info->src_h; | |
1188 info->frame_size = vinfo->frame_size; | |
22850 | 1189 |
25370 | 1190 info->picture_offset = info->screen_x * info->screen_y * (info->bpp >> 3); |
1191 if (info->picture_offset > (info->chip.fbsize - vinfo->frame_size)) { | |
1192 printf("not enough memory for overlay\n"); | |
1193 return -1; | |
22850 | 1194 } |
1195 | |
25370 | 1196 if (info->chip.arch == S3_SAVAGE3D) |
1197 info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); | |
1198 else | |
1199 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
22850 | 1200 |
25370 | 1201 if (info->video_base == NULL) { |
1202 printf("errno = %s\n", strerror(errno)); | |
1203 return -1; | |
1204 } | |
22850 | 1205 |
25370 | 1206 info->picture_base = (uint32_t) info->video_base + info->picture_offset; |
1207 vinfo->dga_addr = (void*)(info->picture_base); | |
1208 vinfo->num_frames = (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1209 if(vinfo->num_frames > VID_PLAY_MAXFRAMES) vinfo->num_frames = VID_PLAY_MAXFRAMES; | |
22850 | 1210 |
25370 | 1211 for(i = 0; i < vinfo->num_frames; i++) |
1212 vinfo->offsets[i] = vinfo->frame_size * i; | |
1213 | |
22850 | 1214 return 0; |
1215 } | |
1216 | |
1217 /** | |
1218 * @brief Set playback on : driver should activate BES on this call. | |
1219 * | |
1220 * @return 0. | |
1221 */ | |
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1223 savage_playback_on (void) |
22850 | 1224 { |
1225 // FIXME: enable | |
1226 SavageDisplayVideoOld(); | |
1227 //FIXME ADD | |
1228 return 0; | |
1229 } | |
1230 | |
1231 /** | |
1232 * @brief Set playback off : driver should deactivate BES on this call. | |
1233 * | |
1234 * @return 0. | |
1235 */ | |
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1236 static int |
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1237 savage_playback_off (void) |
22850 | 1238 { |
1239 // otherwise we wont disable streams properly in new xorg | |
1240 // FIXME: shouldnt this be enabled? | |
1241 // SavageStreamsOn(); | |
1242 SavageStreamsOff(); | |
1243 // info->vidixcolorkey=0x0; | |
1244 | |
1245 // OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
1246 // SavageSetColorKeyOld(); | |
1247 //FIXME ADD | |
1248 return 0; | |
1249 } | |
1250 | |
25371 | 1251 /** |
1252 * @brief Driver should prepare and activate corresponded frame. | |
1253 * | |
1254 * @param frame the frame index. | |
1255 * | |
1256 * @return 0. | |
1257 * | |
1258 * @note This function is used only for double and triple buffering | |
1259 * and never used for single buffering playback. | |
1260 */ | |
1261 int | |
1262 savage_frame_select (unsigned int frame) | |
1263 { | |
1264 OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset | |
1265 + (info->frame_size * frame)); | |
1266 | |
1267 return 0; | |
1268 } | |
1269 | |
23057 | 1270 static void debugout(unsigned int addr, unsigned int val){ |
22850 | 1271 return ; |
1272 switch ( addr ){ | |
1273 case PSTREAM_CONTROL_REG: | |
1274 fprintf(stderr,"PSTREAM_CONTROL_REG"); | |
1275 break; | |
1276 case COL_CHROMA_KEY_CONTROL_REG: | |
1277 fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); | |
1278 break; | |
1279 case SSTREAM_CONTROL_REG: | |
1280 fprintf(stderr,"SSTREAM_CONTROL_REG"); | |
1281 break; | |
1282 case CHROMA_KEY_UPPER_BOUND_REG: | |
1283 fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); | |
1284 break; | |
1285 case SSTREAM_STRETCH_REG: | |
1286 fprintf(stderr,"SSTREAM_STRETCH_REG"); | |
1287 break; | |
1288 case COLOR_ADJUSTMENT_REG: | |
1289 fprintf(stderr,"COLOR_ADJUSTMENT_REG"); | |
1290 break; | |
1291 case BLEND_CONTROL_REG: | |
1292 fprintf(stderr,"BLEND_CONTROL_REG"); | |
1293 break; | |
1294 case PSTREAM_FBADDR0_REG: | |
1295 fprintf(stderr,"PSTREAM_FBADDR0_REG"); | |
1296 break; | |
1297 case PSTREAM_FBADDR1_REG: | |
1298 fprintf(stderr,"PSTREAM_FBADDR1_REG"); | |
1299 break; | |
1300 case PSTREAM_STRIDE_REG: | |
1301 fprintf(stderr,"PSTREAM_STRIDE_REG"); | |
1302 break; | |
1303 case DOUBLE_BUFFER_REG: | |
1304 fprintf(stderr,"DOUBLE_BUFFER_REG"); | |
1305 break; | |
1306 case SSTREAM_FBADDR0_REG: | |
1307 fprintf(stderr,"SSTREAM_FBADDR0_REG"); | |
1308 break; | |
1309 case SSTREAM_FBADDR1_REG: | |
1310 fprintf(stderr,"SSTREAM_FBADDR1_REG"); | |
1311 break; | |
1312 case SSTREAM_STRIDE_REG: | |
1313 fprintf(stderr,"SSTREAM_STRIDE_REG"); | |
1314 break; | |
1315 case SSTREAM_VSCALE_REG: | |
1316 fprintf(stderr,"SSTREAM_VSCALE_REG"); | |
1317 break; | |
1318 case SSTREAM_VINITIAL_REG: | |
1319 fprintf(stderr,"SSTREAM_VINITIAL_REG"); | |
1320 break; | |
1321 case SSTREAM_LINES_REG: | |
1322 fprintf(stderr,"SSTREAM_LINES_REG"); | |
1323 break; | |
1324 case STREAMS_FIFO_REG: | |
1325 fprintf(stderr,"STREAMS_FIFO_REG"); | |
1326 break; | |
1327 case PSTREAM_WINDOW_START_REG: | |
1328 fprintf(stderr,"PSTREAM_WINDOW_START_REG"); | |
1329 break; | |
1330 case PSTREAM_WINDOW_SIZE_REG: | |
1331 fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); | |
1332 break; | |
1333 case SSTREAM_WINDOW_START_REG: | |
1334 fprintf(stderr,"SSTREAM_WINDOW_START_REG"); | |
1335 break; | |
1336 case SSTREAM_WINDOW_SIZE_REG: | |
1337 fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); | |
1338 break; | |
1339 case FIFO_CONTROL: | |
1340 fprintf(stderr,"FIFO_CONTROL"); | |
1341 break; | |
1342 case PSTREAM_FBSIZE_REG: | |
1343 fprintf(stderr,"PSTREAM_FBSIZE_REG"); | |
1344 break; | |
1345 case SSTREAM_FBSIZE_REG: | |
1346 fprintf(stderr,"SSTREAM_FBSIZE_REG"); | |
1347 break; | |
1348 case SSTREAM_FBADDR2_REG: | |
1349 fprintf(stderr,"SSTREAM_FBADDR2_REG"); | |
1350 break; | |
1351 | |
1352 } | |
1353 fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); | |
1354 } | |
1355 | |
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1356 VDXDriver savage_drv = { |
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1357 "savage", |
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1358 NULL, |
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1359 .probe = savage_probe, |
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1360 .get_caps = savage_get_caps, |
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1361 .query_fourcc = savage_query_fourcc, |
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1362 .init = savage_init, |
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1363 .destroy = savage_destroy, |
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1364 .config_playback = savage_config_playback, |
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1365 .playback_on = savage_playback_on, |
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1366 .playback_off = savage_playback_off, |
25371 | 1367 .frame_sel = savage_frame_select, |
22857
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1368 .get_eq = savage_get_eq, |
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1369 .set_eq = savage_set_eq, |
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1370 .set_gkey = savage_set_gkeys, |
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1371 }; |