Mercurial > mplayer.hg
annotate vidix/savage_vid.c @ 23510:a6c619ee9d30
Teletext support for tv:// (v4l and v4l2 only)
modified patch from Otvos Attila oattila at chello dot hu
Module uses zvbi library for all low-level VBI operations (like I/O with vbi
device, converting vbi pages into usefull vbi_page stuctures, rendering them
into RGB32 images).
All teletext related stuff (except properties, slave commands and rendering
osd in text mode or RGB32 rendered teletext pages in spu mode) is implemented
in tvi_vbi.c
New properties:
teletext_page - switching between pages
teletext_mode - switch between on/off/opaque/transparent modes
teletext_format - (currently read-only) allows to get format info
(black/white,gray,text)
teletext_half_page - trivial zooming (displaying top/bottom half of teletext
page)
New slave commands:
teletext_add_dec - user interface for jumping to any page by editing page number
interactively
teletext_go_link - goes though links, specified on current page
author | voroshil |
---|---|
date | Sun, 10 Jun 2007 00:06:12 +0000 |
parents | 91ad6d4d6a54 |
children | e5bdf17ce399 |
rev | line source |
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22850 | 1 /* |
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2 * VIDIX driver for S3 Savage chipsets. |
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3 * Copyright (C) 2004 Reza Jelveh |
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4 * |
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5 * This file is part of MPlayer. |
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6 * |
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7 * MPlayer is free software; you can redistribute it and/or modify |
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8 * it under the terms of the GNU General Public License as published by |
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9 * the Free Software Foundation; either version 2 of the License, or |
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10 * (at your option) any later version. |
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11 * |
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12 * MPlayer is distributed in the hope that it will be useful, |
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 * GNU General Public License for more details. |
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16 * |
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17 * You should have received a copy of the GNU General Public License |
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18 * along with MPlayer; if not, write to the Free Software |
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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20 * |
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21 * Thanks to Alex Deucher for Support |
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22 */ |
22850 | 23 |
24 #include <errno.h> | |
25 #include <stdio.h> | |
26 #include <stdlib.h> | |
27 #include <string.h> | |
28 #include <inttypes.h> | |
29 #include <unistd.h> | |
30 #include <math.h> | |
31 | |
32 #include "vidix.h" | |
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33 #include "vidixlib.h" |
22850 | 34 #include "fourcc.h" |
22901 | 35 #include "dha.h" |
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36 #include "pci_ids.h" |
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37 #include "pci_names.h" |
22905 | 38 #include "config.h" |
22850 | 39 |
40 #include "savage_regs.h" | |
41 | |
42 | |
43 #define VF_STREAMS_ON 0x0001 | |
44 #define BASE_PAD 0xf | |
45 #define FRAMEBUFFER_SIZE 1024*2000*4 | |
46 /************************************** | |
47 S3 streams processor | |
48 **************************************/ | |
49 | |
50 #define EXT_MISC_CTRL2 0x67 | |
51 | |
52 /* New streams */ | |
53 | |
54 /* CR67[2] = 1 : enable stream 1 */ | |
55 #define ENABLE_STREAM1 0x04 | |
56 /* CR67[1] = 1 : enable stream 2 */ | |
57 #define ENABLE_STREAM2 0x02 | |
58 /* mask to clear CR67[2,1] */ | |
59 #define NO_STREAMS 0xF9 | |
60 /* CR67[3] = 1 : Mem-mapped regs */ | |
61 #define USE_MM_FOR_PRI_STREAM 0x08 | |
62 | |
63 #define HDM_SHIFT 16 | |
64 #define HDSCALE_4 (2 << HDM_SHIFT) | |
65 #define HDSCALE_8 (3 << HDM_SHIFT) | |
66 #define HDSCALE_16 (4 << HDM_SHIFT) | |
67 #define HDSCALE_32 (5 << HDM_SHIFT) | |
68 #define HDSCALE_64 (6 << HDM_SHIFT) | |
69 | |
70 /* Old Streams */ | |
71 | |
72 #define ENABLE_STREAMS_OLD 0x0c | |
73 #define NO_STREAMS_OLD 0xf3 | |
74 /* CR69[0] = 1 : Mem-mapped regs */ | |
75 #define USE_MM_FOR_PRI_STREAM_OLD 0x01 | |
76 | |
23057 | 77 static void SavageStreamsOn(void); |
22850 | 78 |
79 /* | |
80 * There are two different streams engines used in the Savage line. | |
81 * The old engine is in the 3D, 4, Pro, and Twister. | |
82 * The new engine is in the 2000, MX, IX, and Super. | |
83 */ | |
84 | |
85 | |
86 /* streams registers for old engine */ | |
87 #define PSTREAM_CONTROL_REG 0x8180 | |
88 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 | |
89 #define SSTREAM_CONTROL_REG 0x8190 | |
90 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 | |
91 #define SSTREAM_STRETCH_REG 0x8198 | |
92 #define COLOR_ADJUSTMENT_REG 0x819C | |
93 #define BLEND_CONTROL_REG 0x81A0 | |
94 #define PSTREAM_FBADDR0_REG 0x81C0 | |
95 #define PSTREAM_FBADDR1_REG 0x81C4 | |
96 #define PSTREAM_STRIDE_REG 0x81C8 | |
97 #define DOUBLE_BUFFER_REG 0x81CC | |
98 #define SSTREAM_FBADDR0_REG 0x81D0 | |
99 #define SSTREAM_FBADDR1_REG 0x81D4 | |
100 #define SSTREAM_STRIDE_REG 0x81D8 | |
101 #define SSTREAM_VSCALE_REG 0x81E0 | |
102 #define SSTREAM_VINITIAL_REG 0x81E4 | |
103 #define SSTREAM_LINES_REG 0x81E8 | |
104 #define STREAMS_FIFO_REG 0x81EC | |
105 #define PSTREAM_WINDOW_START_REG 0x81F0 | |
106 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 | |
107 #define SSTREAM_WINDOW_START_REG 0x81F8 | |
108 #define SSTREAM_WINDOW_SIZE_REG 0x81FC | |
109 #define FIFO_CONTROL 0x8200 | |
110 #define PSTREAM_FBSIZE_REG 0x8300 | |
111 #define SSTREAM_FBSIZE_REG 0x8304 | |
112 #define SSTREAM_FBADDR2_REG 0x8308 | |
113 | |
114 #define OS_XY(x,y) (((x+1)<<16)|(y+1)) | |
115 #define OS_WH(x,y) (((x-1)<<16)|(y)) | |
116 | |
117 #define PCI_COMMAND_MEM 0x2 | |
118 #define MAX_FRAMES 3 | |
119 /** | |
120 * @brief Information on PCI device. | |
121 */ | |
23057 | 122 static pciinfo_t pci_info; |
22850 | 123 |
124 #define outb(reg,val) OUTPORT8(reg,val) | |
125 #define inb(reg) INPORT8(reg) | |
126 #define outw(reg,val) OUTPORT16(reg,val) | |
127 #define inw(reg) INPORT16(reg) | |
128 #define outl(reg,val) OUTPORT32(reg,val) | |
129 #define inl(reg) INPORT32(reg) | |
130 | |
131 | |
132 /* | |
133 * PCI-Memory IO access macros. | |
134 */ | |
135 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
136 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
137 | |
138 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
139 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
140 | |
141 #ifndef USE_RMW_CYCLES | |
142 /* | |
143 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
144 */ | |
145 | |
146 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
147 | |
148 #undef VID_WR08 | |
149 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
150 #undef VID_RD08 | |
151 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
152 | |
153 #undef VID_WR16 | |
154 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) | |
155 #undef VID_RD16 | |
156 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) | |
157 | |
158 #undef VID_WR32 | |
159 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
160 #undef VID_RD32 | |
161 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
162 #endif /* USE_RMW_CYCLES */ | |
163 | |
164 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
165 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
166 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
167 | |
168 | |
169 /* from x driver */ | |
170 | |
171 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) | |
172 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) | |
173 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) | |
174 | |
175 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) | |
176 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) | |
177 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) | |
178 | |
179 #define INREG(addr) VID_RD32(info->control_base, addr) | |
180 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) | |
181 #define INREG8(addr) VID_RD08(info->control_base, addr) | |
182 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) | |
183 #define INREG16(addr) VID_RD16(info->control_base, addr) | |
184 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) | |
185 | |
186 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) | |
187 | |
188 | |
23057 | 189 static void debugout(unsigned int addr, unsigned int val); |
22850 | 190 |
191 | |
192 struct savage_chip { | |
193 volatile uint32_t *PMC; /* general control */ | |
194 volatile uint32_t *PME; /* multimedia port */ | |
195 volatile uint32_t *PFB; /* framebuffer control */ | |
196 volatile uint32_t *PVIDEO; /* overlay control */ | |
197 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
198 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
199 volatile uint32_t *PRAMIN; /* instance memory */ | |
200 volatile uint32_t *PRAMHT; /* hash table */ | |
201 volatile uint32_t *PRAMFC; /* fifo context table */ | |
202 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
203 volatile uint32_t *PFIFO; /* fifo control region */ | |
204 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
205 volatile uint32_t *PGRAPH; /* graphics engine */ | |
206 | |
207 int arch; /* compatible NV_ARCH_XX define */ | |
208 unsigned long fbsize; /* framebuffer size */ | |
209 void (* lock) (struct savage_chip *, int); | |
210 }; | |
211 typedef struct savage_chip savage_chip; | |
212 | |
213 | |
214 struct savage_info { | |
215 unsigned int use_colorkey; | |
216 unsigned int colorkey; /* saved xv colorkey*/ | |
217 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
218 unsigned int depth; | |
219 unsigned int bpp; | |
220 unsigned int videoFlags; | |
221 unsigned int format; | |
222 unsigned int pitch; | |
223 unsigned int blendBase; | |
224 unsigned int lastKnownPitch; | |
225 unsigned int displayWidth, displayHeight; | |
226 unsigned int brightness,hue,saturation,contrast; | |
227 unsigned int src_w,src_h; | |
228 unsigned int drw_w,drw_h; /*scaled width && height*/ | |
229 unsigned int wx,wy; /*window x && y*/ | |
230 unsigned int screen_x; /*screen width*/ | |
231 unsigned int screen_y; /*screen height*/ | |
232 unsigned long buffer_size; /* size of the image buffer */ | |
233 struct savage_chip chip; /* NV architecture structure */ | |
234 void* video_base; /* virtual address of control region */ | |
235 void* control_base; /* virtual address of fb region */ | |
236 unsigned long picture_base; /* direct pointer to video picture */ | |
237 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
238 // struct savage_dma dma; /* DMA structure */ | |
239 unsigned int cur_frame; | |
240 unsigned int num_frames; /* number of buffers */ | |
241 int bps; /* bytes per line */ | |
242 void (*SavageWaitIdle) (); | |
243 void (*SavageWaitFifo) (int space); | |
244 }; | |
245 typedef struct savage_info savage_info; | |
246 | |
247 | |
248 static savage_info* info; | |
249 | |
250 | |
251 /** | |
252 * @brief Unichrome driver vidix capabilities. | |
253 */ | |
254 static vidix_capability_t savage_cap = { | |
255 "Savage/ProSavage/Twister vidix", | |
256 "Reza Jelveh <reza.jelveh@tuhh.de>", | |
257 TYPE_OUTPUT, | |
258 {0, 0, 0, 0}, | |
259 4096, | |
260 4096, | |
261 4, | |
262 4, | |
263 -1, | |
264 FLAG_UPSCALER | FLAG_DOWNSCALER, | |
265 VENDOR_S3_INC, | |
266 -1, | |
267 {0, 0, 0, 0} | |
268 }; | |
269 | |
270 struct savage_cards { | |
271 unsigned short chip_id; | |
272 unsigned short arch; | |
273 }; | |
274 | |
275 | |
276 static | |
277 unsigned int GetBlendForFourCC( int id ) | |
278 { | |
279 switch( id ) { | |
280 case IMGFMT_YUY2: | |
281 case IMGFMT_YV12: | |
282 case IMGFMT_I420: | |
283 return 1; | |
284 case IMGFMT_Y211: | |
285 return 4; | |
286 case IMGFMT_RGB15: | |
287 return 3; | |
288 case IMGFMT_RGB16: | |
289 return 5; | |
290 default: | |
291 return 0; | |
292 } | |
293 } | |
294 | |
295 /** | |
296 * @brief list of card IDs compliant with the Unichrome driver . | |
297 */ | |
298 static struct savage_cards savage_card_ids[] = { | |
299 /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ | |
300 { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, | |
301 /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ | |
302 { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, | |
303 /*ProSavage DDR*/ | |
304 { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, | |
305 /*[ProSavageDDR P4M266 K] */ | |
306 { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, | |
307 }; | |
308 | |
309 static void SavageSetColorOld(void) | |
310 { | |
311 | |
312 | |
313 if( | |
314 (info->format == IMGFMT_RGB15) || | |
315 (info->format == IMGFMT_RGB16) | |
316 ) | |
317 { | |
318 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
319 } | |
320 else | |
321 { | |
322 /* Change 0..255 into 0..15 */ | |
323 long sat = info->saturation * 16 / 256; | |
324 double hue = info->hue * 0.017453292; | |
325 unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; | |
326 unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; | |
327 | |
328 OUTREG( COLOR_ADJUSTMENT_REG, | |
329 0x80008000 | | |
330 (info->brightness + 128) | | |
331 ((info->contrast & 0xf8) << (12-7)) | | |
332 (hs1 << 16) | | |
333 (hs2 << 24) | |
334 ); | |
335 debugout( COLOR_ADJUSTMENT_REG, | |
336 0x80008000 | | |
337 (info->brightness + 128) | | |
338 ((info->contrast & 0xf8) << (12-7)) | | |
339 (hs1 << 16) | | |
340 (hs2 << 24) | |
341 ); | |
342 | |
343 } | |
344 } | |
345 | |
346 static void SavageSetColorKeyOld(void) | |
347 { | |
348 int red, green, blue; | |
349 | |
350 /* Here, we reset the colorkey and all the controls. */ | |
351 | |
352 red = (info->vidixcolorkey & 0x00FF0000) >> 16; | |
353 green = (info->vidixcolorkey & 0x0000FF00) >> 8; | |
354 blue = info->vidixcolorkey & 0x000000FF; | |
355 | |
356 if( !info->vidixcolorkey ) { | |
357 printf("SavageSetColorKey disabling colorkey\n"); | |
358 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
359 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
360 OUTREG( BLEND_CONTROL_REG, 0 ); | |
361 } | |
362 else { | |
363 switch (info->depth) { | |
364 // FIXME: isnt fixed yet | |
365 case 8: | |
366 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
367 0x37000000 | (info->vidixcolorkey & 0xFF) ); | |
368 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
369 0x00000000 | (info->vidixcolorkey & 0xFF) ); | |
370 break; | |
371 case 15: | |
372 /* 15 bpp 555 */ | |
373 red&=0x1f; | |
374 green&=0x1f; | |
375 blue&=0x1f; | |
376 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
377 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
378 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
379 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
380 break; | |
381 case 16: | |
382 /* 16 bpp 565 */ | |
383 red&=0x1f; | |
384 green&=0x3f; | |
385 blue&=0x1f; | |
386 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
387 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); | |
388 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
389 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); | |
390 break; | |
391 case 24: | |
392 /* 24 bpp 888 */ | |
393 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
394 0x17000000 | (red<<16) | (green<<8) | (blue) ); | |
395 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
396 0x00000000 | (red<<16) | (green<<8) | (blue) ); | |
397 break; | |
398 } | |
399 | |
400 /* We use destination colorkey */ | |
401 OUTREG( BLEND_CONTROL_REG, 0x05000000 ); | |
402 } | |
403 } | |
404 | |
405 | |
406 static void | |
407 SavageDisplayVideoOld(void) | |
408 { | |
409 int vgaCRIndex, vgaCRReg, vgaIOBase; | |
410 unsigned int ssControl; | |
411 int cr92; | |
412 | |
413 | |
414 vgaIOBase = 0x3d0; | |
415 vgaCRIndex = vgaIOBase + 4; | |
416 vgaCRReg = vgaIOBase + 5; | |
417 | |
418 // if( psav->videoFourCC != id ) | |
419 // SavageStreamsOff(pScrn); | |
420 | |
421 if( !info->videoFlags & VF_STREAMS_ON ) | |
422 { | |
423 SavageStreamsOn(); | |
424 // SavageResetVideo(); | |
425 SavageSetColorOld(); | |
426 SavageSetColorKeyOld(); | |
427 } | |
428 | |
429 | |
430 | |
431 | |
432 /* Set surface format. */ | |
433 | |
434 OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
435 | |
436 debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
437 | |
438 /* Calculate horizontal scale factor. */ | |
439 | |
440 //FIXME: enable scaling | |
441 OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); | |
442 // debugout(SSTREAM_STRETCH_REG, 1 << 15); | |
443 | |
444 OUTREG(SSTREAM_LINES_REG, info->src_h ); | |
445 debugout(SSTREAM_LINES_REG, info->src_h ); | |
446 | |
447 | |
448 OUTREG(SSTREAM_VINITIAL_REG, 0 ); | |
449 debugout(SSTREAM_VINITIAL_REG, 0 ); | |
450 /* Calculate vertical scale factor. */ | |
451 | |
452 // OUTREG(SSTREAM_VSCALE_REG, 1 << 15); | |
453 OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
454 debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
455 // OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); | |
456 | |
457 /* Set surface location and stride. */ | |
458 | |
459 OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
460 debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
461 | |
462 OUTREG(SSTREAM_FBADDR1_REG, 0 ); | |
463 debugout(SSTREAM_FBADDR1_REG, 0 ); | |
464 | |
465 OUTREG(SSTREAM_STRIDE_REG, info->pitch ); | |
466 debugout(SSTREAM_STRIDE_REG, info->pitch ); | |
467 | |
468 OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
469 debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
470 OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
471 debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
472 | |
473 | |
474 | |
475 ssControl = 0; | |
476 | |
477 if( info->src_w > (info->drw_w << 1) ) | |
478 { | |
479 /* BUGBUG shouldn't this be >=? */ | |
480 if( info->src_w <= (info->drw_w << 2) ) | |
481 ssControl |= HDSCALE_4; | |
482 else if( info->src_w > (info->drw_w << 3) ) | |
483 ssControl |= HDSCALE_8; | |
484 else if( info->src_w > (info->drw_w << 4) ) | |
485 ssControl |= HDSCALE_16; | |
486 else if( info->src_w > (info->drw_w << 5) ) | |
487 ssControl |= HDSCALE_32; | |
488 else if( info->src_w > (info->drw_w << 6) ) | |
489 ssControl |= HDSCALE_64; | |
490 } | |
491 | |
492 ssControl |= info->src_w; | |
493 ssControl |= (1 << 24); | |
494 | |
495 //FIXME: enable scaling | |
496 OUTREG(SSTREAM_CONTROL_REG, ssControl); | |
497 debugout(SSTREAM_CONTROL_REG, ssControl); | |
498 | |
499 // FIXME: this should actually be enabled | |
500 | |
501 info->pitch = (info->pitch + 7) / 8; | |
502 VGAOUT8(vgaCRIndex, 0x92); | |
503 cr92 = VGAIN8(vgaCRReg); | |
504 VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); | |
505 VGAOUT8(vgaCRIndex, 0x93); | |
506 VGAOUT8(vgaCRReg, info->pitch); | |
507 OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); | |
508 | |
509 | |
510 | |
511 | |
512 } | |
513 | |
514 static void SavageInitStreamsOld(void) | |
515 { | |
516 /*unsigned long jDelta;*/ | |
517 unsigned long format = 0; | |
518 | |
519 /* | |
520 * For the OLD streams engine, several of these registers | |
521 * cannot be touched unless streams are on. Seems backwards to me; | |
522 * I'd want to set 'em up, then cut 'em loose. | |
523 */ | |
524 | |
525 | |
526 /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ | |
527 switch( info->depth ) { | |
528 case 8: format = 0 << 24; break; | |
529 case 15: format = 3 << 24; break; | |
530 case 16: format = 5 << 24; break; | |
531 case 24: format = 7 << 24; break; | |
532 } | |
533 #warning enable this again | |
534 OUTREG(PSTREAM_FBSIZE_REG, | |
535 info->screen_y * info->screen_x * (info->bpp >> 3)); | |
536 | |
537 OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); | |
538 OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); | |
539 OUTREG( PSTREAM_FBADDR1_REG, 0 ); | |
540 /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ | |
541 OUTREG( PSTREAM_CONTROL_REG, format ); | |
542 OUTREG( PSTREAM_FBADDR0_REG, 0 ); | |
543 | |
544 /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ | |
545 | |
546 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
547 OUTREG( SSTREAM_CONTROL_REG, 0 ); | |
548 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
549 OUTREG( SSTREAM_STRETCH_REG, 0 ); | |
550 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
551 OUTREG( BLEND_CONTROL_REG, 1 << 24 ); | |
552 OUTREG( DOUBLE_BUFFER_REG, 0 ); | |
553 OUTREG( SSTREAM_FBADDR0_REG, 0 ); | |
554 OUTREG( SSTREAM_FBADDR1_REG, 0 ); | |
555 OUTREG( SSTREAM_FBADDR2_REG, 0 ); | |
556 OUTREG( SSTREAM_FBSIZE_REG, 0 ); | |
557 OUTREG( SSTREAM_STRIDE_REG, 0 ); | |
558 OUTREG( SSTREAM_VSCALE_REG, 0 ); | |
559 OUTREG( SSTREAM_LINES_REG, 0 ); | |
560 OUTREG( SSTREAM_VINITIAL_REG, 0 ); | |
561 #warning is this needed? | |
562 OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
563 OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); | |
564 | |
565 } | |
566 | |
23057 | 567 static void |
22850 | 568 SavageStreamsOn(void) |
569 { | |
570 unsigned char jStreamsControl; | |
571 unsigned short vgaCRIndex = 0x3d0 + 4; | |
572 unsigned short vgaCRReg = 0x3d0 + 5; | |
573 | |
574 // xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); | |
575 | |
576 /* Sequence stolen from streams.c in M7 NT driver */ | |
577 | |
578 | |
579 enable_app_io (); | |
580 | |
581 /* Unlock extended registers. */ | |
582 | |
583 /* FIXME: it looks like mmaped io is broken with vgaout16 */ | |
584 VGAOUT16(vgaCRIndex, 0x4838 ); | |
585 VGAOUT16(vgaCRIndex, 0xa039); | |
586 VGAOUT16(0x3c4, 0x0608); | |
587 | |
588 | |
589 | |
590 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
591 | |
592 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) | |
593 { | |
594 // SavageInitStreamsNew( pScrn ); | |
595 | |
596 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
597 | |
598 /* Wait for VBLANK. */ | |
599 VerticalRetraceWait(); | |
600 /* Fire up streams! */ | |
601 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
602 /* These values specify brightness, contrast, saturation and hue. */ | |
603 OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); | |
604 OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); | |
605 OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); | |
606 } | |
607 else if (info->chip.arch == S3_SAVAGE2000) | |
608 { | |
609 // SavageInitStreams2000( pScrn ); | |
610 | |
611 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
612 | |
613 /* Wait for VBLANK. */ | |
614 VerticalRetraceWait(); | |
615 /* Fire up streams! */ | |
616 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
617 /* These values specify brightness, contrast, saturation and hue. */ | |
618 OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); | |
619 OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); | |
620 OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); | |
621 OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); | |
622 } | |
623 else | |
624 { | |
625 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; | |
626 | |
627 /* Wait for VBLANK. */ | |
628 | |
629 VerticalRetraceWait(); | |
630 | |
631 /* Fire up streams! */ | |
632 | |
633 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
634 | |
635 SavageInitStreamsOld( ); | |
636 } | |
637 | |
638 /* Wait for VBLANK. */ | |
639 | |
640 VerticalRetraceWait(); | |
641 | |
642 /* Turn on secondary stream TV flicker filter, once we support TV. */ | |
643 | |
644 /* SR70 |= 0x10 */ | |
645 | |
646 info->videoFlags |= VF_STREAMS_ON; | |
647 | |
648 } | |
649 | |
650 | |
651 | |
652 | |
653 static void savage_getscreenproperties(struct savage_info *info){ | |
654 unsigned char bpp=0; | |
655 | |
656 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; | |
657 | |
658 vgaIOBase = 0x3d0; | |
659 vgaCRIndex = vgaIOBase + 4; | |
660 vgaCRReg = vgaIOBase + 5; | |
661 | |
662 | |
663 /* a little reversed from x driver source code */ | |
664 VGAOUT8(vgaCRIndex, 0x67); | |
665 bpp = VGAIN8(vgaCRReg); | |
666 | |
667 | |
668 switch (bpp&0xf0) { | |
669 case 0x00: | |
670 case 0x10: | |
671 info->depth=8; | |
672 info->bpp=8; | |
673 break; | |
674 case 0x20: | |
675 case 0x30: | |
676 info->depth=15; | |
677 info->bpp=16; | |
678 break; | |
679 case 0x40: | |
680 case 0x50: | |
681 info->depth=16; | |
682 info->bpp=16; | |
683 break; | |
684 case 0x70: | |
685 case 0xd0: | |
686 info->depth=24; | |
687 info->bpp=32; | |
688 break; | |
689 | |
690 | |
691 } | |
692 | |
693 | |
694 VGAOUT8(vgaCRIndex, 0x1); | |
695 info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; | |
696 /*get screen height*/ | |
697 /* get first 8 bits in VT_DISPLAY_END*/ | |
698 VGAOUT8(0x03D4, 0x12); | |
699 info->screen_y = VGAIN8(0x03D5); | |
700 VGAOUT8(0x03D4,0x07); | |
701 /* get 9th bit in CRTC_OVERFLOW*/ | |
702 info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; | |
703 /* and the 10th in CRTC_OVERFLOW*/ | |
704 info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; | |
705 ++info->screen_y; | |
706 | |
707 printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); | |
708 } | |
709 | |
710 | |
711 static void SavageStreamsOff(void) | |
712 { | |
713 unsigned char jStreamsControl; | |
714 unsigned short vgaCRIndex = 0x3d0 + 4; | |
715 unsigned short vgaCRReg = 0x3d0 + 5; | |
716 | |
717 | |
718 /* Unlock extended registers. */ | |
719 | |
720 VGAOUT16(vgaCRIndex, 0x4838); | |
721 VGAOUT16(vgaCRIndex, 0xa039); | |
722 VGAOUT16(0x3c4, 0x0608); | |
723 | |
724 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
725 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || | |
726 (info->chip.arch == S3_SUPERSAVAGE) || | |
727 (info->chip.arch == S3_SAVAGE2000) ) | |
728 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; | |
729 else | |
730 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; | |
731 | |
732 /* Wait for VBLANK. */ | |
733 | |
734 VerticalRetraceWait(); | |
735 | |
736 /* Kill streams. */ | |
737 | |
738 VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
739 | |
740 VGAOUT16(vgaCRIndex, 0x0093 ); | |
741 VGAOUT8( vgaCRIndex, 0x92 ); | |
742 VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); | |
743 | |
744 info->videoFlags &= ~VF_STREAMS_ON; | |
745 } | |
746 | |
747 /** | |
748 * @brief Find chip index in Unichrome compliant devices list. | |
749 * | |
750 * @param chip_id PCI device ID. | |
751 * | |
752 * @returns index position in savage_card_ids if successful. | |
753 * -1 if chip_id is not a compliant chipset ID. | |
754 */ | |
755 | |
756 static int find_chip(unsigned chip_id){ | |
757 unsigned i; | |
758 for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) | |
759 { | |
760 if(chip_id == savage_card_ids[i].chip_id)return i; | |
761 } | |
762 return -1; | |
763 } | |
764 | |
765 /** | |
766 * @brief Probe hardware to find some useable chipset. | |
767 * | |
768 * @param verbose specifies verbose level. | |
769 * @param force specifies force mode : driver should ignore | |
770 * device_id (danger but useful for new devices) | |
771 * | |
772 * @returns 0 if it can handle something in PC. | |
773 * a negative error code otherwise. | |
774 */ | |
775 | |
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776 static int savage_probe(int verbose, int force){ |
22850 | 777 pciinfo_t lst[MAX_PCI_DEVICES]; |
778 unsigned i,num_pci; | |
779 int err; | |
780 | |
781 if (force) | |
782 printf("[savage_vid]: warning: forcing not supported yet!\n"); | |
783 err = pci_scan(lst,&num_pci); | |
784 if(err){ | |
785 printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
786 return err; | |
787 } | |
788 else { | |
789 err = ENXIO; | |
790 for(i=0; i < num_pci; i++){ | |
791 if(lst[i].vendor == VENDOR_S3_INC) { | |
792 int idx; | |
793 const char *dname; | |
794 idx = find_chip(lst[i].device); | |
795 if(idx == -1) | |
796 continue; | |
797 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
798 dname = dname ? dname : "Unknown chip"; | |
799 printf("[savage_vid] Found chip: %s\n", dname); | |
800 // FIXME: whats wrong here? | |
801 if ((lst[i].command & PCI_COMMAND_IO ) == 0){ | |
802 printf("[savage_vid] Device is disabled, ignoring\n"); | |
803 continue; | |
804 } | |
805 savage_cap.device_id = lst[i].device; | |
806 err = 0; | |
807 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
808 break; | |
809 } | |
810 } | |
811 } | |
812 if(err && verbose) printf("[savage_vid] Can't find chip\n"); | |
813 return err; | |
814 } | |
815 | |
816 /** | |
817 * @brief Initializes driver. | |
818 * | |
819 * @returns 0 if ok. | |
820 * a negative error code otherwise. | |
821 */ | |
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822 static int |
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823 savage_init (void) |
22850 | 824 { |
825 int mtrr; | |
22868 | 826 unsigned char config1, tmp; |
22850 | 827 |
828 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; | |
829 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; | |
830 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; | |
831 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; | |
832 | |
22868 | 833 int videoRam; |
22850 | 834 |
835 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; | |
836 | |
837 unsigned char val; | |
838 | |
839 vgaIOBase = 0x3d0; | |
840 vgaCRIndex = vgaIOBase + 4; | |
841 vgaCRReg = vgaIOBase + 5; | |
842 | |
843 fprintf(stderr, "vixInit enter \n"); | |
844 // //getc(stdin); | |
845 | |
846 info = calloc(1,sizeof(savage_info)); | |
847 | |
848 | |
849 /* need this if we want direct outb and inb access? */ | |
850 enable_app_io (); | |
851 | |
852 /* 12mb + 32kb ? */ | |
853 /* allocate some space for control registers */ | |
854 info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; | |
855 | |
856 if (info->chip.arch == S3_SAVAGE3D) { | |
857 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); | |
858 } | |
859 else { | |
860 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); | |
861 } | |
862 | |
863 // info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); | |
864 | |
865 // FIXME: enable mmio? | |
866 val = VGAIN8 (0x3c3); | |
867 VGAOUT8 (0x3c3, val | 0x01); | |
868 val = VGAIN8 (0x3cc); | |
869 VGAOUT8 (0x3c2, val | 0x01); | |
870 | |
871 if (info->chip.arch >= S3_SAVAGE4) | |
872 { | |
873 VGAOUT8 (0x3d4, 0x40); | |
874 val = VGAIN8 (0x3d5); | |
875 VGAOUT8 (0x3d5, val | 1); | |
876 } | |
877 | |
878 | |
879 | |
880 /* unprotect CRTC[0-7] */ | |
881 VGAOUT8(vgaCRIndex, 0x11); | |
882 tmp = VGAIN8(vgaCRReg); | |
883 // printf("$########## tmp = %d\n",tmp); | |
884 VGAOUT8(vgaCRReg, tmp & 0x7f); | |
885 | |
886 | |
887 /* unlock extended regs */ | |
888 VGAOUT16(vgaCRIndex, 0x4838); | |
889 VGAOUT16(vgaCRIndex, 0xa039); | |
890 VGAOUT16(0x3c4, 0x0608); | |
891 | |
892 VGAOUT8(vgaCRIndex, 0x40); | |
893 tmp = VGAIN8(vgaCRReg); | |
894 VGAOUT8(vgaCRReg, tmp & ~0x01); | |
895 | |
896 /* unlock sys regs */ | |
897 VGAOUT8(vgaCRIndex, 0x38); | |
898 VGAOUT8(vgaCRReg, 0x48); | |
899 | |
900 /* Unlock system registers. */ | |
901 VGAOUT16(vgaCRIndex, 0x4838); | |
902 | |
903 /* Next go on to detect amount of installed ram */ | |
904 | |
905 VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ | |
906 config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ | |
907 | |
908 | |
909 switch( info->chip.arch ) { | |
910 case S3_SAVAGE3D: | |
911 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; | |
912 break; | |
913 | |
914 case S3_SAVAGE4: | |
915 /* | |
916 * The Savage4 has one ugly special case to consider. On | |
917 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB | |
918 * when it really means 8MB. Why do it the same when you | |
919 * can do it different... | |
920 */ | |
921 VGAOUT8(0x3d4, 0x68); /* memory control 1 */ | |
922 if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) | |
923 RamSavage4[1] = 8; | |
924 | |
925 /*FALLTHROUGH*/ | |
926 | |
927 case S3_SAVAGE2000: | |
928 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; | |
929 break; | |
930 | |
931 case S3_SAVAGE_MX: | |
932 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; | |
933 break; | |
934 | |
935 case S3_PROSAVAGE: | |
936 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; | |
937 break; | |
938 | |
939 default: | |
940 /* How did we get here? */ | |
941 videoRam = 0; | |
942 break; | |
943 } | |
944 | |
945 | |
946 printf("###### videoRam = %d\n",videoRam); | |
947 info->chip.fbsize = videoRam * 1024; | |
948 | |
949 | |
950 /* reset graphics engine to avoid memory corruption */ | |
951 /* VGAOUT8 (0x3d4, 0x66); | |
952 cr66 = VGAIN8 (0x3d5); | |
953 VGAOUT8 (0x3d5, cr66 | 0x02); | |
954 udelay (10000); | |
955 | |
956 VGAOUT8 (0x3d4, 0x66); | |
22868 | 957 VGAOUT8 (0x3d5, cr66 & ~0x02); */ // clear reset flag |
22850 | 958 /* udelay (10000); */ |
959 | |
960 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
961 if (info->chip.arch == S3_SAVAGE3D) { | |
962 info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); | |
963 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
964 } | |
965 else { | |
966 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
967 info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; | |
968 // info->picture_offset = 1024*1024* 4 * 2; | |
969 } | |
22868 | 970 if ( info->video_base == NULL){ |
22850 | 971 printf("errno = %s\n", strerror(errno)); |
972 return -1; | |
973 } | |
974 | |
975 | |
976 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
977 | |
978 if ( info->chip.arch == S3_SAVAGE3D ){ | |
979 mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
980 } | |
981 else{ | |
982 mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
983 } | |
984 | |
985 if (mtrr!= 0) | |
986 printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
987 else | |
988 printf("[savage_vid] MTRR set up\n"); | |
989 | |
990 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
991 | |
992 | |
993 savage_getscreenproperties(info); | |
994 // return -1; | |
995 info->videoFlags = 0; | |
996 | |
997 SavageStreamsOn(); | |
998 //getc(stdin); | |
999 //FIXME ADD | |
1000 return 0; | |
1001 } | |
1002 | |
1003 /** | |
1004 * @brief Destroys driver. | |
1005 */ | |
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1006 static void |
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1007 savage_destroy (void) |
22850 | 1008 { |
1009 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
1010 unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); | |
1011 //FIXME ADD | |
1012 } | |
1013 | |
1014 /** | |
1015 * @brief Get chipset's hardware capabilities. | |
1016 * | |
1017 * @param to Pointer to the vidix_capability_t structure to be filled. | |
1018 * | |
1019 * @returns 0. | |
1020 */ | |
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1021 static int |
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1022 savage_get_caps (vidix_capability_t * to) |
22850 | 1023 { |
1024 memcpy (to, &savage_cap, sizeof (vidix_capability_t)); | |
1025 return 0; | |
1026 } | |
1027 | |
1028 /** | |
1029 * @brief Report if the video FourCC is supported by hardware. | |
1030 * | |
1031 * @param fourcc input image format. | |
1032 * | |
1033 * @returns 1 if the fourcc is supported. | |
1034 * 0 otherwise. | |
1035 */ | |
1036 static int | |
1037 is_supported_fourcc (uint32_t fourcc) | |
1038 { | |
1039 switch (fourcc) | |
1040 { | |
1041 //FIXME: YV12 isnt working properly yet | |
1042 // case IMGFMT_YV12: | |
1043 // case IMGFMT_I420: | |
1044 case IMGFMT_UYVY: | |
1045 case IMGFMT_YVYU: | |
1046 case IMGFMT_YUY2: | |
1047 case IMGFMT_RGB15: | |
1048 case IMGFMT_RGB16: | |
1049 // case IMGFMT_BGR32: | |
1050 return 1; | |
1051 default: | |
1052 return 0; | |
1053 } | |
1054 } | |
1055 | |
1056 /** | |
1057 * @brief Try to configure video memory for given fourcc. | |
1058 * | |
1059 * @param to Pointer to the vidix_fourcc_t structure to be filled. | |
1060 * | |
1061 * @returns 0 if ok. | |
1062 * errno otherwise. | |
1063 */ | |
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1064 static int |
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1065 savage_query_fourcc (vidix_fourcc_t * to) |
22850 | 1066 { |
1067 if (is_supported_fourcc (to->fourcc)) | |
1068 { | |
23060 | 1069 to->depth = VID_DEPTH_ALL; |
22850 | 1070 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
1071 return 0; | |
1072 } | |
1073 else | |
1074 to->depth = to->flags = 0; | |
1075 | |
1076 return ENOSYS; | |
1077 } | |
1078 | |
1079 /** | |
1080 * @brief Get the GrKeys | |
1081 * | |
1082 * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. | |
1083 * | |
1084 * @return 0. | |
1085 */ | |
1086 /*int | |
1087 vixGetGrKeys (vidix_grkey_t * grkey) | |
1088 { | |
1089 | |
1090 // if(info->d_width && info->d_height)savage_overlay_start(info,0); | |
1091 | |
1092 return (0); | |
1093 } | |
1094 * */ | |
1095 | |
1096 /** | |
1097 * @brief Set the GrKeys | |
1098 * | |
1099 * @param grkey Colorkey to be set. | |
1100 * | |
1101 * @return 0. | |
1102 */ | |
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1103 static int |
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1104 savage_set_gkeys (const vidix_grkey_t * grkey) |
22850 | 1105 { |
1106 if (grkey->ckey.op == CKEY_FALSE) | |
1107 { | |
1108 info->use_colorkey = 0; | |
1109 info->vidixcolorkey=0; | |
1110 printf("[savage_vid] colorkeying disabled\n"); | |
1111 } | |
1112 else { | |
1113 info->use_colorkey = 1; | |
1114 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1115 | |
1116 printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1117 } | |
1118 //FIXME: freezes if streams arent enabled | |
1119 SavageSetColorKeyOld(); | |
1120 return (0); | |
1121 } | |
1122 | |
1123 /** | |
1124 * @brief Unichrome driver equalizer capabilities. | |
1125 */ | |
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1126 static vidix_video_eq_t equal = { |
22850 | 1127 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, |
1128 300, 100, 0, 0, 0, 0, 0, 0 | |
1129 }; | |
1130 | |
1131 | |
1132 /** | |
1133 * @brief Get the equalizer capabilities. | |
1134 * | |
1135 * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. | |
1136 * | |
1137 * @return 0. | |
1138 */ | |
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1139 static int |
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1140 savage_get_eq (vidix_video_eq_t * eq) |
22850 | 1141 { |
1142 memcpy (eq, &equal, sizeof (vidix_video_eq_t)); | |
1143 return 0; | |
1144 } | |
1145 | |
1146 /** | |
1147 * @brief Set the equalizer capabilities for color correction | |
1148 * | |
1149 * @param eq equalizer capabilities to be set. | |
1150 * | |
1151 * @return 0. | |
1152 */ | |
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1153 static int |
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1154 savage_set_eq (const vidix_video_eq_t * eq) |
22850 | 1155 { |
1156 return 0; | |
1157 } | |
1158 | |
1159 /** | |
1160 * @brief Configure driver for playback. Driver should prepare BES. | |
1161 * | |
1162 * @param info configuration description for playback. | |
1163 * | |
1164 * @returns 0 in case of success. | |
1165 * -1 otherwise. | |
1166 */ | |
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1167 static int |
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1168 savage_config_playback (vidix_playback_t * vinfo) |
22850 | 1169 { |
1170 int uv_size, swap_uv; | |
1171 unsigned int i; | |
1172 | |
1173 if (!is_supported_fourcc (vinfo->fourcc)) | |
1174 return -1; | |
1175 | |
1176 | |
1177 | |
1178 info->src_w = vinfo->src.w; | |
1179 info->src_h = vinfo->src.h; | |
1180 | |
1181 info->drw_w = vinfo->dest.w; | |
1182 info->drw_h = vinfo->dest.h; | |
1183 | |
1184 info->wx = vinfo->dest.x; | |
1185 info->wy = vinfo->dest.y; | |
1186 info->format = vinfo->fourcc; | |
1187 | |
1188 info->lastKnownPitch = 0; | |
1189 info->brightness = 0; | |
1190 info->contrast = 128; | |
1191 info->saturation = 128; | |
1192 info->hue = 0; | |
1193 | |
1194 | |
1195 vinfo->dga_addr=(void*)(info->picture_base); | |
1196 | |
1197 | |
1198 vinfo->offset.y = 0; | |
1199 vinfo->offset.v = 0; | |
1200 vinfo->offset.u = 0; | |
1201 | |
1202 vinfo->dest.pitch.y = 32; | |
1203 vinfo->dest.pitch.u = 32; | |
1204 vinfo->dest.pitch.v = 32; | |
1205 // vinfo->dest.pitch.u = 0; | |
1206 // vinfo->dest.pitch.v = 0; | |
1207 | |
1208 | |
1209 info->pitch = ((info->src_w << 1) + 15) & ~15; | |
1210 | |
1211 swap_uv = 0; | |
1212 switch (vinfo->fourcc) | |
1213 { | |
1214 case IMGFMT_YUY2: | |
1215 case IMGFMT_UYVY: | |
1216 | |
1217 info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1218 | |
1219 info->pitch = info->src_w << 1; | |
1220 info->pitch = ALIGN_TO (info->src_w << 1, 32); | |
1221 uv_size = 0; | |
1222 break; | |
1223 case IMGFMT_YV12: | |
1224 swap_uv = 1; | |
1225 | |
1226 | |
1227 | |
1228 /* | |
1229 srcPitch = (info->src_w + 3) & ~3; | |
1230 vinfo->offset.u = srcPitch * info->src_h; | |
1231 srcPitch2 = ((info->src_w >> 1) + 3) & ~3; | |
1232 vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; | |
1233 | |
1234 vinfo->dest.pitch.y=srcPitch ; | |
1235 vinfo->dest.pitch.v=srcPitch2 ; | |
1236 vinfo->dest.pitch.u=srcPitch2 ; | |
1237 */ | |
1238 | |
1239 | |
1240 info->pitch = ALIGN_TO (info->src_w, 32); | |
1241 uv_size = (info->pitch >> 1) * (info->src_h >> 1); | |
1242 | |
1243 vinfo->offset.y = 0; | |
1244 vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; | |
1245 vinfo->offset.u = vinfo->offset.v + uv_size; | |
1246 vinfo->frame_size = vinfo->offset.u + uv_size; | |
1247 /* YOffs = info->offset.y; | |
1248 UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); | |
1249 VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); | |
1250 */ | |
1251 // vinfo->offset.y = info->src_w; | |
1252 // vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; | |
1253 // vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; | |
1254 | |
1255 break; | |
1256 } | |
1257 info->pitch |= ((info->pitch >> 1) << 16); | |
1258 | |
1259 vinfo->frame_size = info->pitch * info->src_h; | |
1260 | |
1261 printf("$#### destination pitch = %u\n", info->pitch&0xffff); | |
1262 | |
1263 | |
1264 | |
1265 | |
1266 info->buffer_size = vinfo->frame_size; | |
1267 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1268 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1269 // vinfo->num_frames = 1; | |
1270 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1271 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1272 | |
1273 return 0; | |
1274 } | |
1275 | |
1276 /** | |
1277 * @brief Set playback on : driver should activate BES on this call. | |
1278 * | |
1279 * @return 0. | |
1280 */ | |
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1281 static int |
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1282 savage_playback_on (void) |
22850 | 1283 { |
1284 // FIXME: enable | |
1285 SavageDisplayVideoOld(); | |
1286 //FIXME ADD | |
1287 return 0; | |
1288 } | |
1289 | |
1290 /** | |
1291 * @brief Set playback off : driver should deactivate BES on this call. | |
1292 * | |
1293 * @return 0. | |
1294 */ | |
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1295 static int |
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1296 savage_playback_off (void) |
22850 | 1297 { |
1298 // otherwise we wont disable streams properly in new xorg | |
1299 // FIXME: shouldnt this be enabled? | |
1300 // SavageStreamsOn(); | |
1301 SavageStreamsOff(); | |
1302 // info->vidixcolorkey=0x0; | |
1303 | |
1304 // OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
1305 // SavageSetColorKeyOld(); | |
1306 //FIXME ADD | |
1307 return 0; | |
1308 } | |
1309 | |
23057 | 1310 static void debugout(unsigned int addr, unsigned int val){ |
22850 | 1311 return ; |
1312 switch ( addr ){ | |
1313 case PSTREAM_CONTROL_REG: | |
1314 fprintf(stderr,"PSTREAM_CONTROL_REG"); | |
1315 break; | |
1316 case COL_CHROMA_KEY_CONTROL_REG: | |
1317 fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); | |
1318 break; | |
1319 case SSTREAM_CONTROL_REG: | |
1320 fprintf(stderr,"SSTREAM_CONTROL_REG"); | |
1321 break; | |
1322 case CHROMA_KEY_UPPER_BOUND_REG: | |
1323 fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); | |
1324 break; | |
1325 case SSTREAM_STRETCH_REG: | |
1326 fprintf(stderr,"SSTREAM_STRETCH_REG"); | |
1327 break; | |
1328 case COLOR_ADJUSTMENT_REG: | |
1329 fprintf(stderr,"COLOR_ADJUSTMENT_REG"); | |
1330 break; | |
1331 case BLEND_CONTROL_REG: | |
1332 fprintf(stderr,"BLEND_CONTROL_REG"); | |
1333 break; | |
1334 case PSTREAM_FBADDR0_REG: | |
1335 fprintf(stderr,"PSTREAM_FBADDR0_REG"); | |
1336 break; | |
1337 case PSTREAM_FBADDR1_REG: | |
1338 fprintf(stderr,"PSTREAM_FBADDR1_REG"); | |
1339 break; | |
1340 case PSTREAM_STRIDE_REG: | |
1341 fprintf(stderr,"PSTREAM_STRIDE_REG"); | |
1342 break; | |
1343 case DOUBLE_BUFFER_REG: | |
1344 fprintf(stderr,"DOUBLE_BUFFER_REG"); | |
1345 break; | |
1346 case SSTREAM_FBADDR0_REG: | |
1347 fprintf(stderr,"SSTREAM_FBADDR0_REG"); | |
1348 break; | |
1349 case SSTREAM_FBADDR1_REG: | |
1350 fprintf(stderr,"SSTREAM_FBADDR1_REG"); | |
1351 break; | |
1352 case SSTREAM_STRIDE_REG: | |
1353 fprintf(stderr,"SSTREAM_STRIDE_REG"); | |
1354 break; | |
1355 case SSTREAM_VSCALE_REG: | |
1356 fprintf(stderr,"SSTREAM_VSCALE_REG"); | |
1357 break; | |
1358 case SSTREAM_VINITIAL_REG: | |
1359 fprintf(stderr,"SSTREAM_VINITIAL_REG"); | |
1360 break; | |
1361 case SSTREAM_LINES_REG: | |
1362 fprintf(stderr,"SSTREAM_LINES_REG"); | |
1363 break; | |
1364 case STREAMS_FIFO_REG: | |
1365 fprintf(stderr,"STREAMS_FIFO_REG"); | |
1366 break; | |
1367 case PSTREAM_WINDOW_START_REG: | |
1368 fprintf(stderr,"PSTREAM_WINDOW_START_REG"); | |
1369 break; | |
1370 case PSTREAM_WINDOW_SIZE_REG: | |
1371 fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); | |
1372 break; | |
1373 case SSTREAM_WINDOW_START_REG: | |
1374 fprintf(stderr,"SSTREAM_WINDOW_START_REG"); | |
1375 break; | |
1376 case SSTREAM_WINDOW_SIZE_REG: | |
1377 fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); | |
1378 break; | |
1379 case FIFO_CONTROL: | |
1380 fprintf(stderr,"FIFO_CONTROL"); | |
1381 break; | |
1382 case PSTREAM_FBSIZE_REG: | |
1383 fprintf(stderr,"PSTREAM_FBSIZE_REG"); | |
1384 break; | |
1385 case SSTREAM_FBSIZE_REG: | |
1386 fprintf(stderr,"SSTREAM_FBSIZE_REG"); | |
1387 break; | |
1388 case SSTREAM_FBADDR2_REG: | |
1389 fprintf(stderr,"SSTREAM_FBADDR2_REG"); | |
1390 break; | |
1391 | |
1392 } | |
1393 fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); | |
1394 } | |
1395 | |
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1396 VDXDriver savage_drv = { |
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1397 "savage", |
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1398 NULL, |
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1399 .probe = savage_probe, |
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1400 .get_caps = savage_get_caps, |
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1401 .query_fourcc = savage_query_fourcc, |
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1402 .init = savage_init, |
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1403 .destroy = savage_destroy, |
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1404 .config_playback = savage_config_playback, |
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1405 .playback_on = savage_playback_on, |
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1406 .playback_off = savage_playback_off, |
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1407 .get_eq = savage_get_eq, |
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1408 .set_eq = savage_set_eq, |
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1409 .set_gkey = savage_set_gkeys, |
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1410 }; |