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1 /*
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2 * drivers/video/radeonfb.c
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3 * framebuffer driver for ATI Radeon chipset video boards
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4 *
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5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
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6 *
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7 *
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8 * ChangeLog:
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9 * 2000-08-03 initial version 0.0.1
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10 * 2000-09-10 more bug fixes, public release 0.0.5
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11 * 2001-02-19 mode bug fixes, 0.0.7
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12 * 2001-07-05 fixed scrolling issues, engine initialization,
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13 * and minor mode tweaking, 0.0.9
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14 *
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1912
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15 * 2001-09-07 Radeon VE support
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16 * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
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17 * (limitations: on dualhead Radeons (VE, M6, M7)
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18 * driver works only on second head (DVI port).
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19 * TVout is not supported too. M6 & M7 chips
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20 * currently are not supported. Driver has a lot
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21 * of other bugs. Probably they can be solved by
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22 * importing XFree86 code, which has ATI's support).,
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23 * 0.0.11
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24 * 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
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25 * console switching fixes, blanking fixes,
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26 * 0.1.0-ve.0
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27 * 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>),
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28 * Fixed bug of rom bios detection on VE (by NK),
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29 * Minor code cleanup (by NK),
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30 * Enable CRT port on VE (by NK),
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31 * Disable SURFACE_CNTL because mplayer doesn't work
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32 * propertly (by NK)
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33 * 0.1.0-ve.1
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34 * 2001-09-25 MTRR support (by NK)
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35 * Special thanks to ATI DevRel team for their hardware donations.
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36 *
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37 * LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in
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38 * dual monitor configuration. TVout is not supported too.
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39 * Probably these problems can be solved by importing XFree86 code, which
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40 * has ATI's support.
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41 *
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42 * Mini-HOWTO: This driver doesn't accept any options. It only switches your
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43 * video card to graphics mode. Standard way to change video modes and other
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44 * video attributes is using 'fbset' utility.
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45 * Sample:
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46 *
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47 * #!/bin/sh
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48 * fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767
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49 *
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50 */
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51
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52 #define RADEON_VERSION "0.1.0-ve.1"
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53
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54 #include <linux/config.h>
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55 #include <linux/module.h>
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56 #include <linux/kernel.h>
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57 #include <linux/errno.h>
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58 #include <linux/string.h>
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59 #include <linux/mm.h>
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60 #include <linux/tty.h>
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61 #include <linux/malloc.h>
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62 #include <linux/delay.h>
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63 #include <linux/fb.h>
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64 #include <linux/console.h>
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65 #include <linux/selection.h>
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66 #include <linux/ioport.h>
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67 #include <linux/init.h>
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68 #include <linux/pci.h>
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69
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70 #include <asm/io.h>
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71
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72 #include <video/fbcon.h>
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73 #include <video/fbcon-cfb8.h>
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74 #include <video/fbcon-cfb16.h>
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75 #include <video/fbcon-cfb24.h>
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76 #include <video/fbcon-cfb32.h>
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77
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78 #ifdef CONFIG_MTRR
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79 #include <asm/mtrr.h>
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80 #endif
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81
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82 #include "radeon.h"
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83
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84
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85 #define DEBUG 0
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86
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87 #if DEBUG
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88 #define RTRACE printk
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89 #else
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90 #define RTRACE if(0) printk
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91 #endif
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92
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93
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94
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95 enum radeon_chips {
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96 RADEON_QD,
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97 RADEON_QE,
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98 RADEON_QF,
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99 RADEON_QG,
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100 RADEON_QY,
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101 RADEON_QZ,
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102 RADEON_LY,
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103 RADEON_LZ,
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104 RADEON_LW
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105 };
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106
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107 enum radeon_montype
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108 {
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109 MT_NONE,
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110 MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
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111 MT_LCD, /* Liquid Crystal Display */
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112 MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
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113 MT_CTV, /* Composite TV out (not in VE) */
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114 MT_STV /* S-Video TV out (probably in VE only) */
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115 };
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116
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117 enum radeon_ddctype
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118 {
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119 DDC_NONE_DETECTED,
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120 DDC_MONID,
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121 DDC_DVI,
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122 DDC_VGA,
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123 DDC_CRT2
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124 };
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125
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126 enum radeon_connectortype
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127 {
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128 CONNECTOR_NONE,
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129 CONNECTOR_PROPRIETARY,
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130 CONNECTOR_CRT,
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131 CONNECTOR_DVI_I,
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132 CONNECTOR_DVI_D
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133 };
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134
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135 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
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136 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
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137 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
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138 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
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139 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
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140 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
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141 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
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142 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
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143 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
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144 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
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145 { 0, }
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146 };
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147 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
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148
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149
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150 typedef struct {
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151 u16 reg;
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152 u32 val;
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153 } reg_val;
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154
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155
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156 /* these common regs are cleared before mode setting so they do not
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157 * interfere with anything
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158 */
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159 reg_val common_regs[] = {
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160 { OVR_CLR, 0 },
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161 { OVR_WID_LEFT_RIGHT, 0 },
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162 { OVR_WID_TOP_BOTTOM, 0 },
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163 { OV0_SCALE_CNTL, 0 },
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164 { SUBPIC_CNTL, 0 },
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165 { VIPH_CONTROL, 0 },
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166 { I2C_CNTL_1, 0 },
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167 { GEN_INT_CNTL, 0 },
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168 { CAP0_TRIG_CNTL, 0 },
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169 };
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170
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171 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
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172
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173 typedef struct {
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174 u8 clock_chip_type;
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175 u8 struct_size;
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176 u8 accelerator_entry;
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177 u8 VGA_entry;
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178 u16 VGA_table_offset;
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179 u16 POST_table_offset;
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180 u16 XCLK;
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181 u16 MCLK;
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182 u8 num_PLL_blocks;
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183 u8 size_PLL_blocks;
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184 u16 PCLK_ref_freq;
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185 u16 PCLK_ref_divider;
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186 u32 PCLK_min_freq;
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187 u32 PCLK_max_freq;
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188 u16 MCLK_ref_freq;
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189 u16 MCLK_ref_divider;
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190 u32 MCLK_min_freq;
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191 u32 MCLK_max_freq;
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192 u16 XCLK_ref_freq;
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193 u16 XCLK_ref_divider;
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194 u32 XCLK_min_freq;
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195 u32 XCLK_max_freq;
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196 } __attribute__ ((packed)) PLL_BLOCK;
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197
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198
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199 struct pll_info {
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200 int ppll_max;
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201 int ppll_min;
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202 int xclk;
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203 int ref_div;
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204 int ref_clk;
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205 };
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206
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207
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208 struct ram_info {
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209 int ml;
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210 int mb;
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211 int trcd;
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212 int trp;
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213 int twr;
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214 int cl;
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215 int tr2w;
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216 int loop_latency;
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217 int rloop;
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218 };
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219
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220
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221 struct radeon_regs {
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222 u32 crtc_h_total_disp;
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223 u32 crtc_h_sync_strt_wid;
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224 u32 crtc_v_total_disp;
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225 u32 crtc_v_sync_strt_wid;
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226 u32 crtc_pitch;
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227 u32 flags;
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228 u32 pix_clock;
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229 int xres, yres;
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230 int bpp;
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231 u32 crtc_gen_cntl;
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232 u32 crtc_ext_cntl;
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233 #if defined(__BIG_ENDIAN)
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234 u32 surface_cntl;
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235 #endif
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236 u32 dac_cntl;
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237 u32 dda_config;
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238 u32 dda_on_off;
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239 u32 ppll_div_3;
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240 u32 ppll_ref_div;
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241 };
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242
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243
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244 struct radeonfb_info {
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245 struct fb_info info;
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246
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247 struct radeon_regs state;
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248 struct radeon_regs init_state;
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249
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250 char name[14];
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251 char ram_type[12];
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252
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253 int hasCRTC2;
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254 int crtDispType;
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255 int dviDispType;
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256 int hasTVout;
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257 int isM7;
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258
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259 u32 mmio_base_phys;
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260 u32 fb_base_phys;
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261
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262 u32 mmio_base;
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263 u32 fb_base;
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264
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265 struct pci_dev *pdev;
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266
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267 struct display disp;
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268 int currcon;
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269 struct display *currcon_display;
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270
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271 struct { u8 red, green, blue, pad; } palette[256];
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272
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273 int chipset;
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274 int video_ram;
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275 u8 rev;
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276 int pitch, bpp, depth;
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277 int xres, yres, pixclock;
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278
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279 u32 dp_gui_master_cntl;
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280
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281 struct pll_info pll;
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282 int pll_output_freq, post_div, fb_div;
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283
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284 struct ram_info ram;
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285
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286 u32 hack_crtc_ext_cntl;
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287 u32 hack_crtc_v_sync_strt_wid;
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288 #ifdef CONFIG_MTRR
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289 struct { int vram; int vram_valid; } mtrr;
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290 #endif
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291 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
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292 union {
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293 #if defined(FBCON_HAS_CFB16)
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294 u_int16_t cfb16[16];
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295 #endif
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296 #if defined(FBCON_HAS_CFB24)
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297 u_int32_t cfb24[16];
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298 #endif
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299 #if defined(FBCON_HAS_CFB32)
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300 u_int32_t cfb32[16];
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301 #endif
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302 } con_cmap;
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303 #endif
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304 };
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305
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306
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307 static struct fb_var_screeninfo radeonfb_default_var = {
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308 640, 480, 640, 480, 0, 0, 8, 0,
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309 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
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310 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
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311 0, FB_VMODE_NONINTERLACED
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312 };
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313
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314
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315 /*
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316 * IO macros
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317 */
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318
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319 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
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320 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
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321 #define INREG(addr) readl((rinfo->mmio_base)+addr)
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322 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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323
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324 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
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325 OUTREG(CLOCK_CNTL_DATA, val)
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326 #define OUTPLLP(addr,val,mask) \
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327 do { \
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328 unsigned int _tmp = INPLL(addr); \
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329 _tmp &= (mask); \
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330 _tmp |= (val); \
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331 OUTPLL(addr, _tmp); \
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332 } while (0)
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333
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334 #define OUTREGP(addr,val,mask) \
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335 do { \
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336 unsigned int _tmp = INREG(addr); \
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337 _tmp &= (mask); \
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338 _tmp |= (val); \
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339 OUTREG(addr, _tmp); \
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340 } while (0)
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341
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342
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343 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
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344 {
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345 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
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346 return (INREG(CLOCK_CNTL_DATA));
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347 }
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348
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349 #define INPLL(addr) _INPLL(rinfo, addr)
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350
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351
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352 /*
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353 * 2D engine routines
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354 */
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355
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356 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
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357 {
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358 int i;
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359
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360 /* initiate flush */
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361 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
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362 ~RB2D_DC_FLUSH_ALL);
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363
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364 for (i=0; i < 2000000; i++) {
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365 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
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366 break;
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367 }
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368 }
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369
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370
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371 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
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372 {
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373 int i;
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374
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375 for (i=0; i<2000000; i++)
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376 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
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377 return;
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378 }
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379
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380
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381 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
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382 {
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383 int i;
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384
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385 /* ensure FIFO is empty before waiting for idle */
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386 _radeon_fifo_wait (rinfo, 64);
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387
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388 for (i=0; i<2000000; i++) {
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389 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
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390 radeon_engine_flush (rinfo);
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391 return;
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392 }
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393 }
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394 }
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395
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396
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397 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
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398 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
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399
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400
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401
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402 /*
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403 * helper routines
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404 */
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405
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406 static __inline__ u32 radeon_get_dstbpp(u16 depth)
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407 {
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408 switch (depth) {
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409 case 8:
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410 return DST_8BPP;
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411 case 15:
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412 return DST_15BPP;
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413 case 16:
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414 return DST_16BPP;
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415 case 24:
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416 return DST_24BPP;
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417 case 32:
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418 return DST_32BPP;
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419 default:
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420 return 0;
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421 }
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422 }
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423
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424
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425 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
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426 {
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427 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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428
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429 radeon_engine_flush (rinfo);
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430
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431 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
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432 mclk_cntl = INPLL(MCLK_CNTL);
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433
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434 OUTPLL(MCLK_CNTL, (mclk_cntl |
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435 FORCEON_MCLKA |
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436 FORCEON_MCLKB |
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437 FORCEON_YCLKA |
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438 FORCEON_YCLKB |
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439 FORCEON_MC |
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440 FORCEON_AIC));
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441 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
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442
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443 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
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444 SOFT_RESET_CP |
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445 SOFT_RESET_HI |
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446 SOFT_RESET_SE |
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447 SOFT_RESET_RE |
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448 SOFT_RESET_PP |
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449 SOFT_RESET_E2 |
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450 SOFT_RESET_RB |
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451 SOFT_RESET_HDP);
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452 INREG(RBBM_SOFT_RESET);
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453 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
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454 ~(SOFT_RESET_CP |
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455 SOFT_RESET_HI |
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456 SOFT_RESET_SE |
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457 SOFT_RESET_RE |
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458 SOFT_RESET_PP |
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459 SOFT_RESET_E2 |
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460 SOFT_RESET_RB |
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461 SOFT_RESET_HDP));
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462 INREG(RBBM_SOFT_RESET);
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463
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464 OUTPLL(MCLK_CNTL, mclk_cntl);
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465 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
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466 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
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467
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468 return;
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469 }
|
|
470
|
|
471 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
|
|
472
|
|
473
|
|
474 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
|
|
475 {
|
|
476 switch (post_div) {
|
|
477 case 1:
|
|
478 return 0x00;
|
|
479 case 2:
|
|
480 return 0x01;
|
|
481 case 3:
|
|
482 return 0x04;
|
|
483 case 4:
|
|
484 return 0x02;
|
|
485 case 6:
|
|
486 return 0x06;
|
|
487 case 8:
|
|
488 return 0x03;
|
|
489 case 12:
|
|
490 return 0x07;
|
|
491 default:
|
|
492 return 0x02;
|
|
493 }
|
|
494 }
|
|
495
|
|
496
|
|
497
|
|
498 static __inline__ int round_div(int num, int den)
|
|
499 {
|
|
500 return (num + (den / 2)) / den;
|
|
501 }
|
|
502
|
|
503
|
|
504
|
|
505 static __inline__ int min_bits_req(int val)
|
|
506 {
|
|
507 int bits_req = 0;
|
|
508
|
|
509 if (val == 0)
|
|
510 bits_req = 1;
|
|
511
|
|
512 while (val) {
|
|
513 val >>= 1;
|
|
514 bits_req++;
|
|
515 }
|
|
516
|
|
517 return (bits_req);
|
|
518 }
|
|
519
|
|
520
|
|
521 static __inline__ int _max(int val1, int val2)
|
|
522 {
|
|
523 if (val1 >= val2)
|
|
524 return val1;
|
|
525 else
|
|
526 return val2;
|
|
527 }
|
|
528
|
|
529
|
|
530
|
|
531 /*
|
|
532 * globals
|
|
533 */
|
|
534
|
|
535 static char fontname[40] __initdata;
|
|
536 static char *mode_option __initdata;
|
|
537 static char noaccel __initdata = 0;
|
1951
|
538 static int nomtrr __initdata = 0;
|
1911
|
539
|
1914
|
540 #if 0
|
1911
|
541 #ifdef FBCON_HAS_CFB8
|
|
542 static struct display_switch fbcon_radeon8;
|
|
543 #endif
|
1914
|
544 #endif
|
1911
|
545
|
1951
|
546 #ifdef CONFIG_MTRR
|
|
547 static int mtrr = 1;
|
|
548 #endif
|
|
549
|
1911
|
550 /*
|
|
551 * prototypes
|
|
552 */
|
|
553
|
|
554 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
555 struct fb_info *info);
|
|
556 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
557 struct fb_info *info);
|
|
558 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
559 struct fb_info *info);
|
|
560 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
561 struct fb_info *info);
|
|
562 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
563 struct fb_info *info);
|
|
564 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
565 struct fb_info *info);
|
|
566 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
567 unsigned long arg, int con, struct fb_info *info);
|
|
568 static int radeonfb_switch (int con, struct fb_info *info);
|
|
569 static int radeonfb_updatevar (int con, struct fb_info *info);
|
|
570 static void radeonfb_blank (int blank, struct fb_info *info);
|
|
571 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
|
|
572 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
573 unsigned *blue, unsigned *transp,
|
|
574 struct fb_info *info);
|
|
575 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
576 unsigned blue, unsigned transp, struct fb_info *info);
|
1914
|
577 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
|
1911
|
578 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
579 struct radeon_regs *save);
|
|
580 static void radeon_engine_init (struct radeonfb_info *rinfo);
|
|
581 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
582 struct fb_var_screeninfo *mode);
|
|
583 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
584 struct radeon_regs *mode);
|
|
585 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
|
|
586 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
|
|
587 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
|
|
588 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
589 const struct pci_device_id *ent);
|
|
590 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
|
|
591 static char *radeon_find_rom(struct radeonfb_info *rinfo);
|
|
592 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
|
1914
|
593 static void do_install_cmap(int con, struct fb_info *info);
|
|
594 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
595 struct fb_var_screeninfo *var,
|
|
596 struct fb_var_screeninfo *v,
|
|
597 int nom, int den);
|
1911
|
598
|
|
599 static struct fb_ops radeon_fb_ops = {
|
|
600 fb_get_fix: radeonfb_get_fix,
|
|
601 fb_get_var: radeonfb_get_var,
|
|
602 fb_set_var: radeonfb_set_var,
|
|
603 fb_get_cmap: radeonfb_get_cmap,
|
|
604 fb_set_cmap: radeonfb_set_cmap,
|
|
605 fb_pan_display: radeonfb_pan_display,
|
|
606 fb_ioctl: radeonfb_ioctl,
|
|
607 };
|
|
608
|
|
609
|
|
610 static struct pci_driver radeonfb_driver = {
|
|
611 name: "radeonfb",
|
|
612 id_table: radeonfb_pci_table,
|
|
613 probe: radeonfb_pci_register,
|
|
614 remove: radeonfb_pci_unregister,
|
|
615 };
|
|
616
|
|
617
|
|
618 int __init radeonfb_init (void)
|
|
619 {
|
1951
|
620 #ifdef CONFIG_MTRR
|
|
621 if (nomtrr) {
|
|
622 mtrr = 0;
|
|
623 printk("radeonfb: Parameter NOMTRR set\n");
|
|
624 }
|
|
625 #endif
|
|
626 return pci_module_init (&radeonfb_driver);
|
1911
|
627 }
|
|
628
|
|
629
|
|
630 void __exit radeonfb_exit (void)
|
|
631 {
|
|
632 pci_unregister_driver (&radeonfb_driver);
|
|
633 }
|
|
634
|
|
635
|
|
636 int __init radeonfb_setup (char *options)
|
|
637 {
|
|
638 char *this_opt;
|
|
639
|
|
640 if (!options || !*options)
|
|
641 return 0;
|
|
642
|
|
643 for (this_opt = strtok (options, ","); this_opt;
|
|
644 this_opt = strtok (NULL, ",")) {
|
|
645 if (!strncmp (this_opt, "font:", 5)) {
|
|
646 char *p;
|
|
647 int i;
|
|
648
|
|
649 p = this_opt + 5;
|
|
650 for (i=0; i<sizeof (fontname) - 1; i++)
|
|
651 if (!*p || *p == ' ' || *p == ',')
|
|
652 break;
|
|
653 memcpy(fontname, this_opt + 5, i);
|
|
654 } else if (!strncmp(this_opt, "noaccel", 7)) {
|
|
655 noaccel = 1;
|
|
656 }
|
1951
|
657 #ifdef CONFIG_MTRR
|
|
658 else if(!strncmp(this_opt, "nomtrr", 6)) {
|
|
659 mtrr = 0;
|
|
660 }
|
|
661 #endif
|
1911
|
662 else mode_option = this_opt;
|
|
663 }
|
|
664
|
|
665 return 0;
|
|
666 }
|
|
667
|
|
668 #ifdef MODULE
|
|
669 module_init(radeonfb_init);
|
|
670 module_exit(radeonfb_exit);
|
|
671 #endif
|
|
672
|
|
673
|
1915
|
674 MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)");
|
|
675 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION);
|
1951
|
676 #ifdef CONFIG_MTRR
|
|
677 MODULE_PARM(nomtrr, "i");
|
|
678 MODULE_PARM_DESC(nomtrr, "Don't touch MTRR (touch=0(default))");
|
|
679 #endif
|
1911
|
680
|
1915
|
681 static char * GET_MON_NAME(int type)
|
|
682 {
|
|
683 char *pret;
|
|
684 switch(type)
|
|
685 {
|
|
686 case MT_NONE: pret = "no"; break;
|
|
687 case MT_CRT: pret = "CRT"; break;
|
|
688 case MT_DFP: pret = "DFP"; break;
|
|
689 case MT_LCD: pret = "LCD"; break;
|
|
690 case MT_CTV: pret = "CTV"; break;
|
|
691 case MT_STV: pret = "STV"; break;
|
|
692 default: pret = "Unknown";
|
|
693 }
|
|
694 return pret;
|
|
695 }
|
1911
|
696
|
|
697
|
|
698 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
699 const struct pci_device_id *ent)
|
|
700 {
|
|
701 struct radeonfb_info *rinfo;
|
|
702 u32 tmp;
|
|
703 int i, j;
|
|
704 char *bios_seg = NULL;
|
|
705
|
|
706 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
|
|
707 if (!rinfo) {
|
|
708 printk ("radeonfb: could not allocate memory\n");
|
|
709 return -ENODEV;
|
|
710 }
|
|
711
|
|
712 memset (rinfo, 0, sizeof (struct radeonfb_info));
|
|
713
|
|
714 /* enable device */
|
|
715 {
|
|
716 int err;
|
|
717
|
|
718 if ((err = pci_enable_device(pdev))) {
|
|
719 printk("radeonfb: cannot enable device\n");
|
|
720 kfree (rinfo);
|
|
721 return -ENODEV;
|
|
722 }
|
|
723 }
|
|
724
|
|
725 /* set base addrs */
|
|
726 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
|
|
727 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
|
|
728
|
|
729 /* request the mem regions */
|
|
730 if (!request_mem_region (rinfo->fb_base_phys,
|
|
731 pci_resource_len(pdev, 0), "radeonfb")) {
|
|
732 printk ("radeonfb: cannot reserve FB region\n");
|
|
733 kfree (rinfo);
|
|
734 return -ENODEV;
|
|
735 }
|
|
736
|
|
737 if (!request_mem_region (rinfo->mmio_base_phys,
|
|
738 pci_resource_len(pdev, 2), "radeonfb")) {
|
|
739 printk ("radeonfb: cannot reserve MMIO region\n");
|
|
740 release_mem_region (rinfo->fb_base_phys,
|
|
741 pci_resource_len(pdev, 0));
|
|
742 kfree (rinfo);
|
|
743 return -ENODEV;
|
|
744 }
|
|
745
|
|
746 /* map the regions */
|
|
747 rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
|
|
748 RADEON_REGSIZE);
|
|
749 if (!rinfo->mmio_base) {
|
|
750 printk ("radeonfb: cannot map MMIO\n");
|
|
751 release_mem_region (rinfo->mmio_base_phys,
|
|
752 pci_resource_len(pdev, 2));
|
|
753 release_mem_region (rinfo->fb_base_phys,
|
|
754 pci_resource_len(pdev, 0));
|
|
755 kfree (rinfo);
|
|
756 return -ENODEV;
|
|
757 }
|
|
758
|
|
759 /* chipset */
|
|
760 switch (pdev->device) {
|
|
761 case PCI_DEVICE_ID_RADEON_QD:
|
|
762 strcpy(rinfo->name, "Radeon QD ");
|
|
763 break;
|
|
764 case PCI_DEVICE_ID_RADEON_QE:
|
|
765 strcpy(rinfo->name, "Radeon QE ");
|
|
766 break;
|
|
767 case PCI_DEVICE_ID_RADEON_QF:
|
|
768 strcpy(rinfo->name, "Radeon QF ");
|
|
769 break;
|
|
770 case PCI_DEVICE_ID_RADEON_QG:
|
|
771 strcpy(rinfo->name, "Radeon QG ");
|
|
772 break;
|
1913
|
773 case PCI_DEVICE_ID_RADEON_QY:
|
1915
|
774 rinfo->hasCRTC2 = 1;
|
|
775 strcpy(rinfo->name, "Radeon VE QY ");
|
1913
|
776 break;
|
|
777 case PCI_DEVICE_ID_RADEON_QZ:
|
1915
|
778 rinfo->hasCRTC2 = 1;
|
|
779 strcpy(rinfo->name, "Radeon VE QZ ");
|
|
780 break;
|
|
781 case PCI_DEVICE_ID_RADEON_LY:
|
|
782 rinfo->hasCRTC2 = 1;
|
|
783 strcpy(rinfo->name, "Radeon M6 LY ");
|
|
784 break;
|
|
785 case PCI_DEVICE_ID_RADEON_LZ:
|
|
786 rinfo->hasCRTC2 = 1;
|
|
787 strcpy(rinfo->name, "Radeon M6 LZ ");
|
|
788 break;
|
|
789 case PCI_DEVICE_ID_RADEON_LW:
|
|
790 /* Note: Only difference between VE,M6 and M7 is initialization CRTC2
|
|
791 registers in dual monitor configuration!!! */
|
|
792 rinfo->hasCRTC2 = 1;
|
|
793 rinfo->isM7 = 1;
|
|
794 strcpy(rinfo->name, "Radeon M7 LW ");
|
1912
|
795 break;
|
1911
|
796 default:
|
1915
|
797 release_mem_region (rinfo->mmio_base_phys,
|
|
798 pci_resource_len(pdev, 2));
|
|
799 release_mem_region (rinfo->fb_base_phys,
|
|
800 pci_resource_len(pdev, 0));
|
|
801 kfree (rinfo);
|
1911
|
802 return -ENODEV;
|
|
803 }
|
|
804
|
|
805 /* framebuffer size */
|
|
806 tmp = INREG(CONFIG_MEMSIZE);
|
|
807
|
|
808 /* mem size is bits [28:0], mask off the rest */
|
|
809 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
|
810
|
|
811 /* ram type */
|
|
812 tmp = INREG(MEM_SDRAM_MODE_REG);
|
|
813 switch ((MEM_CFG_TYPE & tmp) >> 30) {
|
|
814 case 0:
|
|
815 /* SDR SGRAM (2:1) */
|
|
816 strcpy(rinfo->ram_type, "SDR SGRAM");
|
|
817 rinfo->ram.ml = 4;
|
|
818 rinfo->ram.mb = 4;
|
|
819 rinfo->ram.trcd = 1;
|
|
820 rinfo->ram.trp = 2;
|
|
821 rinfo->ram.twr = 1;
|
|
822 rinfo->ram.cl = 2;
|
|
823 rinfo->ram.loop_latency = 16;
|
|
824 rinfo->ram.rloop = 16;
|
|
825
|
|
826 break;
|
|
827 case 1:
|
|
828 /* DDR SGRAM */
|
|
829 strcpy(rinfo->ram_type, "DDR SGRAM");
|
|
830 rinfo->ram.ml = 4;
|
|
831 rinfo->ram.mb = 4;
|
|
832 rinfo->ram.trcd = 3;
|
|
833 rinfo->ram.trp = 3;
|
|
834 rinfo->ram.twr = 2;
|
|
835 rinfo->ram.cl = 3;
|
|
836 rinfo->ram.tr2w = 1;
|
|
837 rinfo->ram.loop_latency = 16;
|
|
838 rinfo->ram.rloop = 16;
|
|
839
|
|
840 break;
|
|
841 default:
|
|
842 /* 64-bit SDR SGRAM */
|
|
843 strcpy(rinfo->ram_type, "SDR SGRAM 64");
|
|
844 rinfo->ram.ml = 4;
|
|
845 rinfo->ram.mb = 8;
|
|
846 rinfo->ram.trcd = 3;
|
|
847 rinfo->ram.trp = 3;
|
|
848 rinfo->ram.twr = 1;
|
|
849 rinfo->ram.cl = 3;
|
|
850 rinfo->ram.tr2w = 1;
|
|
851 rinfo->ram.loop_latency = 17;
|
|
852 rinfo->ram.rloop = 17;
|
|
853
|
|
854 break;
|
|
855 }
|
|
856
|
|
857 bios_seg = radeon_find_rom(rinfo);
|
|
858 radeon_get_pllinfo(rinfo, bios_seg);
|
|
859
|
|
860 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
|
|
861 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
|
|
862
|
|
863 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
|
864
|
1915
|
865 /*****
|
|
866 VE and M6 have both DVI and CRT ports (for M6 DVI port can be switch to
|
|
867 DFP port). The DVI port can also be conneted to a CRT with an adapter.
|
|
868 Here is the definition of ports for this driver---
|
|
869 (1) If both port are connected, DVI port will be treated as the Primary
|
|
870 port (uses CRTC1) and CRT port will be treated as the Secondary port
|
|
871 (uses CRTC2)
|
|
872 (2) If only one port is connected, it will treated as the Primary port
|
|
873 (??? uses CRTC1 ???)
|
|
874 *****/
|
|
875 if(rinfo->hasCRTC2) {
|
|
876 /* Using BIOS scratch registers works with for VE/M6,
|
|
877 no such registers in regular RADEON!!!*/
|
|
878 tmp = INREG(RADEON_BIOS_4_SCRATCH);
|
|
879 /*check Primary (DVI/DFP port)*/
|
|
880 if(tmp & 0x08) rinfo->dviDispType = MT_DFP;
|
|
881 else if(tmp & 0x04) rinfo->dviDispType = MT_LCD;
|
|
882 else if(tmp & 0x0200) rinfo->dviDispType = MT_CRT;
|
|
883 else if(tmp & 0x10) rinfo->dviDispType = MT_CTV;
|
|
884 else if(tmp & 0x20) rinfo->dviDispType = MT_STV;
|
|
885 /*check Secondary (CRT port).*/
|
|
886 if(tmp & 0x02) rinfo->crtDispType = MT_CRT;
|
|
887 else if(tmp & 0x800) rinfo->crtDispType = MT_DFP;
|
|
888 else if(tmp & 0x400) rinfo->crtDispType = MT_LCD;
|
|
889 else if(tmp & 0x1000) rinfo->crtDispType = MT_CTV;
|
|
890 else if(tmp & 0x2000) rinfo->crtDispType = MT_STV;
|
|
891 if(rinfo->dviDispType == MT_NONE &&
|
|
892 rinfo->crtDispType == MT_NONE) {
|
|
893 printk("radeonfb: No monitor detected!!!\n");
|
|
894 release_mem_region (rinfo->mmio_base_phys,
|
|
895 pci_resource_len(pdev, 2));
|
|
896 release_mem_region (rinfo->fb_base_phys,
|
|
897 pci_resource_len(pdev, 0));
|
|
898 kfree (rinfo);
|
|
899 return -ENODEV;
|
|
900 }
|
|
901 }
|
|
902 else {
|
|
903 /*Regular Radeon ASIC, only one CRTC, but it could be
|
|
904 used for DFP with a DVI output, like AIW board*/
|
|
905 rinfo->dviDispType = MT_NONE;
|
|
906 tmp = INREG(FP_GEN_CNTL);
|
|
907 if(tmp & FP_EN_TMDS) rinfo->crtDispType = MT_DFP;
|
|
908 else rinfo->crtDispType = MT_CRT;
|
|
909 }
|
|
910
|
|
911 if(bios_seg) {
|
|
912 /*
|
|
913 FIXME!!! TVout support currently is incomplete
|
|
914 On Radeon VE TVout is recognized as STV monitor on DVI port.
|
|
915 */
|
|
916 char * bios_ptr = bios_seg + 0x48L;
|
|
917 rinfo->hasTVout = readw(bios_ptr+0x32);
|
|
918 }
|
|
919
|
1911
|
920 rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
|
921 rinfo->video_ram);
|
|
922 if (!rinfo->fb_base) {
|
|
923 printk ("radeonfb: cannot map FB\n");
|
|
924 iounmap ((void*)rinfo->mmio_base);
|
|
925 release_mem_region (rinfo->mmio_base_phys,
|
|
926 pci_resource_len(pdev, 2));
|
|
927 release_mem_region (rinfo->fb_base_phys,
|
|
928 pci_resource_len(pdev, 0));
|
|
929 kfree (rinfo);
|
|
930 return -ENODEV;
|
|
931 }
|
|
932
|
|
933 /* XXX turn off accel for now, blts aren't working right */
|
|
934 noaccel = 1;
|
|
935
|
|
936 /* set all the vital stuff */
|
|
937 radeon_set_fbinfo (rinfo);
|
|
938
|
|
939 /* save current mode regs before we switch into the new one
|
|
940 * so we can restore this upon __exit
|
|
941 */
|
|
942 radeon_save_state (rinfo, &rinfo->init_state);
|
|
943
|
|
944 /* init palette */
|
|
945 for (i=0; i<16; i++) {
|
|
946 j = color_table[i];
|
|
947 rinfo->palette[i].red = default_red[j];
|
|
948 rinfo->palette[i].green = default_grn[j];
|
|
949 rinfo->palette[i].blue = default_blu[j];
|
|
950 }
|
|
951
|
|
952 pdev->driver_data = rinfo;
|
|
953
|
|
954 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
|
|
955 printk ("radeonfb: could not register framebuffer\n");
|
|
956 iounmap ((void*)rinfo->fb_base);
|
|
957 iounmap ((void*)rinfo->mmio_base);
|
|
958 release_mem_region (rinfo->mmio_base_phys,
|
|
959 pci_resource_len(pdev, 2));
|
|
960 release_mem_region (rinfo->fb_base_phys,
|
|
961 pci_resource_len(pdev, 0));
|
|
962 kfree (rinfo);
|
|
963 return -ENODEV;
|
|
964 }
|
|
965
|
|
966 if (!noaccel) {
|
|
967 /* initialize the engine */
|
|
968 radeon_engine_init (rinfo);
|
|
969 }
|
|
970
|
1915
|
971 printk ("radeonfb: ATI %s %s %d MB\n",rinfo->name,rinfo->ram_type,
|
1911
|
972 (rinfo->video_ram/(1024*1024)));
|
1915
|
973 if(rinfo->hasCRTC2) {
|
|
974 printk("radeonfb: DVI port has %s monitor connected\n",GET_MON_NAME(rinfo->dviDispType));
|
|
975 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
976 }
|
|
977 else
|
|
978 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
979 printk("radeonfb: This card has %sTVout\n",rinfo->hasTVout ? "" : "no ");
|
1951
|
980 #ifdef CONFIG_MTRR
|
|
981 if (mtrr) {
|
|
982 rinfo->mtrr.vram = mtrr_add(rinfo->fb_base_phys,
|
|
983 rinfo->video_ram, MTRR_TYPE_WRCOMB, 1);
|
|
984 rinfo->mtrr.vram_valid = 1;
|
|
985 /* let there be speed */
|
|
986 printk("radeonfb: MTRR set to ON\n");
|
|
987 }
|
|
988 #endif /* CONFIG_MTRR */
|
1911
|
989
|
|
990 return 0;
|
|
991 }
|
|
992
|
|
993
|
|
994
|
|
995 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
|
|
996 {
|
|
997 struct radeonfb_info *rinfo = pdev->driver_data;
|
|
998
|
|
999 if (!rinfo)
|
|
1000 return;
|
|
1001
|
|
1002 /* restore original state */
|
|
1003 radeon_write_mode (rinfo, &rinfo->init_state);
|
|
1004
|
|
1005 unregister_framebuffer ((struct fb_info *) rinfo);
|
1951
|
1006 #ifdef CONFIG_MTRR
|
|
1007 if (rinfo->mtrr.vram_valid)
|
|
1008 mtrr_del(rinfo->mtrr.vram, rinfo->fb_base_phys,
|
|
1009 rinfo->video_ram);
|
|
1010 #endif /* CONFIG_MTRR */
|
1911
|
1011 iounmap ((void*)rinfo->mmio_base);
|
|
1012 iounmap ((void*)rinfo->fb_base);
|
|
1013
|
|
1014 release_mem_region (rinfo->mmio_base_phys,
|
|
1015 pci_resource_len(pdev, 2));
|
|
1016 release_mem_region (rinfo->fb_base_phys,
|
|
1017 pci_resource_len(pdev, 0));
|
|
1018
|
|
1019 kfree (rinfo);
|
|
1020 }
|
|
1021
|
|
1022
|
|
1023
|
|
1024 static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
|
1025 {
|
1914
|
1026 #if defined(__i386__)
|
1911
|
1027 u32 segstart;
|
|
1028 char *rom_base;
|
|
1029 char *rom;
|
|
1030 int stage;
|
1915
|
1031 int i,j;
|
1911
|
1032 char aty_rom_sig[] = "761295520";
|
1915
|
1033 char *radeon_sig[] = {
|
|
1034 "RG6",
|
|
1035 "RADEON"
|
|
1036 };
|
1911
|
1037
|
|
1038 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
|
1039 stage = 1;
|
|
1040
|
|
1041 rom_base = (char *)ioremap(segstart, 0x1000);
|
|
1042
|
|
1043 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
|
|
1044 stage = 2;
|
|
1045
|
|
1046
|
|
1047 if (stage != 2) {
|
|
1048 iounmap(rom_base);
|
|
1049 continue;
|
|
1050 }
|
|
1051
|
|
1052 rom = rom_base;
|
|
1053
|
|
1054 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
|
|
1055 if (aty_rom_sig[0] == *rom)
|
|
1056 if (strncmp(aty_rom_sig, rom,
|
|
1057 strlen(aty_rom_sig)) == 0)
|
|
1058 stage = 3;
|
|
1059 rom++;
|
|
1060 }
|
|
1061 if (stage != 3) {
|
|
1062 iounmap(rom_base);
|
|
1063 continue;
|
|
1064 }
|
|
1065 rom = rom_base;
|
|
1066
|
|
1067 for (i = 0; (i < 512) && (stage != 4); i++) {
|
1915
|
1068 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
|
|
1069 if (radeon_sig[j][0] == *rom)
|
|
1070 if (strncmp(radeon_sig[j], rom,
|
|
1071 strlen(radeon_sig[j])) == 0) {
|
|
1072 stage = 4;
|
|
1073 break;
|
|
1074 }
|
|
1075 }
|
1911
|
1076 rom++;
|
|
1077 }
|
|
1078 if (stage != 4) {
|
|
1079 iounmap(rom_base);
|
|
1080 continue;
|
|
1081 }
|
|
1082
|
|
1083 return rom_base;
|
|
1084 }
|
|
1085 #endif
|
|
1086 return NULL;
|
|
1087 }
|
|
1088
|
|
1089
|
|
1090
|
|
1091 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
|
|
1092 {
|
|
1093 void *bios_header;
|
|
1094 void *header_ptr;
|
|
1095 u16 bios_header_offset, pll_info_offset;
|
|
1096 PLL_BLOCK pll;
|
|
1097
|
|
1098 if (bios_seg) {
|
|
1099 bios_header = bios_seg + 0x48L;
|
|
1100 header_ptr = bios_header;
|
|
1101
|
|
1102 bios_header_offset = readw(header_ptr);
|
|
1103 bios_header = bios_seg + bios_header_offset;
|
|
1104 bios_header += 0x30;
|
|
1105
|
|
1106 header_ptr = bios_header;
|
|
1107 pll_info_offset = readw(header_ptr);
|
|
1108 header_ptr = bios_seg + pll_info_offset;
|
|
1109
|
|
1110 memcpy_fromio(&pll, header_ptr, 50);
|
|
1111
|
|
1112 rinfo->pll.xclk = (u32)pll.XCLK;
|
|
1113 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
|
|
1114 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
|
|
1115 rinfo->pll.ppll_min = pll.PCLK_min_freq;
|
|
1116 rinfo->pll.ppll_max = pll.PCLK_max_freq;
|
|
1117 } else {
|
|
1118 /* no BIOS or BIOS not found, use defaults */
|
|
1119
|
|
1120 rinfo->pll.ppll_max = 35000;
|
|
1121 rinfo->pll.ppll_min = 12000;
|
|
1122 rinfo->pll.xclk = 16600;
|
|
1123 rinfo->pll.ref_div = 67;
|
|
1124 rinfo->pll.ref_clk = 2700;
|
|
1125 }
|
|
1126 }
|
|
1127
|
|
1128 static void radeon_engine_init (struct radeonfb_info *rinfo)
|
|
1129 {
|
|
1130 u32 temp;
|
|
1131
|
|
1132 /* disable 3D engine */
|
|
1133 OUTREG(RB3D_CNTL, 0);
|
|
1134
|
|
1135 radeon_engine_reset ();
|
|
1136
|
|
1137 radeon_fifo_wait (1);
|
|
1138 OUTREG(DSTCACHE_MODE, 0);
|
|
1139
|
|
1140 /* XXX */
|
|
1141 rinfo->pitch = ((rinfo->xres * (rinfo->depth / 8) + 0x3f)) >> 6;
|
|
1142
|
|
1143 radeon_fifo_wait (1);
|
|
1144 temp = INREG(DEFAULT_PITCH_OFFSET);
|
|
1145 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
|
|
1146 (rinfo->pitch << 0x16)));
|
|
1147
|
|
1148 radeon_fifo_wait (1);
|
|
1149 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
1150
|
|
1151 radeon_fifo_wait (1);
|
|
1152 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
|
|
1153 DEFAULT_SC_BOTTOM_MAX));
|
|
1154
|
|
1155 temp = radeon_get_dstbpp(rinfo->depth);
|
|
1156 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
|
|
1157 radeon_fifo_wait (1);
|
|
1158 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
1159 GMC_BRUSH_SOLID_COLOR |
|
|
1160 GMC_SRC_DATATYPE_COLOR));
|
|
1161
|
|
1162 radeon_fifo_wait (7);
|
|
1163
|
|
1164 /* clear line drawing regs */
|
|
1165 OUTREG(DST_LINE_START, 0);
|
|
1166 OUTREG(DST_LINE_END, 0);
|
|
1167
|
|
1168 /* set brush color regs */
|
|
1169 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
1170 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
1171
|
|
1172 /* set source color regs */
|
|
1173 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
1174 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
1175
|
|
1176 /* default write mask */
|
|
1177 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
1178
|
|
1179 radeon_engine_idle ();
|
|
1180 }
|
|
1181
|
|
1182
|
|
1183
|
|
1184 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
|
|
1185 {
|
|
1186 struct fb_info *info;
|
|
1187
|
|
1188 info = &rinfo->info;
|
|
1189
|
|
1190 strcpy (info->modename, rinfo->name);
|
|
1191 info->node = -1;
|
|
1192 info->flags = FBINFO_FLAG_DEFAULT;
|
|
1193 info->fbops = &radeon_fb_ops;
|
|
1194 info->display_fg = NULL;
|
|
1195 strncpy (info->fontname, fontname, sizeof (info->fontname));
|
|
1196 info->fontname[sizeof (info->fontname) - 1] = 0;
|
|
1197 info->changevar = NULL;
|
|
1198 info->switch_con = radeonfb_switch;
|
|
1199 info->updatevar = radeonfb_updatevar;
|
|
1200 info->blank = radeonfb_blank;
|
|
1201
|
|
1202 if (radeon_init_disp (rinfo) < 0)
|
|
1203 return -1;
|
|
1204
|
|
1205 return 0;
|
|
1206 }
|
|
1207
|
|
1208
|
|
1209
|
|
1210 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
|
|
1211 {
|
|
1212 struct fb_info *info;
|
|
1213 struct display *disp;
|
|
1214
|
|
1215 info = &rinfo->info;
|
|
1216 disp = &rinfo->disp;
|
|
1217
|
|
1218 disp->var = radeonfb_default_var;
|
|
1219 info->disp = disp;
|
|
1220
|
1914
|
1221 radeon_set_dispsw (rinfo, disp);
|
1911
|
1222
|
|
1223 if (noaccel)
|
|
1224 disp->scrollmode = SCROLL_YREDRAW;
|
|
1225 else
|
|
1226 disp->scrollmode = 0;
|
|
1227
|
|
1228 rinfo->currcon_display = disp;
|
|
1229
|
|
1230 if ((radeon_init_disp_var (rinfo)) < 0)
|
|
1231 return -1;
|
|
1232
|
|
1233 return 0;
|
|
1234 }
|
|
1235
|
|
1236
|
|
1237
|
|
1238 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
|
|
1239 {
|
|
1240 #ifndef MODULE
|
|
1241 if (mode_option)
|
|
1242 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
|
|
1243 NULL, 0, NULL, 8);
|
|
1244 else
|
|
1245 #endif
|
|
1246 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
|
|
1247 NULL, 0, NULL, 0);
|
|
1248
|
|
1249 if (noaccel)
|
|
1250 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
|
|
1251 else
|
|
1252 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
|
|
1253
|
|
1254 return 0;
|
|
1255 }
|
|
1256
|
|
1257
|
1914
|
1258 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
|
1911
|
1259 {
|
|
1260 int accel;
|
|
1261
|
|
1262 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
|
|
1263
|
|
1264 disp->dispsw_data = NULL;
|
|
1265
|
|
1266 disp->screen_base = (char*)rinfo->fb_base;
|
|
1267 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
1268 disp->type_aux = 0;
|
|
1269 disp->ypanstep = 1;
|
|
1270 disp->ywrapstep = 0;
|
|
1271 disp->can_soft_blank = 1;
|
|
1272 disp->inverse = 0;
|
|
1273
|
|
1274 rinfo->depth = disp->var.bits_per_pixel;
|
|
1275 switch (disp->var.bits_per_pixel) {
|
|
1276 #ifdef FBCON_HAS_CFB8
|
|
1277 case 8:
|
1914
|
1278 disp->dispsw = &fbcon_cfb8;
|
1911
|
1279 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1280 disp->line_length = disp->var.xres_virtual;
|
|
1281 break;
|
|
1282 #endif
|
|
1283 #ifdef FBCON_HAS_CFB16
|
|
1284 case 16:
|
|
1285 disp->dispsw = &fbcon_cfb16;
|
|
1286 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
1287 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1288 disp->line_length = disp->var.xres_virtual * 2;
|
|
1289 break;
|
|
1290 #endif
|
|
1291 #ifdef FBCON_HAS_CFB32
|
1914
|
1292 case 24:
|
|
1293 disp->dispsw = &fbcon_cfb24;
|
|
1294 disp->dispsw_data = &rinfo->con_cmap.cfb24;
|
|
1295 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1296 disp->line_length = disp->var.xres_virtual * 4;
|
|
1297 break;
|
|
1298 #endif
|
|
1299 #ifdef FBCON_HAS_CFB32
|
1911
|
1300 case 32:
|
|
1301 disp->dispsw = &fbcon_cfb32;
|
|
1302 disp->dispsw_data = &rinfo->con_cmap.cfb32;
|
|
1303 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1304 disp->line_length = disp->var.xres_virtual * 4;
|
|
1305 break;
|
|
1306 #endif
|
|
1307 default:
|
|
1308 printk ("radeonfb: setting fbcon_dummy renderer\n");
|
|
1309 disp->dispsw = &fbcon_dummy;
|
|
1310 }
|
|
1311
|
|
1312 return;
|
|
1313 }
|
|
1314
|
|
1315
|
|
1316
|
|
1317 /*
|
|
1318 * fb ops
|
|
1319 */
|
|
1320
|
|
1321 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
1322 struct fb_info *info)
|
|
1323 {
|
|
1324 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1325 struct display *disp;
|
|
1326
|
|
1327 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1328
|
|
1329 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
|
|
1330 strcpy (fix->id, rinfo->name);
|
|
1331
|
|
1332 fix->smem_start = rinfo->fb_base_phys;
|
|
1333 fix->smem_len = rinfo->video_ram;
|
|
1334
|
|
1335 fix->type = disp->type;
|
|
1336 fix->type_aux = disp->type_aux;
|
|
1337 fix->visual = disp->visual;
|
|
1338
|
|
1339 fix->xpanstep = 1;
|
|
1340 fix->ypanstep = 1;
|
|
1341 fix->ywrapstep = 0;
|
|
1342
|
|
1343 fix->line_length = disp->line_length;
|
|
1344
|
|
1345 fix->mmio_start = rinfo->mmio_base_phys;
|
|
1346 fix->mmio_len = RADEON_REGSIZE;
|
|
1347 if (noaccel)
|
|
1348 fix->accel = FB_ACCEL_NONE;
|
|
1349 else
|
|
1350 fix->accel = 40; /* XXX */
|
|
1351
|
|
1352 return 0;
|
|
1353 }
|
|
1354
|
|
1355
|
|
1356
|
|
1357 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
1358 struct fb_info *info)
|
|
1359 {
|
|
1360 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1361
|
|
1362 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
|
|
1363
|
|
1364 return 0;
|
|
1365 }
|
|
1366
|
|
1367
|
|
1368
|
|
1369 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
1370 struct fb_info *info)
|
|
1371 {
|
|
1372 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1373 struct display *disp;
|
|
1374 struct fb_var_screeninfo v;
|
1914
|
1375 int nom, den, accel;
|
1911
|
1376 unsigned chgvar = 0;
|
|
1377
|
|
1378 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1379
|
|
1380 accel = var->accel_flags & FB_ACCELF_TEXT;
|
|
1381
|
|
1382 if (con >= 0) {
|
|
1383 chgvar = ((disp->var.xres != var->xres) ||
|
|
1384 (disp->var.yres != var->yres) ||
|
|
1385 (disp->var.xres_virtual != var->xres_virtual) ||
|
|
1386 (disp->var.yres_virtual != var->yres_virtual) ||
|
1914
|
1387 (disp->var.bits_per_pixel != var->bits_per_pixel) ||
|
1911
|
1388 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
|
|
1389 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
|
|
1390 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
|
|
1391 }
|
|
1392
|
|
1393 memcpy (&v, var, sizeof (v));
|
|
1394
|
|
1395 switch (v.bits_per_pixel) {
|
|
1396 #ifdef FBCON_HAS_CFB8
|
|
1397 case 8:
|
|
1398 nom = den = 1;
|
|
1399 disp->line_length = v.xres_virtual;
|
|
1400 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1401 v.red.offset = v.green.offset = v.blue.offset = 0;
|
|
1402 v.red.length = v.green.length = v.blue.length = 8;
|
1914
|
1403 v.transp.offset = v.transp.length = 0;
|
1911
|
1404 break;
|
|
1405 #endif
|
|
1406
|
|
1407 #ifdef FBCON_HAS_CFB16
|
|
1408 case 16:
|
|
1409 nom = 2;
|
|
1410 den = 1;
|
|
1411 disp->line_length = v.xres_virtual * 2;
|
|
1412 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1413 v.red.offset = 11;
|
|
1414 v.green.offset = 5;
|
|
1415 v.blue.offset = 0;
|
|
1416 v.red.length = 5;
|
|
1417 v.green.length = 6;
|
|
1418 v.blue.length = 5;
|
1914
|
1419 v.transp.offset = v.transp.length = 0;
|
1911
|
1420 break;
|
|
1421 #endif
|
|
1422
|
1914
|
1423 #ifdef FBCON_HAS_CFB24
|
|
1424 case 24:
|
|
1425 nom = 4;
|
|
1426 den = 1;
|
|
1427 disp->line_length = v.xres_virtual * 3;
|
|
1428 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1429 v.red.offset = 16;
|
|
1430 v.green.offset = 8;
|
|
1431 v.blue.offset = 0;
|
|
1432 v.red.length = v.blue.length = v.green.length = 8;
|
|
1433 v.transp.offset = v.transp.length = 0;
|
|
1434 break;
|
|
1435 #endif
|
1911
|
1436 #ifdef FBCON_HAS_CFB32
|
|
1437 case 32:
|
|
1438 nom = 4;
|
|
1439 den = 1;
|
|
1440 disp->line_length = v.xres_virtual * 4;
|
|
1441 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1442 v.red.offset = 16;
|
|
1443 v.green.offset = 8;
|
|
1444 v.blue.offset = 0;
|
|
1445 v.red.length = v.blue.length = v.green.length = 8;
|
1914
|
1446 v.transp.offset = 24;
|
|
1447 v.transp.length = 8;
|
1911
|
1448 break;
|
|
1449 #endif
|
|
1450 default:
|
|
1451 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
|
|
1452 var->xres, var->yres, var->bits_per_pixel);
|
|
1453 return -EINVAL;
|
|
1454 }
|
|
1455
|
1914
|
1456 if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
|
|
1457 return -EINVAL;
|
1911
|
1458
|
|
1459 if (v.xoffset < 0)
|
|
1460 v.xoffset = 0;
|
|
1461 if (v.yoffset < 0)
|
|
1462 v.yoffset = 0;
|
|
1463
|
|
1464 if (v.xoffset > v.xres_virtual - v.xres)
|
|
1465 v.xoffset = v.xres_virtual - v.xres - 1;
|
|
1466
|
|
1467 if (v.yoffset > v.yres_virtual - v.yres)
|
|
1468 v.yoffset = v.yres_virtual - v.yres - 1;
|
|
1469
|
|
1470 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
|
|
1471 v.transp.offset = v.transp.length =
|
|
1472 v.transp.msb_right = 0;
|
|
1473
|
|
1474 switch (v.activate & FB_ACTIVATE_MASK) {
|
|
1475 case FB_ACTIVATE_TEST:
|
|
1476 return 0;
|
|
1477 case FB_ACTIVATE_NXTOPEN:
|
|
1478 case FB_ACTIVATE_NOW:
|
|
1479 break;
|
|
1480 default:
|
|
1481 return -EINVAL;
|
|
1482 }
|
|
1483
|
|
1484 memcpy (&disp->var, &v, sizeof (v));
|
|
1485
|
1914
|
1486 if (chgvar) {
|
|
1487 radeon_set_dispsw(rinfo, disp);
|
|
1488
|
|
1489 if (noaccel)
|
|
1490 disp->scrollmode = SCROLL_YREDRAW;
|
|
1491 else
|
|
1492 disp->scrollmode = 0;
|
|
1493
|
|
1494 if (info && info->changevar)
|
|
1495 info->changevar(con);
|
|
1496 }
|
|
1497
|
1911
|
1498 radeon_load_video_mode (rinfo, &v);
|
|
1499
|
1914
|
1500 do_install_cmap(con, info);
|
|
1501
|
1911
|
1502 return 0;
|
|
1503 }
|
|
1504
|
|
1505
|
|
1506
|
|
1507 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1508 struct fb_info *info)
|
|
1509 {
|
|
1510 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1511 struct display *disp;
|
|
1512
|
|
1513 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1514
|
|
1515 if (con == rinfo->currcon) {
|
|
1516 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
|
|
1517 return rc;
|
|
1518 } else if (disp->cmap.len)
|
|
1519 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
|
|
1520 else
|
|
1521 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
|
|
1522 cmap, kspc ? 0 : 2);
|
|
1523
|
|
1524 return 0;
|
|
1525 }
|
|
1526
|
|
1527
|
|
1528
|
|
1529 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1530 struct fb_info *info)
|
|
1531 {
|
|
1532 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1533 struct display *disp;
|
|
1534 unsigned int cmap_len;
|
|
1535
|
|
1536 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1537
|
|
1538 cmap_len = radeon_get_cmap_len (&disp->var);
|
|
1539 if (disp->cmap.len != cmap_len) {
|
|
1540 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
|
|
1541 if (err)
|
|
1542 return err;
|
|
1543 }
|
|
1544
|
|
1545 if (con == rinfo->currcon) {
|
|
1546 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
|
|
1547 return rc;
|
|
1548 } else
|
|
1549 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
|
|
1550
|
|
1551 return 0;
|
|
1552 }
|
|
1553
|
|
1554
|
|
1555
|
|
1556 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
1557 struct fb_info *info)
|
|
1558 {
|
|
1559 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1560 u32 offset, xoffset, yoffset;
|
|
1561
|
|
1562 xoffset = (var->xoffset + 7) & ~7;
|
|
1563 yoffset = var->yoffset;
|
1911
|
1564
|
1914
|
1565 if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
|
|
1566 var->yres_virtual))
|
|
1567 return -EINVAL;
|
1911
|
1568
|
1914
|
1569 offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
|
|
1570
|
|
1571 OUTREG(CRTC_OFFSET, offset);
|
1911
|
1572
|
|
1573 return 0;
|
|
1574 }
|
|
1575
|
|
1576
|
1914
|
1577 static void do_install_cmap(int con, struct fb_info *info)
|
|
1578 {
|
|
1579 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1580
|
|
1581 if (con != rinfo->currcon)
|
|
1582 return;
|
|
1583
|
|
1584 if (fb_display[con].cmap.len)
|
|
1585 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
|
|
1586 else {
|
|
1587 int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
|
|
1588 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
|
|
1589 }
|
|
1590 }
|
|
1591
|
|
1592
|
|
1593 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
1594 struct fb_var_screeninfo *var,
|
|
1595 struct fb_var_screeninfo *v,
|
|
1596 int nom, int den)
|
|
1597 {
|
|
1598 static struct {
|
|
1599 int xres, yres;
|
|
1600 } modes[] = {
|
|
1601 {1600, 1280},
|
|
1602 {1280, 1024},
|
|
1603 {1024, 768},
|
|
1604 {800, 600},
|
|
1605 {640, 480},
|
|
1606 {-1, -1}
|
|
1607 };
|
|
1608 int i;
|
|
1609
|
|
1610 /* use highest possible virtual resolution */
|
|
1611 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
|
|
1612 printk("radeonfb: using max availabe virtual resolution\n");
|
|
1613 for (i=0; modes[i].xres != -1; i++) {
|
|
1614 if (modes[i].xres * nom / den * modes[i].yres <
|
|
1615 rinfo->video_ram / 2)
|
|
1616 break;
|
|
1617 }
|
|
1618 if (modes[i].xres == -1) {
|
|
1619 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
|
|
1620 return -EINVAL;
|
|
1621 }
|
|
1622 v->xres_virtual = modes[i].xres;
|
|
1623 v->yres_virtual = modes[i].yres;
|
|
1624
|
|
1625 printk("radeonfb: virtual resolution set to max of %dx%d\n",
|
|
1626 v->xres_virtual, v->yres_virtual);
|
|
1627 } else if (v->xres_virtual == -1) {
|
|
1628 v->xres_virtual = (rinfo->video_ram * den /
|
|
1629 (nom * v->yres_virtual * 2)) & ~15;
|
|
1630 } else if (v->yres_virtual == -1) {
|
|
1631 v->xres_virtual = (v->xres_virtual + 15) & ~15;
|
|
1632 v->yres_virtual = rinfo->video_ram * den /
|
|
1633 (nom * v->xres_virtual *2);
|
|
1634 } else {
|
|
1635 if (v->xres_virtual * nom / den * v->yres_virtual >
|
|
1636 rinfo->video_ram) {
|
|
1637 return -EINVAL;
|
|
1638 }
|
|
1639 }
|
|
1640
|
|
1641 if (v->xres_virtual * nom / den >= 8192) {
|
|
1642 v->xres_virtual = 8192 * den / nom - 16;
|
|
1643 }
|
|
1644
|
|
1645 if (v->xres_virtual < v->xres)
|
|
1646 return -EINVAL;
|
|
1647
|
|
1648 if (v->yres_virtual < v->yres)
|
|
1649 return -EINVAL;
|
|
1650
|
|
1651 return 0;
|
|
1652 }
|
|
1653
|
1911
|
1654
|
|
1655 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
1656 unsigned long arg, int con, struct fb_info *info)
|
|
1657 {
|
|
1658 return -EINVAL;
|
|
1659 }
|
|
1660
|
|
1661
|
|
1662
|
|
1663 static int radeonfb_switch (int con, struct fb_info *info)
|
|
1664 {
|
|
1665 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1666 struct display *disp;
|
|
1667 struct fb_cmap *cmap;
|
|
1668 int switchcon = 0;
|
1914
|
1669
|
1911
|
1670 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1671
|
|
1672 if (rinfo->currcon >= 0) {
|
|
1673 cmap = &(rinfo->currcon_display->cmap);
|
|
1674 if (cmap->len)
|
|
1675 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
|
|
1676 }
|
|
1677
|
|
1678 if ((disp->var.xres != rinfo->xres) ||
|
|
1679 (disp->var.yres != rinfo->yres) ||
|
|
1680 (disp->var.pixclock != rinfo->pixclock) ||
|
|
1681 (disp->var.bits_per_pixel != rinfo->depth))
|
|
1682 switchcon = 1;
|
|
1683
|
|
1684 if (switchcon) {
|
|
1685 rinfo->currcon = con;
|
|
1686 rinfo->currcon_display = disp;
|
|
1687 disp->var.activate = FB_ACTIVATE_NOW;
|
|
1688
|
|
1689 radeonfb_set_var (&disp->var, con, info);
|
1914
|
1690 radeon_set_dispsw (rinfo, disp);
|
|
1691 do_install_cmap(con, info);
|
1911
|
1692 }
|
1914
|
1693
|
|
1694 /* XXX absurd hack for X to restore console */
|
|
1695 {
|
|
1696 OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
|
1697 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
|
1698 }
|
|
1699
|
1911
|
1700 return 0;
|
|
1701 }
|
|
1702
|
|
1703
|
|
1704
|
|
1705 static int radeonfb_updatevar (int con, struct fb_info *info)
|
|
1706 {
|
|
1707 int rc;
|
|
1708
|
|
1709 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
|
|
1710 con, info);
|
|
1711
|
|
1712 return rc;
|
|
1713 }
|
|
1714
|
|
1715 static void radeonfb_blank (int blank, struct fb_info *info)
|
|
1716 {
|
|
1717 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1718 u32 val = INREG(CRTC_EXT_CNTL);
|
|
1719
|
|
1720 /* reset it */
|
|
1721 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
|
|
1722 CRTC_VSYNC_DIS);
|
1911
|
1723
|
|
1724 switch (blank) {
|
1914
|
1725 case VESA_NO_BLANKING:
|
|
1726 break;
|
|
1727 case VESA_VSYNC_SUSPEND:
|
|
1728 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
|
1911
|
1729 break;
|
1914
|
1730 case VESA_HSYNC_SUSPEND:
|
|
1731 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
|
1911
|
1732 break;
|
1914
|
1733 case VESA_POWERDOWN:
|
|
1734 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
|
|
1735 CRTC_HSYNC_DIS);
|
1911
|
1736 break;
|
|
1737 }
|
1915
|
1738 if(blank == VESA_NO_BLANKING && rinfo->hasCRTC2)
|
|
1739 OUTREGP(CRTC_EXT_CNTL,CRTC_CRT_ON, val);
|
|
1740 else OUTREG(CRTC_EXT_CNTL, val);
|
1911
|
1741 }
|
|
1742
|
|
1743
|
|
1744
|
|
1745 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
|
|
1746 {
|
|
1747 int rc = 16; /* reasonable default */
|
|
1748
|
|
1749 switch (var->bits_per_pixel) {
|
|
1750 case 8:
|
|
1751 rc = 256;
|
|
1752 break;
|
|
1753 case 16:
|
|
1754 rc = 64;
|
|
1755 break;
|
|
1756 default:
|
|
1757 rc = 32;
|
|
1758 break;
|
|
1759 }
|
|
1760
|
|
1761 return rc;
|
|
1762 }
|
|
1763
|
|
1764
|
|
1765
|
|
1766 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
1767 unsigned *blue, unsigned *transp,
|
|
1768 struct fb_info *info)
|
|
1769 {
|
|
1770 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1771
|
|
1772 if (regno > 255)
|
|
1773 return 1;
|
|
1774
|
|
1775 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
|
|
1776 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
|
|
1777 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
|
|
1778 *transp = 0;
|
|
1779
|
|
1780 return 0;
|
|
1781 }
|
|
1782
|
|
1783
|
|
1784
|
|
1785 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
1786 unsigned blue, unsigned transp, struct fb_info *info)
|
|
1787 {
|
|
1788 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1789 u32 pindex;
|
1911
|
1790
|
|
1791 if (regno > 255)
|
|
1792 return 1;
|
|
1793
|
|
1794 red >>= 8;
|
|
1795 green >>= 8;
|
|
1796 blue >>= 8;
|
|
1797 rinfo->palette[regno].red = red;
|
|
1798 rinfo->palette[regno].green = green;
|
|
1799 rinfo->palette[regno].blue = blue;
|
|
1800
|
|
1801 /* init gamma for hicolor */
|
|
1802 if ((rinfo->depth > 8) && (regno == 0)) {
|
|
1803 int i;
|
|
1804
|
|
1805 for (i=0; i<255; i++) {
|
|
1806 OUTREG(PALETTE_INDEX, i);
|
1914
|
1807 OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
|
1911
|
1808 }
|
|
1809 }
|
|
1810
|
|
1811 /* default */
|
|
1812 pindex = regno;
|
1914
|
1813
|
|
1814 /* XXX actually bpp, fixme */
|
|
1815 if (rinfo->depth == 16)
|
|
1816 pindex = regno * 8;
|
|
1817
|
|
1818 if (rinfo->depth == 16) {
|
|
1819 OUTREG(PALETTE_INDEX, pindex/2);
|
|
1820 OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
|
|
1821 (green << 8) | (rinfo->palette[regno/2].blue));
|
|
1822 green = rinfo->palette[regno/2].green;
|
|
1823 }
|
|
1824
|
|
1825 if ((rinfo->depth == 8) || (regno < 32)) {
|
|
1826 OUTREG(PALETTE_INDEX, pindex);
|
|
1827 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
|
|
1828 }
|
|
1829
|
|
1830 #if 0
|
1911
|
1831 col = (red << 16) | (green << 8) | blue;
|
|
1832
|
|
1833 if (rinfo->depth == 16) {
|
|
1834 pindex = regno << 3;
|
|
1835
|
|
1836 if ((rinfo->depth == 16) && (regno >= 32)) {
|
|
1837 pindex -= 252;
|
|
1838
|
|
1839 col = (rinfo->palette[regno >> 1].red << 16) |
|
|
1840 (green << 8) |
|
|
1841 (rinfo->palette[regno >> 1].blue);
|
|
1842 } else {
|
|
1843 col = (red << 16) | (green << 8) | blue;
|
|
1844 }
|
|
1845 }
|
|
1846
|
|
1847 OUTREG8(PALETTE_INDEX, pindex);
|
|
1848 radeon_fifo_wait(32);
|
|
1849 OUTREG(PALETTE_DATA, col);
|
1914
|
1850 #endif
|
1911
|
1851
|
|
1852 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
1853 if (regno < 32) {
|
|
1854 switch (rinfo->depth) {
|
|
1855 #ifdef FBCON_HAS_CFB16
|
|
1856 case 16:
|
1914
|
1857 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
|
1911
|
1858 regno;
|
|
1859 break;
|
|
1860 #endif
|
1914
|
1861 #ifdef FBCON_HAS_CFB24
|
|
1862 case 24:
|
|
1863 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
|
|
1864 break;
|
|
1865 #endif
|
1911
|
1866 #ifdef FBCON_HAS_CFB32
|
|
1867 case 32: {
|
|
1868 u32 i;
|
|
1869
|
|
1870 i = (regno << 8) | regno;
|
|
1871 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
|
|
1872 break;
|
|
1873 }
|
|
1874 #endif
|
|
1875 }
|
|
1876 }
|
|
1877 #endif
|
|
1878 return 0;
|
|
1879 }
|
|
1880
|
|
1881
|
|
1882
|
|
1883 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
1884 struct radeon_regs *save)
|
|
1885 {
|
|
1886 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
|
|
1887 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
|
|
1888 save->dac_cntl = INREG(DAC_CNTL);
|
|
1889 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
|
|
1890 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
|
|
1891 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
|
|
1892 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
|
|
1893 save->crtc_pitch = INREG(CRTC_PITCH);
|
|
1894 }
|
|
1895
|
|
1896
|
|
1897
|
|
1898 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
1899 struct fb_var_screeninfo *mode)
|
|
1900 {
|
|
1901 struct radeon_regs newmode;
|
|
1902 int hTotal, vTotal, hSyncStart, hSyncEnd,
|
|
1903 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
|
|
1904 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
|
|
1905 u32 dotClock = 1000000000 / mode->pixclock,
|
|
1906 sync, h_sync_pol, v_sync_pol;
|
|
1907 int freq = dotClock / 10; /* x 100 */
|
|
1908 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
|
|
1909 int useable_precision, roff, ron;
|
|
1910 int min_bits, format = 0;
|
|
1911 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
|
|
1912
|
|
1913 rinfo->xres = mode->xres;
|
|
1914 rinfo->yres = mode->yres;
|
|
1915 rinfo->pixclock = mode->pixclock;
|
|
1916
|
|
1917 hSyncStart = mode->xres + mode->right_margin;
|
|
1918 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1919 hTotal = hSyncEnd + mode->left_margin;
|
|
1920
|
|
1921 vSyncStart = mode->yres + mode->lower_margin;
|
|
1922 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1923 vTotal = vSyncEnd + mode->upper_margin;
|
|
1924
|
|
1925 sync = mode->sync;
|
|
1926 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1927 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
|
1928
|
|
1929 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
|
|
1930 hSyncStart, hSyncEnd, hTotal);
|
|
1931 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
|
|
1932 vSyncStart, vSyncEnd, vTotal);
|
|
1933
|
|
1934 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1935 vsync_wid = vSyncEnd - vSyncStart;
|
|
1936 if (hsync_wid == 0)
|
|
1937 hsync_wid = 1;
|
|
1938 else if (hsync_wid > 0x3f) /* max */
|
|
1939 hsync_wid = 0x3f;
|
1914
|
1940 vsync_wid = mode->vsync_len;
|
1911
|
1941 if (vsync_wid == 0)
|
|
1942 vsync_wid = 1;
|
|
1943 else if (vsync_wid > 0x1f) /* max */
|
|
1944 vsync_wid = 0x1f;
|
|
1945
|
1914
|
1946 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1947 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
1911
|
1948
|
|
1949 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
|
1950
|
|
1951 switch (mode->bits_per_pixel) {
|
|
1952 case 8:
|
|
1953 format = DST_8BPP;
|
|
1954 bytpp = 1;
|
|
1955 break;
|
|
1956 case 16:
|
|
1957 format = DST_16BPP;
|
|
1958 bytpp = 2;
|
|
1959 break;
|
|
1960 case 24:
|
|
1961 format = DST_24BPP;
|
|
1962 bytpp = 3;
|
|
1963 break;
|
|
1964 case 32:
|
|
1965 format = DST_32BPP;
|
|
1966 bytpp = 4;
|
|
1967 break;
|
|
1968 }
|
|
1969
|
|
1970 hsync_fudge = hsync_adj_tab[format-1];
|
|
1971 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1972
|
|
1973 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
|
|
1974 (format << 8);
|
1915
|
1975 if(rinfo->hasCRTC2)
|
|
1976 /* HACKED: !!! Enable CRT port here !!! */
|
|
1977 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
|
|
1978 else newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
|
1911
|
1979 newmode.dac_cntl = INREG(DAC_CNTL) | DAC_MASK_ALL | DAC_VGA_ADR_EN |
|
|
1980 DAC_8BIT_EN;
|
|
1981
|
1951
|
1982 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
|
|
1983 ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
1911
|
1984
|
|
1985 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
|
1914
|
1986 (hsync_wid << 16) | (h_sync_pol << 23));
|
1911
|
1987
|
|
1988 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
|
1989 ((mode->yres - 1) << 16);
|
|
1990
|
|
1991 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
|
1914
|
1992 (vsync_wid << 16) | (v_sync_pol << 23));
|
1911
|
1993
|
|
1994 newmode.crtc_pitch = (mode->xres >> 3);
|
|
1995
|
1915
|
1996 #if defined(__BIG_ENDIAN)
|
1914
|
1997 newmode.surface_cntl = SURF_TRANSLATION_DIS;
|
|
1998 switch (mode->bits_per_pixel) {
|
|
1999 case 16:
|
|
2000 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
|
2001 break;
|
|
2002 case 24:
|
|
2003 case 32:
|
|
2004 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
|
|
2005 break;
|
|
2006 }
|
|
2007 #endif
|
|
2008
|
1911
|
2009 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
|
2010 & ~(0x3f)) / 64;
|
|
2011
|
|
2012 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
|
|
2013 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
|
|
2014 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
|
|
2015 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
|
|
2016
|
|
2017 newmode.xres = mode->xres;
|
|
2018 newmode.yres = mode->yres;
|
|
2019
|
|
2020 rinfo->bpp = mode->bits_per_pixel;
|
1914
|
2021 rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
|
|
2022 rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
|
1911
|
2023
|
|
2024 if (freq > rinfo->pll.ppll_max)
|
|
2025 freq = rinfo->pll.ppll_max;
|
|
2026 if (freq*12 < rinfo->pll.ppll_min)
|
|
2027 freq = rinfo->pll.ppll_min / 12;
|
|
2028
|
|
2029 {
|
|
2030 struct {
|
|
2031 int divider;
|
|
2032 int bitvalue;
|
|
2033 } *post_div,
|
|
2034 post_divs[] = {
|
|
2035 { 1, 0 },
|
|
2036 { 2, 1 },
|
|
2037 { 4, 2 },
|
|
2038 { 8, 3 },
|
|
2039 { 3, 4 },
|
|
2040 { 16, 5 },
|
|
2041 { 6, 6 },
|
|
2042 { 12, 7 },
|
|
2043 { 0, 0 },
|
|
2044 };
|
|
2045
|
|
2046 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
2047 rinfo->pll_output_freq = post_div->divider * freq;
|
|
2048 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
|
|
2049 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
|
|
2050 break;
|
|
2051 }
|
|
2052
|
|
2053 rinfo->post_div = post_div->divider;
|
|
2054 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
|
|
2055 rinfo->pll.ref_clk);
|
|
2056 newmode.ppll_ref_div = rinfo->pll.ref_div;
|
|
2057 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
|
|
2058 }
|
|
2059
|
|
2060 RTRACE("post div = 0x%x\n", rinfo->post_div);
|
|
2061 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
|
|
2062 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
|
|
2063
|
|
2064 /* DDA */
|
|
2065 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
|
|
2066 rinfo->pll.ref_div * rinfo->post_div);
|
|
2067 xclk_freq = rinfo->pll.xclk;
|
|
2068
|
|
2069 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
|
|
2070
|
|
2071 min_bits = min_bits_req(xclk_per_trans);
|
|
2072 useable_precision = min_bits + 1;
|
|
2073
|
|
2074 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
|
|
2075 vclk_freq * mode->bits_per_pixel);
|
|
2076
|
|
2077 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
|
|
2078 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
|
|
2079 xclk_per_trans) << (11 - useable_precision);
|
|
2080 roff = xclk_per_trans_precise * (32 - 4);
|
|
2081
|
|
2082 RTRACE("ron = %d, roff = %d\n", ron, roff);
|
|
2083 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
|
|
2084
|
|
2085 if ((ron + rinfo->ram.rloop) >= roff) {
|
|
2086 printk("radeonfb: error ron out of range\n");
|
|
2087 return;
|
|
2088 }
|
|
2089
|
|
2090 newmode.dda_config = (xclk_per_trans_precise |
|
|
2091 (useable_precision << 16) |
|
|
2092 (rinfo->ram.rloop << 20));
|
|
2093 newmode.dda_on_off = (ron << 16) | roff;
|
|
2094
|
|
2095 /* do it! */
|
|
2096 radeon_write_mode (rinfo, &newmode);
|
1915
|
2097 /* XXX absurd hack for X to restore console on VE */
|
|
2098 if(rinfo->hasCRTC2 && rinfo->crtDispType == MT_CRT &&
|
|
2099 (rinfo->dviDispType == MT_NONE || rinfo->dviDispType == MT_STV)) {
|
|
2100 OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
|
2101 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
|
2102 }
|
1911
|
2103 return;
|
|
2104 }
|
|
2105
|
|
2106
|
1915
|
2107 /*****
|
|
2108 When changing mode with Dual-head card (VE/M6), care must
|
|
2109 be taken for the special order in setting registers. CRTC2 has
|
|
2110 to be set before changing CRTC_EXT register.
|
|
2111 Otherwise we may get a blank screen.
|
|
2112 *****/
|
1911
|
2113
|
|
2114 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
2115 struct radeon_regs *mode)
|
|
2116 {
|
|
2117 int i;
|
|
2118
|
|
2119 /* blank screen */
|
|
2120 OUTREG8(CRTC_EXT_CNTL + 1, 4);
|
|
2121
|
|
2122 for (i=0; i<9; i++)
|
|
2123 OUTREG(common_regs[i].reg, common_regs[i].val);
|
|
2124
|
|
2125 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
|
|
2126 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
|
2127 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
|
|
2128 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
|
|
2129 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
|
|
2130 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
|
|
2131 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
|
|
2132 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
|
|
2133 OUTREG(CRTC_OFFSET, 0);
|
|
2134 OUTREG(CRTC_OFFSET_CNTL, 0);
|
|
2135 OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
1915
|
2136 #if defined(__BIG_ENDIAN)
|
|
2137 /* XXX this code makes degradation of mplayer quality on Radeon VE */
|
1914
|
2138 OUTREG(SURFACE_CNTL, mode->surface_cntl);
|
1915
|
2139 #endif
|
|
2140 /* Here we should restore FP registers for LCD & DFP monitors */
|
1911
|
2141
|
|
2142 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
|
|
2143 PPLL_DIV_SEL_MASK) {
|
|
2144 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
|
|
2145 }
|
|
2146
|
|
2147 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
|
|
2148
|
|
2149 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
|
|
2150 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
|
|
2151 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
|
2152 }
|
|
2153
|
|
2154 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
|
|
2155 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
|
|
2156 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
|
2157 }
|
|
2158
|
|
2159 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
|
|
2160 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
|
|
2161 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
|
2162 }
|
|
2163
|
|
2164 OUTPLL(HTOTAL_CNTL, 0);
|
|
2165
|
|
2166 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
|
|
2167
|
|
2168 OUTREG(DDA_CONFIG, mode->dda_config);
|
|
2169 OUTREG(DDA_ON_OFF, mode->dda_on_off);
|
|
2170
|
|
2171 /* unblank screen */
|
|
2172 OUTREG8(CRTC_EXT_CNTL + 1, 0);
|
|
2173
|
|
2174 return;
|
|
2175 }
|
|
2176
|
1914
|
2177 #if 0
|
1911
|
2178
|
|
2179 /*
|
|
2180 * text console acceleration
|
|
2181 */
|
|
2182
|
|
2183
|
|
2184 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
|
|
2185 int dsty, int dstx, int height, int width)
|
|
2186 {
|
|
2187 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
2188 u32 dp_cntl = DST_LAST_PEL;
|
|
2189
|
|
2190 srcx *= fontwidth(p);
|
|
2191 srcy *= fontheight(p);
|
|
2192 dstx *= fontwidth(p);
|
|
2193 dsty *= fontheight(p);
|
|
2194 width *= fontwidth(p);
|
|
2195 height *= fontheight(p);
|
|
2196
|
|
2197 if (srcy < dsty) {
|
|
2198 srcy += height - 1;
|
|
2199 dsty += height - 1;
|
|
2200 } else
|
|
2201 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
|
|
2202
|
|
2203 if (srcx < dstx) {
|
|
2204 srcx += width - 1;
|
|
2205 dstx += width - 1;
|
|
2206 } else
|
|
2207 dp_cntl |= DST_X_LEFT_TO_RIGHT;
|
|
2208
|
|
2209 radeon_fifo_wait(6);
|
|
2210 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2211 GMC_BRUSH_NONE |
|
|
2212 GMC_SRC_DATATYPE_COLOR |
|
|
2213 ROP3_S |
|
|
2214 DP_SRC_SOURCE_MEMORY));
|
|
2215 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2216 OUTREG(DP_CNTL, dp_cntl);
|
|
2217 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
|
|
2218 OUTREG(DST_Y_X, (dsty << 16) | dstx);
|
|
2219 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
|
|
2220 }
|
|
2221
|
|
2222
|
|
2223
|
|
2224 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|
2225 int srcy, int srcx, int height, int width)
|
|
2226 {
|
|
2227 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
2228 u32 clr;
|
|
2229
|
|
2230 clr = attr_bgcol_ec(p, conp);
|
|
2231 clr |= (clr << 8);
|
|
2232 clr |= (clr << 16);
|
|
2233
|
|
2234 srcx *= fontwidth(p);
|
|
2235 srcy *= fontheight(p);
|
|
2236 width *= fontwidth(p);
|
|
2237 height *= fontheight(p);
|
|
2238
|
|
2239 radeon_fifo_wait(6);
|
|
2240 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2241 GMC_BRUSH_SOLID_COLOR |
|
|
2242 GMC_SRC_DATATYPE_COLOR |
|
|
2243 ROP3_P));
|
|
2244 OUTREG(DP_BRUSH_FRGD_CLR, clr);
|
|
2245 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2246 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
|
|
2247 OUTREG(DST_Y_X, (srcy << 16) | srcx);
|
|
2248 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
|
|
2249 }
|
|
2250
|
|
2251
|
|
2252
|
|
2253
|
|
2254 #ifdef FBCON_HAS_CFB8
|
|
2255 static struct display_switch fbcon_radeon8 = {
|
|
2256 setup: fbcon_cfb8_setup,
|
|
2257 bmove: fbcon_radeon_bmove,
|
|
2258 clear: fbcon_cfb8_clear,
|
|
2259 putc: fbcon_cfb8_putc,
|
|
2260 putcs: fbcon_cfb8_putcs,
|
|
2261 revc: fbcon_cfb8_revc,
|
|
2262 clear_margins: fbcon_cfb8_clear_margins,
|
|
2263 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
|
2264 };
|
|
2265 #endif
|
1914
|
2266
|
|
2267 #endif /* 0 */
|