Mercurial > mplayer.hg
annotate cpudetect.c @ 4042:d651a7b5d213
STREAMTYPE_PLAYLIST introduced. similar to STREAMTYPE_STREAM but used for playlists. patch by Alban Bedel <albeu@free.fr>
author | arpi |
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date | Tue, 08 Jan 2002 01:19:54 +0000 |
parents | ca9cc0aaacc7 |
children | 35ed5387b804 |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
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3 |
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4 CpuCaps gCpuCaps; |
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5 |
3837 | 6 #ifdef HAVE_MALLOC_H |
7 #include <malloc.h> | |
8 #endif | |
9 #include <stdlib.h> | |
10 | |
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11 #ifdef ARCH_X86 |
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12 |
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13 #include <stdio.h> |
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14 |
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15 #ifdef __FreeBSD__ |
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16 #include <sys/types.h> |
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17 #include <sys/sysctl.h> |
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18 #endif |
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19 |
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20 #ifdef __linux__ |
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21 #include <signal.h> |
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22 #endif |
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23 |
2272 | 24 //#define X86_FXSR_MAGIC |
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25 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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26 * help understanding how to use it. Thanks to the Mesa |
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27 * team for SSE support detection and more cpu detect code. |
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28 */ |
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29 |
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30 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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31 |
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32 static void check_os_katmai_support( void ); |
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33 |
2272 | 34 #if 1 |
35 // return TRUE if cpuid supported | |
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36 static int has_cpuid() |
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37 { |
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38 int a, c; |
2272 | 39 |
40 // code from libavcodec: | |
41 __asm__ __volatile__ ( | |
42 /* See if CPUID instruction is supported ... */ | |
43 /* ... Get copies of EFLAGS into eax and ecx */ | |
44 "pushf\n\t" | |
45 "popl %0\n\t" | |
46 "movl %0, %1\n\t" | |
47 | |
48 /* ... Toggle the ID bit in one copy and store */ | |
49 /* to the EFLAGS reg */ | |
50 "xorl $0x200000, %0\n\t" | |
51 "push %0\n\t" | |
52 "popf\n\t" | |
53 | |
54 /* ... Get the (hopefully modified) EFLAGS */ | |
55 "pushf\n\t" | |
56 "popl %0\n\t" | |
57 : "=a" (a), "=c" (c) | |
58 : | |
59 : "cc" | |
60 ); | |
61 | |
62 return (a!=c); | |
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63 } |
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64 #endif |
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65 |
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66 static void |
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67 do_cpuid(unsigned int ax, unsigned int *p) |
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68 { |
2272 | 69 #if 0 |
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70 __asm __volatile( |
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71 "cpuid;" |
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72 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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73 : "0" (ax) |
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74 ); |
2272 | 75 #else |
76 // code from libavcodec: | |
77 __asm __volatile | |
78 ("movl %%ebx, %%esi\n\t" | |
79 "cpuid\n\t" | |
80 "xchgl %%ebx, %%esi" | |
3403 | 81 : "=a" (p[0]), "=S" (p[1]), |
2272 | 82 "=c" (p[2]), "=d" (p[3]) |
83 : "0" (ax)); | |
84 #endif | |
85 | |
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86 } |
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87 |
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88 void GetCpuCaps( CpuCaps *caps) |
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89 { |
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90 unsigned int regs[4]; |
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91 unsigned int regs2[4]; |
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92 |
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93 caps->isX86=1; |
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94 |
3700 | 95 memset(caps, 0, sizeof(*caps)); |
2288 | 96 if (!has_cpuid()) { |
97 printf("CPUID not supported!???\n"); | |
98 return; | |
99 } | |
100 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
3837 | 101 printf("CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
102 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
2288 | 103 if (regs[0]>=0x00000001) |
2280 | 104 { |
2303 | 105 char *tmpstr; |
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106 |
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107 do_cpuid(0x00000001, regs2); |
2301 | 108 |
2303 | 109 tmpstr=GetCpuFriendlyName(regs, regs2); |
3403 | 110 printf("CPU: %s ",tmpstr); |
2303 | 111 free(tmpstr); |
2301 | 112 |
2288 | 113 caps->cpuType=(regs2[0] >> 8)&0xf; |
114 if(caps->cpuType==0xf){ | |
115 // use extended family (P4, IA64) | |
116 caps->cpuType=8+((regs2[0]>>20)&255); | |
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117 } |
3403 | 118 caps->cpuStepping=regs2[0] & 0xf; |
119 printf("(Type: %d, Stepping: %d)\n", | |
120 caps->cpuType, caps->cpuStepping); | |
2288 | 121 |
122 // general feature flags: | |
2272 | 123 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
124 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
125 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 126 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
127 } | |
128 do_cpuid(0x80000000, regs); | |
129 if (regs[0]>=0x80000001) { | |
130 printf("extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
131 do_cpuid(0x80000001, regs2); | |
3840 | 132 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
133 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 134 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
135 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
136 } | |
137 #if 0 | |
138 printf("cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", | |
139 gCpuCaps.hasMMX, | |
140 gCpuCaps.hasMMX2, | |
141 gCpuCaps.hasSSE, | |
142 gCpuCaps.hasSSE2, | |
143 gCpuCaps.has3DNow, | |
144 gCpuCaps.has3DNowExt ); | |
145 #endif | |
146 | |
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147 /* FIXME: Does SSE2 need more OS support, too? */ |
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148 #if defined(__linux__) || defined(__FreeBSD__) |
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149 if (caps->hasSSE) |
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150 check_os_katmai_support(); |
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151 if (!caps->hasSSE) |
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152 caps->hasSSE2 = 0; |
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153 #else |
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154 caps->hasSSE=0; |
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155 caps->hasSSE2 = 0; |
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156 #endif |
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157 // caps->has3DNow=1; |
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158 // caps->hasMMX2 = 0; |
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159 // caps->hasMMX = 0; |
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160 |
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161 } |
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162 |
2301 | 163 |
164 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
165 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
166 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
167 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
168 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
169 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
170 | |
171 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
172 #include "cputable.h" /* get cpuname and cpuvendors */ | |
173 char vendor[17]; | |
2303 | 174 char *retname; |
2301 | 175 int i; |
176 | |
2417 | 177 if (NULL==(retname=(char*)malloc(256))) { |
2303 | 178 printf("Error: GetCpuFriendlyName() not enough memory\n"); |
179 exit(1); | |
180 } | |
181 | |
3837 | 182 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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183 |
2301 | 184 for(i=0; i<MAX_VENDORS; i++){ |
185 if(!strcmp(cpuvendors[i].string,vendor)){ | |
186 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
2303 | 187 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 188 } else { |
2303 | 189 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
2301 | 190 printf("unknown %s CPU:\n",cpuvendors[i].name); |
191 printf("Vendor: %s\n",cpuvendors[i].string); | |
192 printf("Type: %d\n",CPUID_TYPE); | |
193 printf("Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
194 printf("Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
195 printf("Stepping: %d\n",CPUID_STEPPING); | |
196 printf("Please send the above info along with the exact CPU name" | |
197 "to the MPlayer-Developers, so we can add it to the list!\n"); | |
198 } | |
199 } | |
200 } | |
201 | |
202 //printf("Detected CPU: %s\n", retname); | |
203 return retname; | |
204 } | |
205 | |
206 #undef CPUID_EXTFAMILY | |
207 #undef CPUID_EXTMODEL | |
208 #undef CPUID_TYPE | |
209 #undef CPUID_FAMILY | |
210 #undef CPUID_MODEL | |
211 #undef CPUID_STEPPING | |
212 | |
213 | |
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214 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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215 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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216 { |
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217 printf( "SIGILL, " ); |
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218 |
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219 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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220 * instructions are 3 bytes long. We must increment the instruction |
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221 * pointer manually to avoid repeated execution of the offending |
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222 * instruction. |
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223 * |
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224 * If the SIGILL is caused by a divide-by-zero when unmasked |
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225 * exceptions aren't supported, the SIMD FPU status and control |
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226 * word will be restored at the end of the test, so we don't need |
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227 * to worry about doing it here. Besides, we may not be able to... |
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228 */ |
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229 sc.eip += 3; |
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230 |
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231 gCpuCaps.hasSSE=0; |
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232 } |
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233 |
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234 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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235 { |
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236 printf( "SIGFPE, " ); |
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237 |
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238 if ( sc.fpstate->magic != 0xffff ) { |
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239 /* Our signal context has the extended FPU state, so reset the |
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240 * divide-by-zero exception mask and clear the divide-by-zero |
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241 * exception bit. |
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242 */ |
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243 sc.fpstate->mxcsr |= 0x00000200; |
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244 sc.fpstate->mxcsr &= 0xfffffffb; |
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245 } else { |
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246 /* If we ever get here, we're completely hosed. |
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247 */ |
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248 printf( "\n\n" ); |
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249 printf( "SSE enabling test failed badly!" ); |
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250 } |
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251 } |
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252 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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253 |
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254 /* If we're running on a processor that can do SSE, let's see if we |
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255 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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256 * haven't been configured for a Pentium III but are running on one, |
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257 * and RedHat patched 2.2 kernels that have broken exception handling |
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258 * support for user space apps that do SSE. |
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259 */ |
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260 static void check_os_katmai_support( void ) |
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261 { |
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262 #if defined(__FreeBSD__) |
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263 int has_sse=0, ret; |
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264 size_t len=sizeof(has_sse); |
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265 |
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266 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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267 if (ret || !has_sse) |
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268 gCpuCaps.hasSSE=0; |
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269 |
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270 #elif defined(__linux__) |
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271 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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272 struct sigaction saved_sigill; |
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273 struct sigaction saved_sigfpe; |
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274 |
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275 /* Save the original signal handlers. |
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276 */ |
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277 sigaction( SIGILL, NULL, &saved_sigill ); |
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278 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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279 |
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280 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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281 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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282 |
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283 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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284 * supports the extended FPU save and restore required for SSE. If |
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285 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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286 * doesn't support Streaming SIMD Exceptions, even if the processor |
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287 * does. |
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288 */ |
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289 if ( gCpuCaps.hasSSE ) { |
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290 printf( "Testing OS support for SSE... " ); |
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291 |
2272 | 292 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
293 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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294 |
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295 if ( gCpuCaps.hasSSE ) { |
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296 printf( "yes.\n" ); |
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297 } else { |
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298 printf( "no!\n" ); |
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299 } |
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300 } |
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301 |
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302 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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303 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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304 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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305 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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306 * as expected, we're okay but we need to clean up after it. |
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307 * |
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308 * Are we being too stringent in our requirement that the OS support |
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309 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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310 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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311 * doesn't even support them. We at least know the user-space SSE |
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312 * support is good in kernels that do support unmasked exceptions, |
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313 * and therefore to be safe I'm going to leave this test in here. |
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314 */ |
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315 if ( gCpuCaps.hasSSE ) { |
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316 printf( "Testing OS support for SSE unmasked exceptions... " ); |
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317 |
2272 | 318 // test_os_katmai_exception_support(); |
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319 |
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320 if ( gCpuCaps.hasSSE ) { |
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321 printf( "yes.\n" ); |
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322 } else { |
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323 printf( "no!\n" ); |
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324 } |
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325 } |
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326 |
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327 /* Restore the original signal handlers. |
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328 */ |
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329 sigaction( SIGILL, &saved_sigill, NULL ); |
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330 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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331 |
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332 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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333 * safe to go ahead and hook out the SSE code throughout Mesa. |
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334 */ |
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335 if ( gCpuCaps.hasSSE ) { |
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336 printf( "Tests of OS support for SSE passed.\n" ); |
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337 } else { |
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338 printf( "Tests of OS support for SSE failed!\n" ); |
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339 } |
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340 #else |
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341 /* We can't use POSIX signal handling to test the availability of |
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342 * SSE, so we disable it by default. |
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343 */ |
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344 printf( "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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345 gCpuCaps.hasSSE=0; |
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346 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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347 #else |
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348 /* Do nothing on other platforms for now. |
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349 */ |
3850 | 350 printf( "Not testing OS support for SSE, leaving disabled.\n" ); |
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351 gCpuCaps.hasSSE=0; |
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352 #endif /* __linux__ */ |
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353 } |
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354 #else /* ARCH_X86 */ |
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355 |
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356 void GetCpuCaps( CpuCaps *caps) |
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357 { |
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358 caps->cpuType=0; |
3403 | 359 caps->cpuStepping=0; |
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360 caps->hasMMX=0; |
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361 caps->hasMMX2=0; |
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
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diff
changeset
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362 caps->has3DNow=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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363 caps->has3DNowExt=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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364 caps->hasSSE=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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365 caps->hasSSE2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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366 caps->isX86=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
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changeset
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367 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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368 #endif /* !ARCH_X86 */ |