annotate ppc/dsputil_ppc.c @ 8621:72e109759617 libavcodec

Alpha: add ff_ prefix to idct functions
author mru
date Sun, 18 Jan 2009 05:52:17 +0000
parents 68e959302527
children 13b6cdf7895e
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /*
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2 * Copyright (c) 2002 Brian Foley
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3 * Copyright (c) 2002 Dieter Shirley
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org>
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5 *
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6 * This file is part of FFmpeg.
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7 *
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8 * FFmpeg is free software; you can redistribute it and/or
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ace3ccd18dd2 Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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9 * modify it under the terms of the GNU Lesser General Public
ace3ccd18dd2 Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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10 * License as published by the Free Software Foundation; either
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11 * version 2.1 of the License, or (at your option) any later version.
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12 *
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13 * FFmpeg is distributed in the hope that it will be useful,
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
ace3ccd18dd2 Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
ace3ccd18dd2 Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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16 * Lesser General Public License for more details.
ace3ccd18dd2 Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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17 *
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18 * You should have received a copy of the GNU Lesser General Public
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c8c591fe26f8 Change license headers to say 'FFmpeg' instead of 'this program/this library'
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19 * License along with FFmpeg; if not, write to the Free Software
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20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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21 */
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22
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23 #include "libavcodec/dsputil.h"
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24
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25 #include "dsputil_ppc.h"
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26
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27 #if HAVE_ALTIVEC
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28 #include "dsputil_altivec.h"
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29
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30 void fdct_altivec(int16_t *block);
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31 void gmc1_altivec(uint8_t *dst, uint8_t *src, int stride, int h,
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32 int x16, int y16, int rounder);
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33 void idct_put_altivec(uint8_t *dest, int line_size, int16_t *block);
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34 void idct_add_altivec(uint8_t *dest, int line_size, int16_t *block);
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35
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36 void dsputil_h264_init_ppc(DSPContext* c, AVCodecContext *avctx);
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37
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38 void dsputil_init_altivec(DSPContext* c, AVCodecContext *avctx);
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39 void vc1dsp_init_altivec(DSPContext* c, AVCodecContext *avctx);
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40 void snow_init_altivec(DSPContext* c, AVCodecContext *avctx);
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41 void float_init_altivec(DSPContext* c, AVCodecContext *avctx);
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42 void int_init_altivec(DSPContext* c, AVCodecContext *avctx);
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43
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44 #endif
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45
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46 int mm_flags = 0;
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47
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48 int mm_support(void)
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49 {
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50 int result = 0;
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51 #if HAVE_ALTIVEC
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52 if (has_altivec()) {
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53 result |= FF_MM_ALTIVEC;
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54 }
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55 #endif /* result */
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56 return result;
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57 }
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58
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59 #if CONFIG_POWERPC_PERF
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60 unsigned long long perfdata[POWERPC_NUM_PMC_ENABLED][powerpc_perf_total][powerpc_data_total];
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61 /* list below must match enum in dsputil_ppc.h */
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62 static unsigned char* perfname[] = {
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63 "ff_fft_calc_altivec",
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64 "gmc1_altivec",
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65 "dct_unquantize_h263_altivec",
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66 "fdct_altivec",
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67 "idct_add_altivec",
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68 "idct_put_altivec",
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69 "put_pixels16_altivec",
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70 "avg_pixels16_altivec",
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71 "avg_pixels8_altivec",
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72 "put_pixels8_xy2_altivec",
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73 "put_no_rnd_pixels8_xy2_altivec",
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74 "put_pixels16_xy2_altivec",
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75 "put_no_rnd_pixels16_xy2_altivec",
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76 "hadamard8_diff8x8_altivec",
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77 "hadamard8_diff16_altivec",
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78 "avg_pixels8_xy2_altivec",
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79 "clear_blocks_dcbz32_ppc",
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80 "clear_blocks_dcbz128_ppc",
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81 "put_h264_chroma_mc8_altivec",
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82 "avg_h264_chroma_mc8_altivec",
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83 "put_h264_qpel16_h_lowpass_altivec",
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84 "avg_h264_qpel16_h_lowpass_altivec",
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85 "put_h264_qpel16_v_lowpass_altivec",
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86 "avg_h264_qpel16_v_lowpass_altivec",
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87 "put_h264_qpel16_hv_lowpass_altivec",
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88 "avg_h264_qpel16_hv_lowpass_altivec",
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89 ""
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90 };
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91 #include <stdio.h>
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92 #endif
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93
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94 #if CONFIG_POWERPC_PERF
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95 void powerpc_display_perf_report(void)
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96 {
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97 int i, j;
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98 av_log(NULL, AV_LOG_INFO, "PowerPC performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n");
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99 for(i = 0 ; i < powerpc_perf_total ; i++) {
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100 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) {
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101 if (perfdata[j][i][powerpc_data_num] != (unsigned long long)0)
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102 av_log(NULL, AV_LOG_INFO,
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103 " Function \"%s\" (pmc%d):\n\tmin: %"PRIu64"\n\tmax: %"PRIu64"\n\tavg: %1.2lf (%"PRIu64")\n",
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104 perfname[i],
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105 j+1,
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106 perfdata[j][i][powerpc_data_min],
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107 perfdata[j][i][powerpc_data_max],
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108 (double)perfdata[j][i][powerpc_data_sum] /
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109 (double)perfdata[j][i][powerpc_data_num],
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110 perfdata[j][i][powerpc_data_num]);
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111 }
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112 }
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113 }
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114 #endif /* CONFIG_POWERPC_PERF */
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115
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116 /* ***** WARNING ***** WARNING ***** WARNING ***** */
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117 /*
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118 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a
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119 cache line size not equal to 32 bytes.
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120 Fortunately all processor used by Apple up to at least the 7450 (aka second
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121 generation G4) use 32 bytes cache line.
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122 This is due to the use of the 'dcbz' instruction. It simply clear to zero a
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123 single cache line, so you need to know the cache line size to use it !
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124 It's absurd, but it's fast...
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125
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126 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line
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127 size: 128 bytes. Oups.
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128 The semantic of dcbz was changed, it always clear 32 bytes. so the function
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129 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl,
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130 which is defined to clear a cache line (as dcbz before). So we still can
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131 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required.
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132
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133 see <http://developer.apple.com/technotes/tn/tn2087.html>
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134 and <http://developer.apple.com/technotes/tn/tn2086.html>
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135 */
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136 void clear_blocks_dcbz32_ppc(DCTELEM *blocks)
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137 {
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138 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz32, 1);
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139 register int misal = ((unsigned long)blocks & 0x00000010);
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140 register int i = 0;
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141 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz32, 1);
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142 #if 1
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143 if (misal) {
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144 ((unsigned long*)blocks)[0] = 0L;
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145 ((unsigned long*)blocks)[1] = 0L;
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146 ((unsigned long*)blocks)[2] = 0L;
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147 ((unsigned long*)blocks)[3] = 0L;
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148 i += 16;
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149 }
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150 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) {
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151 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory");
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152 }
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153 if (misal) {
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154 ((unsigned long*)blocks)[188] = 0L;
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155 ((unsigned long*)blocks)[189] = 0L;
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156 ((unsigned long*)blocks)[190] = 0L;
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157 ((unsigned long*)blocks)[191] = 0L;
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158 i += 16;
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159 }
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160 #else
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161 memset(blocks, 0, sizeof(DCTELEM)*6*64);
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162 #endif
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163 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1);
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164 }
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165
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166 /* same as above, when dcbzl clear a whole 128B cache line
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167 i.e. the PPC970 aka G5 */
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168 #if HAVE_DCBZL
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169 void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
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170 {
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171 POWERPC_PERF_DECLARE(powerpc_clear_blocks_dcbz128, 1);
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172 register int misal = ((unsigned long)blocks & 0x0000007f);
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173 register int i = 0;
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174 POWERPC_PERF_START_COUNT(powerpc_clear_blocks_dcbz128, 1);
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175 #if 1
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176 if (misal) {
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177 // we could probably also optimize this case,
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178 // but there's not much point as the machines
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179 // aren't available yet (2003-06-26)
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180 memset(blocks, 0, sizeof(DCTELEM)*6*64);
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181 }
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182 else
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183 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) {
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184 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory");
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185 }
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186 #else
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187 memset(blocks, 0, sizeof(DCTELEM)*6*64);
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188 #endif
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189 POWERPC_PERF_STOP_COUNT(powerpc_clear_blocks_dcbz128, 1);
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190 }
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191 #else
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192 void clear_blocks_dcbz128_ppc(DCTELEM *blocks)
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193 {
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194 memset(blocks, 0, sizeof(DCTELEM)*6*64);
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195 }
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196 #endif
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197
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198 #if HAVE_DCBZL
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199 /* check dcbz report how many bytes are set to 0 by dcbz */
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200 /* update 24/06/2003 : replace dcbz by dcbzl to get
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201 the intended effect (Apple "fixed" dcbz)
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202 unfortunately this cannot be used unless the assembler
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203 knows about dcbzl ... */
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204 long check_dcbzl_effect(void)
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205 {
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206 register char *fakedata = av_malloc(1024);
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207 register char *fakedata_middle;
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208 register long zero = 0;
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209 register long i = 0;
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210 long count = 0;
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211
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212 if (!fakedata) {
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213 return 0L;
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214 }
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215
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216 fakedata_middle = (fakedata + 512);
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217
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218 memset(fakedata, 0xFF, 1024);
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219
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220 /* below the constraint "b" seems to mean "Address base register"
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221 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */
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222 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero));
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223
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224 for (i = 0; i < 1024 ; i ++) {
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225 if (fakedata[i] == (char)0)
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226 count++;
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227 }
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228
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229 av_free(fakedata);
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ef2149182f1c COSMETICS: Remove all trailing whitespace.
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230
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231 return count;
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232 }
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233 #else
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234 long check_dcbzl_effect(void)
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235 {
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236 return 0;
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237 }
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238 #endif
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239
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240 static void prefetch_ppc(void *mem, int stride, int h)
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241 {
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242 register const uint8_t *p = mem;
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243 do {
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244 __asm__ volatile ("dcbt 0,%0" : : "r" (p));
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245 p+= stride;
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246 } while(--h);
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247 }
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248
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249 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx)
638
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250 {
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251 // Common optimizations whether AltiVec is available or not
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252 c->prefetch = prefetch_ppc;
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253 switch (check_dcbzl_effect()) {
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254 case 32:
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255 c->clear_blocks = clear_blocks_dcbz32_ppc;
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256 break;
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257 case 128:
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diff changeset
258 c->clear_blocks = clear_blocks_dcbz128_ppc;
5f97ba9a4eaa Almost cosmetic changes in dsputil_init_ppc and vorbis_inverse_coupling_altivec:
lu_zero
parents: 3542
diff changeset
259 break;
5f97ba9a4eaa Almost cosmetic changes in dsputil_init_ppc and vorbis_inverse_coupling_altivec:
lu_zero
parents: 3542
diff changeset
260 default:
5f97ba9a4eaa Almost cosmetic changes in dsputil_init_ppc and vorbis_inverse_coupling_altivec:
lu_zero
parents: 3542
diff changeset
261 break;
5f97ba9a4eaa Almost cosmetic changes in dsputil_init_ppc and vorbis_inverse_coupling_altivec:
lu_zero
parents: 3542
diff changeset
262 }
2236
b0102ea621dd h264 qpel mc, size 16 patch by (Romain Dolbeau <dolbeau at caps-entreprise dot com>)
michael
parents: 2068
diff changeset
263
8590
7a463923ecd1 Change semantic of CONFIG_*, HAVE_* and ARCH_*.
aurel
parents: 8250
diff changeset
264 #if HAVE_ALTIVEC
8596
68e959302527 replace all occurrence of ENABLE_ by the corresponding CONFIG_, HAVE_ or ARCH_
aurel
parents: 8590
diff changeset
265 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx);
2967
ef2149182f1c COSMETICS: Remove all trailing whitespace.
diego
parents: 2778
diff changeset
266
638
0012f75c92bb altivec build tidyup patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
michaelni
parents:
diff changeset
267 if (has_altivec()) {
8104
0d108ec85620 Remove duplicated MM_* macros for CPU capabilities from dsputil.h.
rathann
parents: 8031
diff changeset
268 mm_flags |= FF_MM_ALTIVEC;
2967
ef2149182f1c COSMETICS: Remove all trailing whitespace.
diego
parents: 2778
diff changeset
269
3547
e542c9978077 standalone snow dsputil init
lu_zero
parents: 3546
diff changeset
270 dsputil_init_altivec(c, avctx);
8596
68e959302527 replace all occurrence of ENABLE_ by the corresponding CONFIG_, HAVE_ or ARCH_
aurel
parents: 8590
diff changeset
271 if(CONFIG_SNOW_DECODER) snow_init_altivec(c, avctx);
68e959302527 replace all occurrence of ENABLE_ by the corresponding CONFIG_, HAVE_ or ARCH_
aurel
parents: 8590
diff changeset
272 if(CONFIG_VC1_DECODER || CONFIG_WMV3_DECODER)
4227
ef1d382309e5 Conditionally compile some of the AltiVec optimizations.
diego
parents: 4197
diff changeset
273 vc1dsp_init_altivec(c, avctx);
3581
49082584828a altivec float optimizations
lu_zero
parents: 3547
diff changeset
274 float_init_altivec(c, avctx);
4838
eeac11145c4e ssd_int8_vs_int16_altivec, not completely benchmarkedwith svq1
lu_zero
parents: 4521
diff changeset
275 int_init_altivec(c, avctx);
2979
bfabfdf9ce55 COSMETICS: tabs --> spaces, some prettyprinting
diego
parents: 2967
diff changeset
276 c->gmc1 = gmc1_altivec;
1092
f59c3f66363b MpegEncContext.(i)dct_* -> DspContext.(i)dct_*
michaelni
parents: 1033
diff changeset
277
8590
7a463923ecd1 Change semantic of CONFIG_*, HAVE_* and ARCH_*.
aurel
parents: 8250
diff changeset
278 #if CONFIG_ENCODERS
2979
bfabfdf9ce55 COSMETICS: tabs --> spaces, some prettyprinting
diego
parents: 2967
diff changeset
279 if (avctx->dct_algo == FF_DCT_AUTO ||
7333
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
280 avctx->dct_algo == FF_DCT_ALTIVEC) {
2979
bfabfdf9ce55 COSMETICS: tabs --> spaces, some prettyprinting
diego
parents: 2967
diff changeset
281 c->fdct = fdct_altivec;
bfabfdf9ce55 COSMETICS: tabs --> spaces, some prettyprinting
diego
parents: 2967
diff changeset
282 }
1578
6a4cfc5f9f96 AltiVec optimized fdct patch by (James Klicman <james at klicman dot org>)
michael
parents: 1511
diff changeset
283 #endif //CONFIG_ENCODERS
6a4cfc5f9f96 AltiVec optimized fdct patch by (James Klicman <james at klicman dot org>)
michael
parents: 1511
diff changeset
284
7333
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
285 if (avctx->lowres==0) {
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
286 if ((avctx->idct_algo == FF_IDCT_AUTO) ||
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
287 (avctx->idct_algo == FF_IDCT_ALTIVEC)) {
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
288 c->idct_put = idct_put_altivec;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
289 c->idct_add = idct_add_altivec;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
290 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
291 }
3546
5f97ba9a4eaa Almost cosmetic changes in dsputil_init_ppc and vorbis_inverse_coupling_altivec:
lu_zero
parents: 3542
diff changeset
292 }
2967
ef2149182f1c COSMETICS: Remove all trailing whitespace.
diego
parents: 2778
diff changeset
293
8590
7a463923ecd1 Change semantic of CONFIG_*, HAVE_* and ARCH_*.
aurel
parents: 8250
diff changeset
294 #if CONFIG_POWERPC_PERF
1009
3b7cc8e4b83f AltiVec perf (take 2), plus a couple AltiVec functions by (Romain Dolbeau <dolbeau at irisa dot fr>)
michaelni
parents: 995
diff changeset
295 {
7333
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
296 int i, j;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
297 for (i = 0 ; i < powerpc_perf_total ; i++) {
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
298 for (j = 0; j < POWERPC_NUM_PMC_ENABLED ; j++) {
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
299 perfdata[j][i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFFULL;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
300 perfdata[j][i][powerpc_data_max] = 0x0000000000000000ULL;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
301 perfdata[j][i][powerpc_data_sum] = 0x0000000000000000ULL;
a8a79f5385f6 cosmetics: Reformat PPC code in libavcodec according to style guidelines.
diego
parents: 6763
diff changeset
302 perfdata[j][i][powerpc_data_num] = 0x0000000000000000ULL;
7334
3a93377e8b76 cosmetics: Reindent two misplaced braces.
diego
parents: 7333
diff changeset
303 }
3a93377e8b76 cosmetics: Reindent two misplaced braces.
diego
parents: 7333
diff changeset
304 }
1009
3b7cc8e4b83f AltiVec perf (take 2), plus a couple AltiVec functions by (Romain Dolbeau <dolbeau at irisa dot fr>)
michaelni
parents: 995
diff changeset
305 }
4521
891590781d9e rename POWERPC_PERFORMANCE_REPORT to CONFIG_POWERPC_PERF
mru
parents: 4227
diff changeset
306 #endif /* CONFIG_POWERPC_PERF */
3957
b6f6bf155661 Non Altivec optimizations already present at the top
lu_zero
parents: 3949
diff changeset
307 }
1024
9cc1031e1864 More AltiVec MC functions patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
michaelni
parents: 1015
diff changeset
308 #endif /* HAVE_ALTIVEC */
638
0012f75c92bb altivec build tidyup patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
michaelni
parents:
diff changeset
309 }