Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 12456:a5ddb39627fd libavcodec
Rename FF_MM_ symbols related to CPU features flags as AV_CPU_FLAG_
symbols, and move them from libavcodec/avcodec.h to libavutil/cpu.h.
author | stefano |
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date | Sat, 04 Sep 2010 09:59:08 +0000 |
parents | 3fc4c625b6f3 |
children | 06abedae2906 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * Copyright (c) 2003-2004 Romain Dolbeau <romain@dolbeau.org> |
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5 * |
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6 * This file is part of FFmpeg. |
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7 * |
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8 * FFmpeg is free software; you can redistribute it and/or |
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9 * modify it under the terms of the GNU Lesser General Public |
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10 * License as published by the Free Software Foundation; either |
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11 * version 2.1 of the License, or (at your option) any later version. |
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12 * |
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13 * FFmpeg is distributed in the hope that it will be useful, |
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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16 * Lesser General Public License for more details. |
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17 * |
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18 * You should have received a copy of the GNU Lesser General Public |
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19 * License along with FFmpeg; if not, write to the Free Software |
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20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA |
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21 */ |
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22 |
6763 | 23 #include "libavcodec/dsputil.h" |
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24 #include "dsputil_altivec.h" |
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25 |
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26 int mm_support(void) |
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27 { |
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28 int result = 0; |
8590 | 29 #if HAVE_ALTIVEC |
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30 if (has_altivec()) { |
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31 result |= AV_CPU_FLAG_ALTIVEC; |
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32 } |
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33 #endif /* result */ |
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34 return result; |
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35 } |
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36 |
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37 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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38 /* |
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39 clear_blocks_dcbz32_ppc will not work properly on PowerPC processors with a |
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40 cache line size not equal to 32 bytes. |
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41 Fortunately all processor used by Apple up to at least the 7450 (aka second |
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42 generation G4) use 32 bytes cache line. |
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43 This is due to the use of the 'dcbz' instruction. It simply clear to zero a |
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44 single cache line, so you need to know the cache line size to use it ! |
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45 It's absurd, but it's fast... |
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46 |
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47 update 24/06/2003 : Apple released yesterday the G5, with a PPC970. cache line |
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48 size: 128 bytes. Oups. |
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49 The semantic of dcbz was changed, it always clear 32 bytes. so the function |
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50 below will work, but will be slow. So I fixed check_dcbz_effect to use dcbzl, |
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51 which is defined to clear a cache line (as dcbz before). So we still can |
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52 distinguish, and use dcbz (32 bytes) or dcbzl (one cache line) as required. |
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53 |
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54 see <http://developer.apple.com/technotes/tn/tn2087.html> |
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55 and <http://developer.apple.com/technotes/tn/tn2086.html> |
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56 */ |
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57 static void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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58 { |
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59 register int misal = ((unsigned long)blocks & 0x00000010); |
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60 register int i = 0; |
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61 #if 1 |
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62 if (misal) { |
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63 ((unsigned long*)blocks)[0] = 0L; |
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64 ((unsigned long*)blocks)[1] = 0L; |
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65 ((unsigned long*)blocks)[2] = 0L; |
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66 ((unsigned long*)blocks)[3] = 0L; |
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67 i += 16; |
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68 } |
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69 for ( ; i < sizeof(DCTELEM)*6*64-31 ; i += 32) { |
8031 | 70 __asm__ volatile("dcbz %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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71 } |
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72 if (misal) { |
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73 ((unsigned long*)blocks)[188] = 0L; |
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74 ((unsigned long*)blocks)[189] = 0L; |
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75 ((unsigned long*)blocks)[190] = 0L; |
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76 ((unsigned long*)blocks)[191] = 0L; |
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77 i += 16; |
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78 } |
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79 #else |
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80 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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81 #endif |
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82 } |
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83 |
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84 /* same as above, when dcbzl clear a whole 128B cache line |
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85 i.e. the PPC970 aka G5 */ |
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87 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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88 { |
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89 register int misal = ((unsigned long)blocks & 0x0000007f); |
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90 register int i = 0; |
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91 #if 1 |
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92 if (misal) { |
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93 // we could probably also optimize this case, |
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94 // but there's not much point as the machines |
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95 // aren't available yet (2003-06-26) |
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96 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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97 } |
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98 else |
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99 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 128) { |
8031 | 100 __asm__ volatile("dcbzl %0,%1" : : "b" (blocks), "r" (i) : "memory"); |
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101 } |
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102 #else |
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103 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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104 #endif |
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105 } |
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106 #else |
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107 static void clear_blocks_dcbz128_ppc(DCTELEM *blocks) |
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108 { |
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109 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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110 } |
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111 #endif |
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112 |
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114 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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115 /* update 24/06/2003 : replace dcbz by dcbzl to get |
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116 the intended effect (Apple "fixed" dcbz) |
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117 unfortunately this cannot be used unless the assembler |
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118 knows about dcbzl ... */ |
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119 static long check_dcbzl_effect(void) |
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120 { |
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121 register char *fakedata = av_malloc(1024); |
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122 register char *fakedata_middle; |
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123 register long zero = 0; |
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124 register long i = 0; |
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125 long count = 0; |
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126 |
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127 if (!fakedata) { |
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128 return 0L; |
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129 } |
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130 |
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131 fakedata_middle = (fakedata + 512); |
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132 |
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133 memset(fakedata, 0xFF, 1024); |
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134 |
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135 /* below the constraint "b" seems to mean "Address base register" |
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136 in gcc-3.3 / RS/6000 speaks. seems to avoid using r0, so.... */ |
8031 | 137 __asm__ volatile("dcbzl %0, %1" : : "b" (fakedata_middle), "r" (zero)); |
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138 |
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139 for (i = 0; i < 1024 ; i ++) { |
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140 if (fakedata[i] == (char)0) |
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141 count++; |
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142 } |
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143 |
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144 av_free(fakedata); |
2967 | 145 |
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146 return count; |
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147 } |
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148 #else |
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149 static long check_dcbzl_effect(void) |
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150 { |
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151 return 0; |
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152 } |
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153 #endif |
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154 |
4003 | 155 static void prefetch_ppc(void *mem, int stride, int h) |
156 { | |
157 register const uint8_t *p = mem; | |
158 do { | |
8031 | 159 __asm__ volatile ("dcbt 0,%0" : : "r" (p)); |
4003 | 160 p+= stride; |
161 } while(--h); | |
162 } | |
163 | |
1092 | 164 void dsputil_init_ppc(DSPContext* c, AVCodecContext *avctx) |
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165 { |
5749 | 166 // Common optimizations whether AltiVec is available or not |
4003 | 167 c->prefetch = prefetch_ppc; |
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168 switch (check_dcbzl_effect()) { |
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169 case 32: |
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170 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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171 break; |
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172 case 128: |
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173 c->clear_blocks = clear_blocks_dcbz128_ppc; |
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174 break; |
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175 default: |
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176 break; |
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177 } |
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178 |
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180 if(CONFIG_H264_DECODER) dsputil_h264_init_ppc(c, avctx); |
2967 | 181 |
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182 if (has_altivec()) { |
3547 | 183 dsputil_init_altivec(c, avctx); |
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184 if(CONFIG_VC1_DECODER) |
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185 vc1dsp_init_altivec(c, avctx); |
3581 | 186 float_init_altivec(c, avctx); |
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187 int_init_altivec(c, avctx); |
2979 | 188 c->gmc1 = gmc1_altivec; |
1092 | 189 |
8590 | 190 #if CONFIG_ENCODERS |
2979 | 191 if (avctx->dct_algo == FF_DCT_AUTO || |
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192 avctx->dct_algo == FF_DCT_ALTIVEC) { |
2979 | 193 c->fdct = fdct_altivec; |
194 } | |
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195 #endif //CONFIG_ENCODERS |
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196 |
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197 if (avctx->lowres==0) { |
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198 if ((avctx->idct_algo == FF_IDCT_AUTO) || |
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199 (avctx->idct_algo == FF_IDCT_ALTIVEC)) { |
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200 c->idct_put = idct_put_altivec; |
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201 c->idct_add = idct_add_altivec; |
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202 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; |
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203 }else if((CONFIG_VP3_DECODER || CONFIG_VP5_DECODER || CONFIG_VP6_DECODER) && |
9711 | 204 avctx->idct_algo==FF_IDCT_VP3){ |
205 c->idct_put = ff_vp3_idct_put_altivec; | |
206 c->idct_add = ff_vp3_idct_add_altivec; | |
207 c->idct = ff_vp3_idct_altivec; | |
208 c->idct_permutation_type = FF_TRANSPOSE_IDCT_PERM; | |
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209 } |
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210 } |
2967 | 211 |
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212 } |
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213 #endif /* HAVE_ALTIVEC */ |
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214 } |