Mercurial > mplayer.hg
annotate vidix/drivers/nvidia_vid.c @ 20757:2f71acee3657
- explain lavc lmin option more clearly
- document lavc mblmin and mblmax options
author | corey |
---|---|
date | Wed, 08 Nov 2006 03:23:02 +0000 |
parents | 59d10ceb72c8 |
children | 1767c271d710 |
rev | line source |
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10954 | 1 /* |
2 nvidia_vid - VIDIX based video driver for NVIDIA chips | |
11902 | 3 Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from |
10954 | 4 RIVATV (rivatv.sf.net) |
5 Licence: GPL | |
11159 | 6 WARNING: THIS DRIVER IS IN BETA STAGE |
10954 | 7 |
11086 | 8 multi buffer support and TNT2 fixes by Dmitry Baryshkov |
10954 | 9 */ |
10 | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16380 | 16 #include <math.h> |
10954 | 17 #include <inttypes.h> |
18 #include <unistd.h> | |
19 | |
20 | |
21 #include "../vidix.h" | |
22 #include "../fourcc.h" | |
23 #include "../../libdha/libdha.h" | |
24 #include "../../libdha/pci_ids.h" | |
25 #include "../../libdha/pci_names.h" | |
26 #include "../../config.h" | |
27 #include "../../bswap.h" | |
28 | |
29 | |
30 pciinfo_t pci_info; | |
31 | |
32 | |
33 #define MAX_FRAMES 3 | |
34 #define NV04_BES_SIZE 1024*2000*4 | |
35 | |
36 | |
37 static vidix_capability_t nvidia_cap = { | |
38 "NVIDIA RIVA OVERLAY DRIVER", | |
39 "Sascha Sommer <saschasommer@freenet.de>", | |
40 TYPE_OUTPUT, | |
41 { 0, 0, 0, 0 }, | |
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42 2046, |
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43 2046, |
10954 | 44 4, |
45 4, | |
46 -1, | |
47 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
48 VENDOR_NVIDIA2, | |
49 -1, | |
50 { 0, 0, 0, 0 } | |
51 }; | |
52 | |
53 | |
54 unsigned int vixGetVersion(void){ | |
55 return(VIDIX_VERSION); | |
56 } | |
57 | |
58 | |
59 #define NV_ARCH_03 0x03 | |
60 #define NV_ARCH_04 0x04 | |
61 #define NV_ARCH_10 0x10 | |
62 #define NV_ARCH_20 0x20 | |
63 #define NV_ARCH_30 0x30 | |
64 | |
16380 | 65 // since no useful information whatsoever is passed |
66 // to the equalizer functions we need this | |
67 static struct { | |
68 uint32_t lum; // luminance (brightness + contrast) | |
69 uint32_t chrom; // chrominance (saturation + hue) | |
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70 uint8_t red_off; // for NV03/NV04 |
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71 uint8_t green_off; |
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72 uint8_t blue_off; |
16380 | 73 vidix_video_eq_t vals; |
74 } eq; | |
75 | |
10954 | 76 struct nvidia_cards { |
77 unsigned short chip_id; | |
78 unsigned short arch; | |
79 }; | |
80 | |
81 | |
82 static struct nvidia_cards nvidia_card_ids[] = { | |
11073 | 83 /*NV03*/ |
10954 | 84 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, |
11073 | 85 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, |
86 /*NV04*/ | |
87 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
88 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, | |
89 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
90 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
91 {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04}, | |
92 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, | |
10954 | 93 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, |
11073 | 94 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, |
95 {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04}, | |
96 {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04}, | |
10954 | 97 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, |
11073 | 98 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, |
99 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
10954 | 100 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, |
101 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
11073 | 102 /*NV10*/ |
103 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, | |
104 {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10}, | |
105 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, | |
106 {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10}, | |
107 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, | |
108 {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10}, | |
109 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10}, | |
110 {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10}, | |
111 {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10}, | |
112 {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10}, | |
113 {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10}, | |
114 {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10}, | |
115 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, | |
116 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, | |
117 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, | |
118 {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, | |
119 {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10}, | |
120 {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10}, | |
121 /*NV20*/ | |
122 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
123 {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20}, | |
124 {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20}, | |
125 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20}, | |
126 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20}, | |
127 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20}, | |
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128 {DEVICE_NVIDIA_QUADRO4_900XGL,NV_ARCH_20}, |
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129 {DEVICE_NVIDIA_QUADRO4_750XGL,NV_ARCH_20}, |
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130 {DEVICE_NVIDIA_QUADRO4_700XGL,NV_ARCH_20}, |
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131 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, |
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132 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, |
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133 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, |
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134 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, |
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135 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, |
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136 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, |
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137 /*NV30*/ |
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138 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, |
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139 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, |
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140 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, |
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141 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, |
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142 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, |
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143 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, |
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144 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, |
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145 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, |
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146 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, |
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147 {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, |
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148 {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, |
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149 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, |
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150 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, |
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151 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, |
16376 | 152 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, |
153 {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, | |
10954 | 154 }; |
155 | |
156 | |
157 static int find_chip(unsigned chip_id){ | |
158 unsigned i; | |
159 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
160 { | |
161 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
162 } | |
163 return -1; | |
164 } | |
165 | |
166 int vixProbe(int verbose, int force){ | |
167 pciinfo_t lst[MAX_PCI_DEVICES]; | |
168 unsigned i,num_pci; | |
169 int err; | |
170 | |
171 if (force) | |
172 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
173 err = pci_scan(lst,&num_pci); | |
174 if(err){ | |
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175 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); |
10954 | 176 return err; |
177 } | |
178 else { | |
179 err = ENXIO; | |
180 for(i=0; i < num_pci; i++){ | |
181 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
182 int idx; | |
183 const char *dname; | |
184 idx = find_chip(lst[i].device); | |
185 if(idx == -1) | |
186 continue; | |
187 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
188 dname = dname ? dname : "Unknown chip"; | |
189 printf("[nvidia_vid] Found chip: %s\n", dname); | |
190 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
191 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
192 continue; | |
193 } | |
194 nvidia_cap.device_id = lst[i].device; | |
195 err = 0; | |
196 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
197 break; | |
198 } | |
199 } | |
200 } | |
201 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
202 return err; | |
203 } | |
204 | |
205 | |
206 | |
207 | |
208 /* | |
209 * PCI-Memory IO access macros. | |
210 */ | |
211 | |
212 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
213 | |
214 #undef VID_WR08 | |
215 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
216 #undef VID_RD08 | |
217 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
218 | |
219 #undef VID_WR32 | |
18318 | 220 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) |
10954 | 221 #undef VID_RD32 |
18318 | 222 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) |
10954 | 223 |
224 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
225 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
226 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
227 | |
228 | |
229 | |
230 | |
231 | |
232 | |
233 struct rivatv_chip { | |
234 volatile uint32_t *PMC; /* general control */ | |
235 volatile uint32_t *PME; /* multimedia port */ | |
236 volatile uint32_t *PFB; /* framebuffer control */ | |
237 volatile uint32_t *PVIDEO; /* overlay control */ | |
238 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
239 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
240 volatile uint32_t *PRAMIN; /* instance memory */ | |
241 volatile uint32_t *PRAMHT; /* hash table */ | |
242 volatile uint32_t *PRAMFC; /* fifo context table */ | |
243 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
244 volatile uint32_t *PFIFO; /* fifo control region */ | |
245 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
246 volatile uint32_t *PGRAPH; /* graphics engine */ | |
247 | |
248 unsigned long fbsize; /* framebuffer size */ | |
249 int arch; /* compatible NV_ARCH_XX define */ | |
250 int realarch; /* real architecture */ | |
251 void (* lock) (struct rivatv_chip *, int); | |
252 }; | |
253 typedef struct rivatv_chip rivatv_chip; | |
254 | |
255 | |
11086 | 256 struct rivatv_info { |
257 unsigned int use_colorkey; | |
10954 | 258 unsigned int colorkey; /* saved xv colorkey*/ |
259 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
260 unsigned int depth; | |
261 unsigned int format; | |
262 unsigned int pitch; | |
263 unsigned int width,height; | |
264 unsigned int d_width,d_height; /*scaled width && height*/ | |
265 unsigned int wx,wy; /*window x && y*/ | |
266 unsigned int screen_x; /*screen width*/ | |
11085 | 267 unsigned int screen_y; /*screen height*/ |
10954 | 268 unsigned long buffer_size; /* size of the image buffer */ |
269 struct rivatv_chip chip; /* NV architecture structure */ | |
270 void* video_base; /* virtual address of control region */ | |
271 void* control_base; /* virtual address of fb region */ | |
16378 | 272 void* picture_base; /* direct pointer to video picture */ |
10954 | 273 unsigned long picture_offset; /* offset of video picture in frame buffer */ |
274 // struct rivatv_dma dma; /* DMA structure */ | |
11783 | 275 unsigned int cur_frame; |
10954 | 276 unsigned int num_frames; /* number of buffers */ |
11783 | 277 int bps; /* bytes per line */ |
10954 | 278 }; |
279 typedef struct rivatv_info rivatv_info; | |
280 | |
281 //framebuffer size funcs | |
282 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
283 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
284 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
285 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
286 /* SDRAM 128 ZX. */ | |
287 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
288 } | |
289 else { | |
290 return 1024 * 1024 * 8; | |
291 } | |
292 } | |
293 else { | |
294 /* SGRAM 128. */ | |
16371 | 295 switch (VID_RD32(chip->PFB, 0) & 0x00000003) { |
10954 | 296 case 0: |
297 return 1024 * 1024 * 8; | |
298 break; | |
299 case 2: | |
300 return 1024 * 1024 * 4; | |
301 break; | |
302 default: | |
303 return 1024 * 1024 * 2; | |
304 break; | |
305 } | |
306 } | |
307 } | |
308 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
309 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
310 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
311 + 1024 * 1024 * 2; | |
312 } else { | |
313 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
314 case 0: | |
315 return 1024 * 1024 * 32; | |
316 break; | |
317 case 1: | |
318 return 1024 * 1024 * 4; | |
319 break; | |
320 case 2: | |
321 return 1024 * 1024 * 8; | |
322 break; | |
323 case 3: | |
324 default: | |
325 return 1024 * 1024 * 16; | |
326 break; | |
327 } | |
328 } | |
329 } | |
330 | |
331 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
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332 return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; |
10954 | 333 } |
334 | |
335 //lock funcs | |
336 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
337 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
338 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
339 } | |
340 | |
341 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
342 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
343 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
344 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
345 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
346 } | |
347 | |
348 | |
349 | |
350 | |
351 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
352 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
353 uint32_t reg; | |
354 | |
355 /* switch off interrupts once for a while */ | |
356 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
357 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
358 | |
359 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
360 | |
361 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
362 | |
363 if ((reg & 0x10100010) != 0x10100010) { | |
364 printf("PVIDEO and PFB disabled, enabling...\n"); | |
365 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
366 } | |
367 | |
368 /* save the current colorkey */ | |
369 switch (info->chip.arch ) { | |
370 case NV_ARCH_10: | |
371 case NV_ARCH_20: | |
372 case NV_ARCH_30: | |
373 /* NV_PVIDEO_COLOR_KEY */ | |
374 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
375 break; | |
376 case NV_ARCH_03: | |
377 case NV_ARCH_04: | |
378 /* NV_PVIDEO_KEY */ | |
379 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
380 break; | |
381 } | |
382 | |
383 | |
384 /* re-enable interrupts again */ | |
385 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
386 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
387 } | |
388 | |
389 /* Stop overlay video. */ | |
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390 static void rivatv_overlay_stop (struct rivatv_info *info) { |
10954 | 391 switch (info->chip.arch ) { |
392 case NV_ARCH_10: | |
393 case NV_ARCH_20: | |
394 case NV_ARCH_30: | |
395 /* NV_PVIDEO_COLOR_KEY */ | |
396 /* Xv-Extension-Hack: Restore previously saved value. */ | |
397 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
398 /* NV_PVIDEO_STOP */ | |
399 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
400 /* NV_PVIDEO_BUFFER */ | |
401 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
402 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
11086 | 403 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); |
10954 | 404 break; |
405 case NV_ARCH_03: | |
406 case NV_ARCH_04: | |
407 /* NV_PVIDEO_KEY */ | |
408 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
409 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
410 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
411 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
11086 | 412 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); |
10954 | 413 /* NV_PVIDEO_OE_STATE */ |
414 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
415 /* NV_PVIDEO_SU_STATE */ | |
416 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
417 /* NV_PVIDEO_RM_STATE */ | |
418 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
419 break; | |
420 } | |
421 } | |
422 | |
423 /* Get pan offset of the physical screen. */ | |
424 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
425 uint32_t pan; | |
426 info->chip.lock (&info->chip, 0); | |
427 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
428 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
429 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
430 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
431 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
432 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
433 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
434 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
435 return pan << 2; | |
436 } | |
437 | |
438 /* Compute and set colorkey depending on the colour depth. */ | |
439 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
440 uint32_t r, g, b, key = 0; | |
11159 | 441 |
10954 | 442 r = (chromakey & 0x00FF0000) >> 16; |
443 g = (chromakey & 0x0000FF00) >> 8; | |
444 b = chromakey & 0x000000FF; | |
445 switch (info->depth) { | |
446 case 15: | |
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447 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); |
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448 #ifndef WIN32 |
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449 key = key | 0x00008000; |
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450 #endif |
10954 | 451 break; |
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452 case 16: // XXX unchecked |
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453 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); |
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454 #ifndef WIN32 |
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455 key = key | 0x00008000; |
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456 #endif |
10954 | 457 break; |
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458 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? |
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459 key = (chromakey & 0x00FFFFFF) | 0x00800000; |
10954 | 460 break; |
461 case 32: | |
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462 key = chromakey; |
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463 #ifndef WIN32 |
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464 key = key | 0x80000000; |
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465 #endif |
10954 | 466 break; |
467 } | |
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468 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); |
10954 | 469 switch (info->chip.arch) { |
470 case NV_ARCH_10: | |
471 case NV_ARCH_20: | |
472 case NV_ARCH_30: | |
473 VID_WR32 (info->chip.PVIDEO, 0xB00, key); | |
474 break; | |
475 case NV_ARCH_03: | |
476 case NV_ARCH_04: | |
477 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
478 break; | |
479 } | |
480 } | |
481 | |
11085 | 482 static void nv_getscreenproperties(struct rivatv_info *info){ |
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483 uint32_t bpp=0,x; |
11085 | 484 info->chip.lock(&info->chip, 0); |
485 /*get screen depth*/ | |
486 VID_WR08(info->chip.PCIO, 0x03D4,0x28); | |
11783 | 487 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; |
16371 | 488 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; |
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489 else info->depth = 0x04 << bpp; |
11085 | 490 /*get screen width*/ |
491 VID_WR08(info->chip.PCIO, 0x03D4, 0x1); | |
492 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; | |
493 /*get screen height*/ | |
494 /* get first 8 bits in VT_DISPLAY_END*/ | |
495 VID_WR08(info->chip.PCIO, 0x03D4, 0x12); | |
496 info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); | |
497 VID_WR08(info->chip.PCIO,0x03D4,0x07); | |
498 /* get 9th bit in CRTC_OVERFLOW*/ | |
499 info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; | |
500 /* and the 10th in CRTC_OVERFLOW*/ | |
501 info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; | |
502 ++info->screen_y; | |
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503 |
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504 /* NV_PCRTC_OFFSET */ |
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505 VID_WR08 (info->chip.PCIO, 0x3D4, 0x13); |
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506 x = VID_RD08 (info->chip.PCIO, 0x3D5); |
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507 /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ |
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508 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); |
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509 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3; |
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510 /* NV_PCRTC_EXTRA_OFFSET_11 */ |
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511 VID_WR08 (info->chip.PCIO, 0x3D4, 0x25); |
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512 x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3; |
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513 info->bps = x * bpp; |
11085 | 514 } |
515 | |
516 | |
517 | |
10954 | 518 |
519 /* Start overlay video. */ | |
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520 static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ |
11085 | 521 uint32_t base, size, offset, xscale, yscale, pan; |
11086 | 522 uint32_t value; |
16367 | 523 int x=info->wx, y=info->wy; |
10954 | 524 int lwidth=info->d_width, lheight=info->d_height; |
525 | |
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526 size = info->buffer_size; |
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527 base = info->picture_offset; |
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528 offset = bufno*size; |
10954 | 529 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ |
11085 | 530 nv_getscreenproperties(info); |
531 | |
532 if(info->depth){ | |
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533 /* get pan offset of the physical screen */ |
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534 pan = rivatv_overlay_pan (info); |
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535 /* adjust window position depending on the pan offset */ |
16370 | 536 if (info->bps != 0) |
11783 | 537 { |
16370 | 538 x = info->wx - (pan % info->bps) * 8 / info->depth; |
539 y = info->wy - (pan / info->bps); | |
11783 | 540 } |
16367 | 541 } else { |
542 // we can't adjust the window position correctly in textmode | |
543 // setting y to 8 seems to work ok, though | |
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544 if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; |
11783 | 545 } |
546 | |
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547 /* adjust negative output window variables */ |
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548 if (x < 0) { |
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549 lwidth = info->d_width + x; |
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550 offset += (-x * info->width / info->d_width) << 1; |
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551 // offset += (-window->x * port->vld_width / window->width) << 1; |
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552 x = 0; |
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553 } |
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554 if (y < 0) { |
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555 lheight = info->d_height + y; |
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556 offset += (-y * info->height / info->d_height * info->width) << 1; |
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557 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; |
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558 y = 0; |
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559 } |
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560 |
10954 | 561 switch (info->chip.arch) { |
562 case NV_ARCH_10: | |
563 case NV_ARCH_20: | |
564 case NV_ARCH_30: | |
565 | |
566 /* NV_PVIDEO_BASE */ | |
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567 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); |
10954 | 568 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); |
569 /* NV_PVIDEO_LIMIT */ | |
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570 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); |
10954 | 571 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); |
572 | |
573 /* extra code for NV20 && NV30 architectures */ | |
574 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { | |
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575 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); |
10954 | 576 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); |
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577 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); |
10954 | 578 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); |
579 } | |
580 | |
581 /* NV_PVIDEO_LUMINANCE */ | |
16380 | 582 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); |
10954 | 583 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); |
584 /* NV_PVIDEO_CHROMINANCE */ | |
16380 | 585 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); |
10954 | 586 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); |
587 | |
588 /* NV_PVIDEO_OFFSET */ | |
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589 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); |
10954 | 590 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); |
591 /* NV_PVIDEO_SIZE_IN */ | |
592 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
593 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
594 /* NV_PVIDEO_POINT_IN */ | |
595 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
596 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
597 /* NV_PVIDEO_DS_DX_RATIO */ | |
598 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
599 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
600 /* NV_PVIDEO_DT_DY_RATIO */ | |
601 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
602 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
603 | |
604 /* NV_PVIDEO_POINT_OUT */ | |
605 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
606 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
607 /* NV_PVIDEO_SIZE_OUT */ | |
608 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
609 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
610 | |
611 /* NV_PVIDEO_FORMAT */ | |
11086 | 612 value = info->pitch; |
613 if(info->use_colorkey)value |= 1 << 20; | |
614 if(info->format == IMGFMT_YUY2)value |= 1 << 16; | |
615 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); | |
616 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
10954 | 617 |
618 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
11086 | 619 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); |
10954 | 620 /* NV_PVIDEO_STOP */ |
11086 | 621 VID_WR32 (info->chip.PVIDEO, 0x704,0x0); |
10954 | 622 /* NV_PVIDEO_BUFFER */ |
11086 | 623 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); |
10954 | 624 break; |
625 | |
626 case NV_ARCH_03: | |
627 case NV_ARCH_04: | |
628 | |
629 | |
630 /* NV_PVIDEO_OE_STATE */ | |
631 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
632 /* NV_PVIDEO_SU_STATE */ | |
633 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
634 /* NV_PVIDEO_RM_STATE */ | |
635 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
636 | |
637 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
638 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
639 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
640 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
641 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
642 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
643 | |
644 /* NV_PVIDEO_WINDOW_START */ | |
645 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
646 /* NV_PVIDEO_WINDOW_SIZE */ | |
647 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
648 /* NV_PVIDEO_STEP_SIZE */ | |
649 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
650 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
651 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
652 | |
653 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
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654 VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); |
10954 | 655 /* NV_PVIDEO_GREEN_CSC_OFFSET */ |
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656 VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); |
10954 | 657 /* NV_PVIDEO_BLUE_CSC_OFFSET */ |
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658 VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); |
10954 | 659 /* NV_PVIDEO_CSC_ADJUST */ |
660 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
661 | |
662 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
663 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
664 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
11086 | 665 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ |
10954 | 666 |
667 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
668 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
669 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
670 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
671 | |
672 /* NV_PVIDEO_BUFF0_OFFSET */ | |
673 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
674 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
675 | |
676 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
677 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
11086 | 678 |
10954 | 679 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ |
11086 | 680 value = 0x1; /*video on*/ |
681 if(info->format==IMGFMT_YUY2)value |= 0x100; | |
682 if(info->use_colorkey)value |=0x10; | |
683 VID_WR32 (info->chip.PVIDEO, 0x244, value); | |
684 | |
10954 | 685 /* NV_PVIDEO_SU_STATE */ |
686 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
687 break; | |
688 } | |
689 /*set colorkey*/ | |
690 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
691 | |
692 } | |
693 | |
694 | |
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695 |
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696 |
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697 |
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698 |
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699 |
10954 | 700 static rivatv_info* info; |
701 | |
702 | |
703 | |
704 | |
705 int vixInit(void){ | |
706 int mtrr; | |
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707 info = calloc(1,sizeof(rivatv_info)); |
10954 | 708 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); |
709 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
16378 | 710 printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); |
10954 | 711 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); |
712 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
713 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
714 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
715 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
716 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
717 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
718 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
719 /* setup chip specific functions */ | |
720 switch (info->chip.arch) { | |
721 case NV_ARCH_03: | |
722 info->chip.lock = rivatv_lock_nv03; | |
723 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
724 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
725 break; | |
726 case NV_ARCH_04: | |
727 info->chip.lock = rivatv_lock_nv04; | |
728 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
729 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
730 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
731 break; | |
732 case NV_ARCH_10: | |
733 case NV_ARCH_20: | |
734 case NV_ARCH_30: | |
735 info->chip.lock = rivatv_lock_nv04; | |
736 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
737 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
738 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
739 break; | |
740 } | |
741 switch (info->chip.arch) { | |
742 case NV_ARCH_03: | |
743 { | |
744 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
745 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
746 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
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747 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); |
16378 | 748 info->picture_base = info->video_base + info->picture_offset; |
10954 | 749 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); |
750 break; | |
751 } | |
752 case NV_ARCH_04: | |
753 case NV_ARCH_10: | |
754 case NV_ARCH_20: | |
755 case NV_ARCH_30: | |
756 { | |
757 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
758 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
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759 if(info->chip.fbsize > 16*1024*1024) |
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760 info->picture_offset -= NV04_BES_SIZE; |
10954 | 761 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); |
16378 | 762 info->picture_base = info->video_base + info->picture_offset; |
10954 | 763 break; |
764 } | |
765 } | |
766 | |
767 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
768 | |
769 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
11085 | 770 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); |
10954 | 771 else |
11085 | 772 printf("[nvidia_vid] MTRR set up\n"); |
10954 | 773 |
11085 | 774 nv_getscreenproperties(info); |
775 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); | |
776 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); | |
777 | |
10954 | 778 |
779 rivatv_enable_PMEDIA(info); | |
11783 | 780 info->cur_frame = 0; |
11159 | 781 info->use_colorkey = 0; |
11783 | 782 |
16380 | 783 eq.lum = 0x00001000; |
784 eq.chrom = 0x00001000; | |
785 memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); | |
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786 eq.vals.cap = VEQ_CAP_BRIGHTNESS; |
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787 if (info->chip.arch > NV_ARCH_04) |
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788 eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; |
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789 eq.red_off = 0x69; |
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790 eq.green_off = 0x3e; |
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791 eq.blue_off = 0x89; |
10954 | 792 return 0; |
793 } | |
794 | |
795 void vixDestroy(void){ | |
796 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); | |
797 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
798 free(info); | |
799 } | |
800 | |
801 int vixGetCapability(vidix_capability_t *to){ | |
802 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); | |
803 return 0; | |
804 } | |
805 | |
806 inline static int is_supported_fourcc(uint32_t fourcc) | |
807 { | |
11086 | 808 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) |
10954 | 809 return 1; |
810 else | |
811 return 0; | |
812 } | |
813 | |
814 int vixQueryFourcc(vidix_fourcc_t *to){ | |
815 if(is_supported_fourcc(to->fourcc)){ | |
816 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
817 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
818 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
819 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
820 VID_DEPTH_32BPP; | |
821 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
822 return 0; | |
823 } | |
824 else to->depth = to->flags = 0; | |
825 return ENOSYS; | |
826 } | |
827 | |
828 int vixConfigPlayback(vidix_playback_t *vinfo){ | |
829 uint32_t i; | |
830 printf("called %s\n", __FUNCTION__); | |
831 if (! is_supported_fourcc(vinfo->fourcc)) | |
832 return ENOSYS; | |
833 | |
834 info->width = vinfo->src.w; | |
835 info->height = vinfo->src.h; | |
836 | |
837 info->d_width = vinfo->dest.w; | |
838 info->d_height = vinfo->dest.h; | |
839 info->wx = vinfo->dest.x; | |
840 info->wy = vinfo->dest.y; | |
841 info->format = vinfo->fourcc; | |
842 | |
843 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
844 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
845 | |
846 | |
16378 | 847 vinfo->dga_addr=info->picture_base; |
10954 | 848 |
849 switch (vinfo->fourcc) | |
850 { | |
851 case IMGFMT_YUY2: | |
852 case IMGFMT_UYVY: | |
853 | |
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854 vinfo->dest.pitch.y = 64; |
10954 | 855 vinfo->dest.pitch.u = 0; |
856 vinfo->dest.pitch.v = 0; | |
857 | |
858 vinfo->offset.y = 0; | |
859 vinfo->offset.v = 0; | |
860 vinfo->offset.u = 0; | |
11902 | 861 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); |
10954 | 862 vinfo->frame_size = info->pitch * info->height; |
863 break; | |
864 } | |
865 info->buffer_size = vinfo->frame_size; | |
866 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
867 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
868 // vinfo->num_frames = 1; | |
869 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
870 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
871 return 0; | |
872 } | |
873 | |
874 int vixPlaybackOn(void){ | |
11783 | 875 rivatv_overlay_start(info,info->cur_frame); |
10954 | 876 return 0; |
877 } | |
878 | |
879 int vixPlaybackOff(void){ | |
880 rivatv_overlay_stop(info); | |
881 return 0; | |
882 } | |
883 | |
884 int vixSetGrKeys( const vidix_grkey_t * grkey){ | |
11159 | 885 if (grkey->ckey.op == CKEY_FALSE) |
886 { | |
887 info->use_colorkey = 0; | |
888 printf("[nvidia_vid] colorkeying disabled\n"); | |
889 } | |
11165 | 890 else { |
11159 | 891 info->use_colorkey = 1; |
10954 | 892 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); |
893 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
11165 | 894 } |
11210 | 895 if(info->d_width && info->d_height)rivatv_overlay_start(info,0); |
10954 | 896 return 0; |
897 } | |
898 | |
899 int vixPlaybackFrameSelect(unsigned int frame){ | |
900 // printf("selecting buffer %d\n", frame); | |
901 rivatv_overlay_start(info, frame); | |
902 if (info->num_frames >= 1) | |
11783 | 903 info->cur_frame = frame/*(frame+1)%info->num_frames*/; |
10954 | 904 return 0; |
905 } | |
16380 | 906 |
907 int vixPlaybackSetEq(const vidix_video_eq_t *eq_parm) { | |
908 double angle; | |
909 int16_t chrom_cos, chrom_sin; | |
910 if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) | |
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911 eq.vals.brightness = eq_parm->brightness; |
16380 | 912 if (eq_parm->cap & VEQ_CAP_CONTRAST) |
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913 eq.vals.contrast = eq_parm->contrast; |
16380 | 914 if (eq_parm->cap & VEQ_CAP_SATURATION) |
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915 eq.vals.saturation = eq_parm->saturation; |
16380 | 916 if (eq_parm->cap & VEQ_CAP_HUE) |
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917 eq.vals.hue = eq_parm->hue; |
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918 eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | |
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919 ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); |
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920 angle = (double)eq.vals.hue / 1000.0 * 3.1415927; |
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921 chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; |
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922 chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; |
16380 | 923 eq.chrom = chrom_sin << 16 | chrom_cos; |
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924 eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; |
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925 eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; |
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926 eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; |
16380 | 927 return 0; |
928 } | |
929 | |
930 int vixPlaybackGetEq(vidix_video_eq_t *eq_parm) { | |
931 memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); | |
932 return 0; | |
933 } | |
934 |