Mercurial > mplayer.hg
annotate vidix/drivers/nvidia_vid.c @ 16370:b2e4d3f3c0af
simplification
author | faust3 |
---|---|
date | Sat, 03 Sep 2005 10:06:08 +0000 |
parents | 8e859a01904f |
children | f3e6984c415c |
rev | line source |
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10954 | 1 /* |
2 nvidia_vid - VIDIX based video driver for NVIDIA chips | |
11902 | 3 Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from |
10954 | 4 RIVATV (rivatv.sf.net) |
5 Licence: GPL | |
11159 | 6 WARNING: THIS DRIVER IS IN BETA STAGE |
10954 | 7 |
11086 | 8 multi buffer support and TNT2 fixes by Dmitry Baryshkov |
10954 | 9 */ |
10 | |
11 | |
12 #include <errno.h> | |
13 #include <stdio.h> | |
14 #include <stdlib.h> | |
15 #include <string.h> | |
16 #include <inttypes.h> | |
17 #include <unistd.h> | |
18 | |
19 | |
20 #include "../vidix.h" | |
21 #include "../fourcc.h" | |
22 #include "../../libdha/libdha.h" | |
23 #include "../../libdha/pci_ids.h" | |
24 #include "../../libdha/pci_names.h" | |
25 #include "../../config.h" | |
26 #include "../../bswap.h" | |
27 | |
28 | |
29 pciinfo_t pci_info; | |
30 | |
31 | |
32 #define MAX_FRAMES 3 | |
33 #define NV04_BES_SIZE 1024*2000*4 | |
34 | |
35 | |
36 static vidix_capability_t nvidia_cap = { | |
37 "NVIDIA RIVA OVERLAY DRIVER", | |
38 "Sascha Sommer <saschasommer@freenet.de>", | |
39 TYPE_OUTPUT, | |
40 { 0, 0, 0, 0 }, | |
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41 2046, |
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42 2046, |
10954 | 43 4, |
44 4, | |
45 -1, | |
46 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
47 VENDOR_NVIDIA2, | |
48 -1, | |
49 { 0, 0, 0, 0 } | |
50 }; | |
51 | |
52 | |
53 unsigned int vixGetVersion(void){ | |
54 return(VIDIX_VERSION); | |
55 } | |
56 | |
57 | |
58 #define NV_ARCH_03 0x03 | |
59 #define NV_ARCH_04 0x04 | |
60 #define NV_ARCH_10 0x10 | |
61 #define NV_ARCH_20 0x20 | |
62 #define NV_ARCH_30 0x30 | |
63 | |
64 struct nvidia_cards { | |
65 unsigned short chip_id; | |
66 unsigned short arch; | |
67 }; | |
68 | |
69 | |
70 static struct nvidia_cards nvidia_card_ids[] = { | |
11073 | 71 /*NV03*/ |
10954 | 72 {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, |
11073 | 73 {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, |
74 /*NV04*/ | |
75 {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, | |
76 {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, | |
77 {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, | |
78 {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, | |
79 {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04}, | |
80 {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, | |
10954 | 81 {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, |
11073 | 82 {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, |
83 {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04}, | |
84 {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04}, | |
10954 | 85 {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, |
11073 | 86 {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, |
87 {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, | |
10954 | 88 {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, |
89 {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, | |
11073 | 90 /*NV10*/ |
91 {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, | |
92 {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10}, | |
93 {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, | |
94 {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10}, | |
95 {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, | |
96 {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10}, | |
97 {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10}, | |
98 {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10}, | |
99 {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10}, | |
100 {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10}, | |
101 {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10}, | |
102 {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10}, | |
103 {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, | |
104 {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, | |
105 {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, | |
106 {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, | |
107 {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10}, | |
108 {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10}, | |
109 /*NV20*/ | |
110 {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, | |
111 {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20}, | |
112 {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20}, | |
113 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20}, | |
114 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20}, | |
115 {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20}, | |
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116 {DEVICE_NVIDIA_QUADRO4_900XGL,NV_ARCH_20}, |
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117 {DEVICE_NVIDIA_QUADRO4_750XGL,NV_ARCH_20}, |
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118 {DEVICE_NVIDIA_QUADRO4_700XGL,NV_ARCH_20}, |
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119 {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, |
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120 {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, |
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121 {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, |
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122 {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, |
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123 {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, |
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124 {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, |
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125 /*NV30*/ |
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126 {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, |
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127 {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, |
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128 {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, |
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129 {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, |
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130 {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, |
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131 {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, |
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132 {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, |
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133 {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, |
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134 {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, |
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135 {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, |
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136 {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, |
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137 {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, |
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138 {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30} |
10954 | 139 }; |
140 | |
141 | |
142 static int find_chip(unsigned chip_id){ | |
143 unsigned i; | |
144 for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) | |
145 { | |
146 if(chip_id == nvidia_card_ids[i].chip_id)return i; | |
147 } | |
148 return -1; | |
149 } | |
150 | |
151 int vixProbe(int verbose, int force){ | |
152 pciinfo_t lst[MAX_PCI_DEVICES]; | |
153 unsigned i,num_pci; | |
154 int err; | |
155 | |
156 if (force) | |
157 printf("[nvidia_vid]: warning: forcing not supported yet!\n"); | |
158 err = pci_scan(lst,&num_pci); | |
159 if(err){ | |
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160 printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); |
10954 | 161 return err; |
162 } | |
163 else { | |
164 err = ENXIO; | |
165 for(i=0; i < num_pci; i++){ | |
166 if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ | |
167 int idx; | |
168 const char *dname; | |
169 idx = find_chip(lst[i].device); | |
170 if(idx == -1) | |
171 continue; | |
172 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
173 dname = dname ? dname : "Unknown chip"; | |
174 printf("[nvidia_vid] Found chip: %s\n", dname); | |
175 if ((lst[i].command & PCI_COMMAND_IO) == 0){ | |
176 printf("[nvidia_vid] Device is disabled, ignoring\n"); | |
177 continue; | |
178 } | |
179 nvidia_cap.device_id = lst[i].device; | |
180 err = 0; | |
181 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
182 break; | |
183 } | |
184 } | |
185 } | |
186 if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); | |
187 return err; | |
188 } | |
189 | |
190 | |
191 | |
192 | |
193 /* | |
194 * PCI-Memory IO access macros. | |
195 */ | |
196 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
197 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
198 | |
199 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
200 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
201 | |
202 #ifndef USE_RMW_CYCLES | |
203 /* | |
204 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
205 */ | |
206 | |
207 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
208 | |
209 #undef VID_WR08 | |
210 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
211 #undef VID_RD08 | |
212 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
213 | |
214 #undef VID_WR32 | |
215 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
216 #undef VID_RD32 | |
217 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
218 #endif /* USE_RMW_CYCLES */ | |
219 | |
220 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
221 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
222 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
223 | |
224 | |
225 | |
226 | |
227 | |
228 | |
229 struct rivatv_chip { | |
230 volatile uint32_t *PMC; /* general control */ | |
231 volatile uint32_t *PME; /* multimedia port */ | |
232 volatile uint32_t *PFB; /* framebuffer control */ | |
233 volatile uint32_t *PVIDEO; /* overlay control */ | |
234 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
235 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
236 volatile uint32_t *PRAMIN; /* instance memory */ | |
237 volatile uint32_t *PRAMHT; /* hash table */ | |
238 volatile uint32_t *PRAMFC; /* fifo context table */ | |
239 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
240 volatile uint32_t *PFIFO; /* fifo control region */ | |
241 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
242 volatile uint32_t *PGRAPH; /* graphics engine */ | |
243 | |
244 unsigned long fbsize; /* framebuffer size */ | |
245 int arch; /* compatible NV_ARCH_XX define */ | |
246 int realarch; /* real architecture */ | |
247 void (* lock) (struct rivatv_chip *, int); | |
248 }; | |
249 typedef struct rivatv_chip rivatv_chip; | |
250 | |
251 | |
11086 | 252 struct rivatv_info { |
253 unsigned int use_colorkey; | |
10954 | 254 unsigned int colorkey; /* saved xv colorkey*/ |
255 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
256 unsigned int depth; | |
257 unsigned int format; | |
258 unsigned int pitch; | |
259 unsigned int width,height; | |
260 unsigned int d_width,d_height; /*scaled width && height*/ | |
261 unsigned int wx,wy; /*window x && y*/ | |
262 unsigned int screen_x; /*screen width*/ | |
11085 | 263 unsigned int screen_y; /*screen height*/ |
10954 | 264 unsigned long buffer_size; /* size of the image buffer */ |
265 struct rivatv_chip chip; /* NV architecture structure */ | |
266 void* video_base; /* virtual address of control region */ | |
267 void* control_base; /* virtual address of fb region */ | |
268 unsigned long picture_base; /* direct pointer to video picture */ | |
269 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
270 // struct rivatv_dma dma; /* DMA structure */ | |
11783 | 271 unsigned int cur_frame; |
10954 | 272 unsigned int num_frames; /* number of buffers */ |
11783 | 273 int bps; /* bytes per line */ |
10954 | 274 }; |
275 typedef struct rivatv_info rivatv_info; | |
276 | |
277 //framebuffer size funcs | |
278 static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ | |
279 if (VID_RD32 (chip->PFB, 0) & 0x00000020) { | |
280 if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) | |
281 && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { | |
282 /* SDRAM 128 ZX. */ | |
283 return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); | |
284 } | |
285 else { | |
286 return 1024 * 1024 * 8; | |
287 } | |
288 } | |
289 else { | |
290 /* SGRAM 128. */ | |
291 switch (chip->PFB[0x00000000] & 0x00000003) { | |
292 case 0: | |
293 return 1024 * 1024 * 8; | |
294 break; | |
295 case 2: | |
296 return 1024 * 1024 * 4; | |
297 break; | |
298 default: | |
299 return 1024 * 1024 * 2; | |
300 break; | |
301 } | |
302 } | |
303 } | |
304 static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ | |
305 if (VID_RD32 (chip->PFB, 0) & 0x00000100) { | |
306 return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 | |
307 + 1024 * 1024 * 2; | |
308 } else { | |
309 switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { | |
310 case 0: | |
311 return 1024 * 1024 * 32; | |
312 break; | |
313 case 1: | |
314 return 1024 * 1024 * 4; | |
315 break; | |
316 case 2: | |
317 return 1024 * 1024 * 8; | |
318 break; | |
319 case 3: | |
320 default: | |
321 return 1024 * 1024 * 16; | |
322 break; | |
323 } | |
324 } | |
325 } | |
326 | |
327 static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ | |
328 return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 1024; | |
329 } | |
330 | |
331 //lock funcs | |
332 static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ | |
333 VID_WR08 (chip->PVIO, 0x3C4, 0x06); | |
334 VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
335 } | |
336 | |
337 static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ | |
338 VID_WR08 (chip->PCIO, 0x3C4, 0x06); | |
339 VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); | |
340 VID_WR08 (chip->PCIO, 0x3D4, 0x1F); | |
341 VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); | |
342 } | |
343 | |
344 | |
345 | |
346 | |
347 /* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ | |
348 static void rivatv_enable_PMEDIA (struct rivatv_info *info){ | |
349 uint32_t reg; | |
350 | |
351 /* switch off interrupts once for a while */ | |
352 // VID_WR32 (info->chip.PME, 0x200140, 0x00); | |
353 // VID_WR32 (info->chip.PMC, 0x000140, 0x00); | |
354 | |
355 reg = VID_RD32 (info->chip.PMC, 0x000200); | |
356 | |
357 /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ | |
358 | |
359 if ((reg & 0x10100010) != 0x10100010) { | |
360 printf("PVIDEO and PFB disabled, enabling...\n"); | |
361 VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); | |
362 } | |
363 | |
364 /* save the current colorkey */ | |
365 switch (info->chip.arch ) { | |
366 case NV_ARCH_10: | |
367 case NV_ARCH_20: | |
368 case NV_ARCH_30: | |
369 /* NV_PVIDEO_COLOR_KEY */ | |
370 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); | |
371 break; | |
372 case NV_ARCH_03: | |
373 case NV_ARCH_04: | |
374 /* NV_PVIDEO_KEY */ | |
375 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); | |
376 break; | |
377 } | |
378 | |
379 | |
380 /* re-enable interrupts again */ | |
381 // VID_WR32 (info->chip.PMC, 0x000140, 0x01); | |
382 // VID_WR32 (info->chip.PME, 0x200140, 0x01); | |
383 } | |
384 | |
385 /* Stop overlay video. */ | |
386 void rivatv_overlay_stop (struct rivatv_info *info) { | |
387 switch (info->chip.arch ) { | |
388 case NV_ARCH_10: | |
389 case NV_ARCH_20: | |
390 case NV_ARCH_30: | |
391 /* NV_PVIDEO_COLOR_KEY */ | |
392 /* Xv-Extension-Hack: Restore previously saved value. */ | |
393 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); | |
394 /* NV_PVIDEO_STOP */ | |
395 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); | |
396 /* NV_PVIDEO_BUFFER */ | |
397 VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); | |
398 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
11086 | 399 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); |
10954 | 400 break; |
401 case NV_ARCH_03: | |
402 case NV_ARCH_04: | |
403 /* NV_PVIDEO_KEY */ | |
404 VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); | |
405 /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ | |
406 VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); | |
407 /* NV_PVIDEO_INTR_EN_0_NOTIFY */ | |
11086 | 408 // VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); |
10954 | 409 /* NV_PVIDEO_OE_STATE */ |
410 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
411 /* NV_PVIDEO_SU_STATE */ | |
412 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
413 /* NV_PVIDEO_RM_STATE */ | |
414 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
415 break; | |
416 } | |
417 } | |
418 | |
419 /* Get pan offset of the physical screen. */ | |
420 static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ | |
421 uint32_t pan; | |
422 info->chip.lock (&info->chip, 0); | |
423 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); | |
424 pan = VID_RD08 (info->chip.PCIO, 0x3D5); | |
425 VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); | |
426 pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; | |
427 VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); | |
428 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; | |
429 VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); | |
430 pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; | |
431 return pan << 2; | |
432 } | |
433 | |
434 /* Compute and set colorkey depending on the colour depth. */ | |
435 static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ | |
436 uint32_t r, g, b, key = 0; | |
11159 | 437 |
10954 | 438 r = (chromakey & 0x00FF0000) >> 16; |
439 g = (chromakey & 0x0000FF00) >> 8; | |
440 b = chromakey & 0x000000FF; | |
441 switch (info->depth) { | |
442 case 15: | |
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443 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); |
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444 #ifndef WIN32 |
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445 key = key | 0x00008000; |
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446 #endif |
10954 | 447 break; |
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448 case 16: // XXX unchecked |
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449 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); |
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450 #ifndef WIN32 |
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451 key = key | 0x00008000; |
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452 #endif |
10954 | 453 break; |
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454 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? |
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455 key = (chromakey & 0x00FFFFFF) | 0x00800000; |
10954 | 456 break; |
457 case 32: | |
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458 key = chromakey; |
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459 #ifndef WIN32 |
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460 key = key | 0x80000000; |
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461 #endif |
10954 | 462 break; |
463 } | |
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464 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); |
10954 | 465 switch (info->chip.arch) { |
466 case NV_ARCH_10: | |
467 case NV_ARCH_20: | |
468 case NV_ARCH_30: | |
469 VID_WR32 (info->chip.PVIDEO, 0xB00, key); | |
470 break; | |
471 case NV_ARCH_03: | |
472 case NV_ARCH_04: | |
473 VID_WR32 (info->chip.PVIDEO, 0x240, key); | |
474 break; | |
475 } | |
476 } | |
477 | |
11085 | 478 static void nv_getscreenproperties(struct rivatv_info *info){ |
479 uint32_t bpp=0; | |
480 info->chip.lock(&info->chip, 0); | |
481 /*get screen depth*/ | |
482 VID_WR08(info->chip.PCIO, 0x03D4,0x28); | |
11783 | 483 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; |
11085 | 484 if(bpp==3)bpp=4; |
485 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; | |
486 else info->depth = bpp*8; | |
16370 | 487 info->bps=bpp; |
11085 | 488 /*get screen width*/ |
489 VID_WR08(info->chip.PCIO, 0x03D4, 0x1); | |
490 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; | |
491 /*get screen height*/ | |
492 /* get first 8 bits in VT_DISPLAY_END*/ | |
493 VID_WR08(info->chip.PCIO, 0x03D4, 0x12); | |
494 info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); | |
495 VID_WR08(info->chip.PCIO,0x03D4,0x07); | |
496 /* get 9th bit in CRTC_OVERFLOW*/ | |
497 info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; | |
498 /* and the 10th in CRTC_OVERFLOW*/ | |
499 info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; | |
500 ++info->screen_y; | |
501 } | |
502 | |
503 | |
504 | |
10954 | 505 |
506 /* Start overlay video. */ | |
507 void rivatv_overlay_start (struct rivatv_info *info,int bufno){ | |
11085 | 508 uint32_t base, size, offset, xscale, yscale, pan; |
11086 | 509 uint32_t value; |
16367 | 510 int x=info->wx, y=info->wy; |
10954 | 511 int lwidth=info->d_width, lheight=info->d_height; |
11783 | 512 int i; |
10954 | 513 |
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514 size = info->buffer_size; |
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515 base = info->picture_offset; |
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516 offset = bufno*size; |
10954 | 517 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ |
11085 | 518 nv_getscreenproperties(info); |
519 | |
520 if(info->depth){ | |
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521 /* get pan offset of the physical screen */ |
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522 pan = rivatv_overlay_pan (info); |
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523 /* adjust window position depending on the pan offset */ |
16370 | 524 if (info->bps != 0) |
11783 | 525 { |
16370 | 526 x = info->wx - (pan % info->bps) * 8 / info->depth; |
527 y = info->wy - (pan / info->bps); | |
11783 | 528 } |
16367 | 529 } else { |
530 // we can't adjust the window position correctly in textmode | |
531 // setting y to 8 seems to work ok, though | |
532 if(!y)y = info->wy+8; | |
11783 | 533 } |
534 | |
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535 /* adjust negative output window variables */ |
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536 if (x < 0) { |
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537 lwidth = info->d_width + x; |
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538 offset += (-x * info->width / info->d_width) << 1; |
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539 // offset += (-window->x * port->vld_width / window->width) << 1; |
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540 x = 0; |
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541 } |
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542 if (y < 0) { |
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543 lheight = info->d_height + y; |
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544 offset += (-y * info->height / info->d_height * info->width) << 1; |
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545 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; |
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546 y = 0; |
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547 } |
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548 |
10954 | 549 switch (info->chip.arch) { |
550 case NV_ARCH_10: | |
551 case NV_ARCH_20: | |
552 case NV_ARCH_30: | |
553 | |
554 /* NV_PVIDEO_BASE */ | |
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555 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); |
10954 | 556 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); |
557 /* NV_PVIDEO_LIMIT */ | |
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558 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); |
10954 | 559 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); |
560 | |
561 /* extra code for NV20 && NV30 architectures */ | |
562 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { | |
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563 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); |
10954 | 564 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); |
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565 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); |
10954 | 566 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); |
567 } | |
568 | |
569 /* NV_PVIDEO_LUMINANCE */ | |
570 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000); | |
571 //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); | |
572 /* NV_PVIDEO_CHROMINANCE */ | |
573 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000); | |
574 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); | |
575 | |
576 /* NV_PVIDEO_OFFSET */ | |
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577 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); |
10954 | 578 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); |
579 /* NV_PVIDEO_SIZE_IN */ | |
580 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); | |
581 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); | |
582 /* NV_PVIDEO_POINT_IN */ | |
583 VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); | |
584 //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); | |
585 /* NV_PVIDEO_DS_DX_RATIO */ | |
586 VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); | |
587 //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); | |
588 /* NV_PVIDEO_DT_DY_RATIO */ | |
589 VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); | |
590 //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); | |
591 | |
592 /* NV_PVIDEO_POINT_OUT */ | |
593 VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); | |
594 //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); | |
595 /* NV_PVIDEO_SIZE_OUT */ | |
596 VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); | |
597 //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); | |
598 | |
599 /* NV_PVIDEO_FORMAT */ | |
11086 | 600 value = info->pitch; |
601 if(info->use_colorkey)value |= 1 << 20; | |
602 if(info->format == IMGFMT_YUY2)value |= 1 << 16; | |
603 VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); | |
604 //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); | |
10954 | 605 |
606 /* NV_PVIDEO_INTR_EN_BUFFER */ | |
11086 | 607 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); |
10954 | 608 /* NV_PVIDEO_STOP */ |
11086 | 609 VID_WR32 (info->chip.PVIDEO, 0x704,0x0); |
10954 | 610 /* NV_PVIDEO_BUFFER */ |
11086 | 611 VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); |
10954 | 612 break; |
613 | |
614 case NV_ARCH_03: | |
615 case NV_ARCH_04: | |
616 | |
617 | |
618 /* NV_PVIDEO_OE_STATE */ | |
619 VID_WR32 (info->chip.PVIDEO, 0x224, 0); | |
620 /* NV_PVIDEO_SU_STATE */ | |
621 VID_WR32 (info->chip.PVIDEO, 0x228, 0); | |
622 /* NV_PVIDEO_RM_STATE */ | |
623 VID_WR32 (info->chip.PVIDEO, 0x22C, 0); | |
624 | |
625 /* NV_PVIDEO_BUFF0_START_ADDRESS */ | |
626 VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); | |
627 VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); | |
628 /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ | |
629 VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); | |
630 VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); | |
631 | |
632 /* NV_PVIDEO_WINDOW_START */ | |
633 VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); | |
634 /* NV_PVIDEO_WINDOW_SIZE */ | |
635 VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); | |
636 /* NV_PVIDEO_STEP_SIZE */ | |
637 yscale = ((info->height - 1) << 11) / (info->d_height - 1); | |
638 xscale = ((info->width - 1) << 11) / (info->d_width - 1); | |
639 VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); | |
640 | |
641 /* NV_PVIDEO_RED_CSC_OFFSET */ | |
642 VID_WR32 (info->chip.PVIDEO, 0x280, 0x69); | |
643 /* NV_PVIDEO_GREEN_CSC_OFFSET */ | |
644 VID_WR32 (info->chip.PVIDEO, 0x284, 0x3e); | |
645 /* NV_PVIDEO_BLUE_CSC_OFFSET */ | |
646 VID_WR32 (info->chip.PVIDEO, 0x288, 0x89); | |
647 /* NV_PVIDEO_CSC_ADJUST */ | |
648 VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ | |
649 | |
650 /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ | |
651 VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); | |
652 /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ | |
11086 | 653 VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ |
10954 | 654 |
655 /* NV_PVIDEO_FIFO_BURST_LENGTH */ | |
656 VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); | |
657 /* NV_PVIDEO_FIFO_THRES_SIZE */ | |
658 VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ | |
659 | |
660 /* NV_PVIDEO_BUFF0_OFFSET */ | |
661 VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); | |
662 VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); | |
663 | |
664 /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ | |
665 // VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); | |
11086 | 666 |
10954 | 667 /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ |
11086 | 668 value = 0x1; /*video on*/ |
669 if(info->format==IMGFMT_YUY2)value |= 0x100; | |
670 if(info->use_colorkey)value |=0x10; | |
671 VID_WR32 (info->chip.PVIDEO, 0x244, value); | |
672 | |
10954 | 673 /* NV_PVIDEO_SU_STATE */ |
674 VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); | |
675 break; | |
676 } | |
677 /*set colorkey*/ | |
678 rivatv_overlay_colorkey(info,info->vidixcolorkey); | |
679 | |
680 } | |
681 | |
682 | |
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683 |
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684 |
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685 |
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686 |
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687 |
10954 | 688 static rivatv_info* info; |
689 | |
690 | |
691 | |
692 | |
693 int vixInit(void){ | |
694 int mtrr; | |
695 info = (rivatv_info*)calloc(1,sizeof(rivatv_info)); | |
696 info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); | |
697 info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; | |
698 printf("[nvidia_vid] arch %x register base %x\n",info->chip.arch,(unsigned int)info->control_base); | |
699 info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); | |
700 info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); | |
701 info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); | |
702 info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); | |
703 info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); | |
704 info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); | |
705 info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); | |
706 info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); | |
707 /* setup chip specific functions */ | |
708 switch (info->chip.arch) { | |
709 case NV_ARCH_03: | |
710 info->chip.lock = rivatv_lock_nv03; | |
711 info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); | |
712 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
713 break; | |
714 case NV_ARCH_04: | |
715 info->chip.lock = rivatv_lock_nv04; | |
716 info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); | |
717 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
718 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); | |
719 break; | |
720 case NV_ARCH_10: | |
721 case NV_ARCH_20: | |
722 case NV_ARCH_30: | |
723 info->chip.lock = rivatv_lock_nv04; | |
724 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); | |
725 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); | |
726 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); | |
727 break; | |
728 } | |
729 switch (info->chip.arch) { | |
730 case NV_ARCH_03: | |
731 { | |
732 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
733 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
734 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
10977
3da6b1de1c33
make it work in textmode again && support for nv03 with 4MB RAM
faust3
parents:
10970
diff
changeset
|
735 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); |
10954 | 736 info->picture_base = (uint32_t) info->video_base + info->picture_offset; |
737 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); | |
738 break; | |
739 } | |
740 case NV_ARCH_04: | |
741 case NV_ARCH_10: | |
742 case NV_ARCH_20: | |
743 case NV_ARCH_30: | |
744 { | |
745 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
746 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; | |
747 // info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); | |
748 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
749 break; | |
750 } | |
751 } | |
752 | |
753 printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); | |
754 | |
755 if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) | |
11085 | 756 printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); |
10954 | 757 else |
11085 | 758 printf("[nvidia_vid] MTRR set up\n"); |
10954 | 759 |
11085 | 760 nv_getscreenproperties(info); |
761 if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); | |
762 else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); | |
763 | |
10954 | 764 |
765 rivatv_enable_PMEDIA(info); | |
11783 | 766 info->cur_frame = 0; |
11159 | 767 info->use_colorkey = 0; |
11783 | 768 |
10954 | 769 return 0; |
770 } | |
771 | |
772 void vixDestroy(void){ | |
773 unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); | |
774 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
775 free(info); | |
776 } | |
777 | |
778 int vixGetCapability(vidix_capability_t *to){ | |
779 memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); | |
780 return 0; | |
781 } | |
782 | |
783 inline static int is_supported_fourcc(uint32_t fourcc) | |
784 { | |
11086 | 785 if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) |
10954 | 786 return 1; |
787 else | |
788 return 0; | |
789 } | |
790 | |
791 int vixQueryFourcc(vidix_fourcc_t *to){ | |
792 if(is_supported_fourcc(to->fourcc)){ | |
793 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
794 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
795 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
796 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
797 VID_DEPTH_32BPP; | |
798 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
799 return 0; | |
800 } | |
801 else to->depth = to->flags = 0; | |
802 return ENOSYS; | |
803 } | |
804 | |
805 int vixConfigPlayback(vidix_playback_t *vinfo){ | |
806 uint32_t i; | |
807 printf("called %s\n", __FUNCTION__); | |
808 if (! is_supported_fourcc(vinfo->fourcc)) | |
809 return ENOSYS; | |
810 | |
811 info->width = vinfo->src.w; | |
812 info->height = vinfo->src.h; | |
813 | |
814 info->d_width = vinfo->dest.w; | |
815 info->d_height = vinfo->dest.h; | |
816 info->wx = vinfo->dest.x; | |
817 info->wy = vinfo->dest.y; | |
818 info->format = vinfo->fourcc; | |
819 | |
820 printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", | |
821 info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); | |
822 | |
823 | |
824 vinfo->dga_addr=(void*)(info->picture_base); | |
825 | |
826 switch (vinfo->fourcc) | |
827 { | |
828 case IMGFMT_YUY2: | |
829 case IMGFMT_UYVY: | |
830 | |
11086 | 831 vinfo->dest.pitch.y = 16; |
10954 | 832 vinfo->dest.pitch.u = 0; |
833 vinfo->dest.pitch.v = 0; | |
834 | |
835 vinfo->offset.y = 0; | |
836 vinfo->offset.v = 0; | |
837 vinfo->offset.u = 0; | |
11902 | 838 info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); |
10954 | 839 vinfo->frame_size = info->pitch * info->height; |
840 break; | |
841 } | |
842 info->buffer_size = vinfo->frame_size; | |
843 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
844 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
845 // vinfo->num_frames = 1; | |
846 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
847 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
848 return 0; | |
849 } | |
850 | |
851 int vixPlaybackOn(void){ | |
11783 | 852 rivatv_overlay_start(info,info->cur_frame); |
10954 | 853 return 0; |
854 } | |
855 | |
856 int vixPlaybackOff(void){ | |
857 rivatv_overlay_stop(info); | |
858 return 0; | |
859 } | |
860 | |
861 int vixSetGrKeys( const vidix_grkey_t * grkey){ | |
11159 | 862 if (grkey->ckey.op == CKEY_FALSE) |
863 { | |
864 info->use_colorkey = 0; | |
865 printf("[nvidia_vid] colorkeying disabled\n"); | |
866 } | |
11165 | 867 else { |
11159 | 868 info->use_colorkey = 1; |
10954 | 869 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); |
870 printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
11165 | 871 } |
11210 | 872 if(info->d_width && info->d_height)rivatv_overlay_start(info,0); |
10954 | 873 return 0; |
874 } | |
875 | |
876 int vixPlaybackFrameSelect(unsigned int frame){ | |
877 // printf("selecting buffer %d\n", frame); | |
878 rivatv_overlay_start(info, frame); | |
879 if (info->num_frames >= 1) | |
11783 | 880 info->cur_frame = frame/*(frame+1)%info->num_frames*/; |
10954 | 881 return 0; |
882 } |