Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3164:3c5ad8d5ac00
radeon_vid new features:
- tested UYVY format and known as working
- YV12, I420, IYUV direct support
(were missed: p23_blank_lines_at_top, p23_v_accum_init in
radeon_vid_display_video - good info for Y800 support ;)
- experimental support for Rage128/Rage128Pro chips
author | nick |
---|---|
date | Tue, 27 Nov 2001 18:36:02 +0000 |
parents | 60c2510ab0ae |
children | 5eae81895171 |
rev | line source |
---|---|
2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
2870 | 15 */ |
16 | |
3164 | 17 #define RADEON_VID_VERSION "1.0.0" |
2951 | 18 |
2870 | 19 /* |
20 It's entirely possible this major conflicts with something else | |
21 mknod /dev/radeon_vid c 178 0 | |
3164 | 22 or |
23 mknod /dev/rage128_vid c 178 0 | |
24 for Rage128/Rage128Pro chips (althrough it doesn't matter) | |
25 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
26 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
27 ----------------------------------------------------------- | |
2870 | 28 TODO: |
3164 | 29 Highest priority: fbvid.h compatibility |
30 High priority: RGB/BGR 2-32, YVU9, IF09 support | |
3122 | 31 Middle priority: |
32 OV0_COLOUR_CNTL brightness saturation | |
33 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? | |
34 OV0_GRAPHICS_KEY_CLR color key | |
35 OV0_AUTO_FLIP_CNTL | |
36 OV0_FILTER_CNTL | |
37 OV0_VIDEO_KEY_CLR | |
38 OV0_KEY_CNTL | |
3164 | 39 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV |
3122 | 40 YUNV, YVYU, Y41P, Y211, Y41T, Y42T, V422, V655, CLJR |
41 ^^^^ | |
42 YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
2870 | 43 */ |
44 | |
45 #include <linux/config.h> | |
46 #include <linux/version.h> | |
47 #include <linux/module.h> | |
48 #include <linux/types.h> | |
49 #include <linux/kernel.h> | |
50 #include <linux/sched.h> | |
51 #include <linux/mm.h> | |
52 #include <linux/string.h> | |
53 #include <linux/errno.h> | |
54 #include <linux/slab.h> | |
55 #include <linux/pci.h> | |
56 #include <linux/ioport.h> | |
57 #include <linux/init.h> | |
58 | |
59 #include "radeon_vid.h" | |
60 #include "radeon.h" | |
61 | |
62 #ifdef CONFIG_MTRR | |
63 #include <asm/mtrr.h> | |
64 #endif | |
65 | |
66 #include <asm/uaccess.h> | |
67 #include <asm/system.h> | |
68 #include <asm/io.h> | |
69 | |
70 #define TRUE 1 | |
71 #define FALSE 0 | |
72 | |
73 #define RADEON_VID_MAJOR 178 | |
74 | |
75 | |
76 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
3164 | 77 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128/Radeons. Version: "RADEON_VID_VERSION); |
2965 | 78 #ifdef MODULE_LICENSE |
2870 | 79 MODULE_LICENSE("GPL"); |
2965 | 80 #endif |
2870 | 81 |
3164 | 82 #ifdef RAGE128 |
83 #define RVID_MSG "rage128_vid: " | |
84 #define X_ADJUST 0 | |
85 #else | |
86 #define RVID_MSG "radeon_vid: " | |
87 #define X_ADJUST 8 | |
88 #endif | |
89 | |
2870 | 90 typedef struct bes_registers_s |
91 { | |
92 /* base address of yuv framebuffer */ | |
93 uint32_t yuv_base; | |
94 uint32_t fourcc; | |
95 /* YUV BES registers */ | |
96 uint32_t reg_load_cntl; | |
97 uint32_t h_inc; | |
98 uint32_t step_by; | |
99 uint32_t y_x_start; | |
100 uint32_t y_x_end; | |
101 uint32_t v_inc; | |
102 uint32_t p1_blank_lines_at_top; | |
3019 | 103 uint32_t p23_blank_lines_at_top; |
2870 | 104 uint32_t vid_buf_pitch0_value; |
2944 | 105 uint32_t vid_buf_pitch1_value; |
2870 | 106 uint32_t p1_x_start_end; |
107 uint32_t p2_x_start_end; | |
108 uint32_t p3_x_start_end; | |
3122 | 109 uint32_t base_addr; |
2870 | 110 uint32_t vid_buf0_base_adrs; |
111 /* These ones are for auto flip: maybe in the future */ | |
112 uint32_t vid_buf1_base_adrs; | |
113 uint32_t vid_buf2_base_adrs; | |
114 uint32_t vid_buf3_base_adrs; | |
115 uint32_t vid_buf4_base_adrs; | |
116 uint32_t vid_buf5_base_adrs; | |
117 | |
118 uint32_t p1_v_accum_init; | |
119 uint32_t p1_h_accum_init; | |
3019 | 120 uint32_t p23_v_accum_init; |
2870 | 121 uint32_t p23_h_accum_init; |
122 uint32_t scale_cntl; | |
123 uint32_t exclusive_horz; | |
124 uint32_t auto_flip_cntl; | |
125 uint32_t filter_cntl; | |
126 uint32_t colour_cntl; | |
127 uint32_t graphics_key_msk; | |
128 uint32_t graphics_key_clr; | |
129 uint32_t key_cntl; | |
130 uint32_t test; | |
131 } bes_registers_t; | |
132 | |
133 typedef struct video_registers_s | |
134 { | |
135 uint32_t name; | |
136 uint32_t value; | |
137 }video_registers_t; | |
138 | |
139 static bes_registers_t besr; | |
140 static video_registers_t vregs[] = | |
141 { | |
142 { OV0_REG_LOAD_CNTL, 0 }, | |
143 { OV0_H_INC, 0 }, | |
144 { OV0_STEP_BY, 0 }, | |
145 { OV0_Y_X_START, 0 }, | |
146 { OV0_Y_X_END, 0 }, | |
147 { OV0_V_INC, 0 }, | |
148 { OV0_P1_BLANK_LINES_AT_TOP, 0 }, | |
3019 | 149 { OV0_P23_BLANK_LINES_AT_TOP, 0 }, |
2870 | 150 { OV0_VID_BUF_PITCH0_VALUE, 0 }, |
2944 | 151 { OV0_VID_BUF_PITCH1_VALUE, 0 }, |
2870 | 152 { OV0_P1_X_START_END, 0 }, |
153 { OV0_P2_X_START_END, 0 }, | |
154 { OV0_P3_X_START_END, 0 }, | |
3122 | 155 { OV0_BASE_ADDR, 0 }, |
2870 | 156 { OV0_VID_BUF0_BASE_ADRS, 0 }, |
157 { OV0_VID_BUF1_BASE_ADRS, 0 }, | |
158 { OV0_VID_BUF2_BASE_ADRS, 0 }, | |
159 { OV0_VID_BUF3_BASE_ADRS, 0 }, | |
160 { OV0_VID_BUF4_BASE_ADRS, 0 }, | |
161 { OV0_VID_BUF5_BASE_ADRS, 0 }, | |
162 { OV0_P1_V_ACCUM_INIT, 0 }, | |
163 { OV0_P1_H_ACCUM_INIT, 0 }, | |
3019 | 164 { OV0_P23_V_ACCUM_INIT, 0 }, |
2870 | 165 { OV0_P23_H_ACCUM_INIT, 0 }, |
166 { OV0_SCALE_CNTL, 0 }, | |
167 { OV0_EXCLUSIVE_HORZ, 0 }, | |
168 { OV0_AUTO_FLIP_CNTL, 0 }, | |
169 { OV0_FILTER_CNTL, 0 }, | |
170 { OV0_COLOUR_CNTL, 0 }, | |
171 { OV0_GRAPHICS_KEY_MSK, 0 }, | |
172 { OV0_GRAPHICS_KEY_CLR, 0 }, | |
173 { OV0_KEY_CNTL, 0 }, | |
174 { OV0_TEST, 0 } | |
175 }; | |
176 | |
177 static uint32_t radeon_vid_in_use = 0; | |
178 | |
179 static uint8_t *radeon_mmio_base = 0; | |
180 static uint32_t radeon_mem_base = 0; | |
3019 | 181 static int32_t radeon_overlay_off = 0; |
2870 | 182 |
183 static uint32_t radeon_ram_size = 0; | |
184 | |
185 static mga_vid_config_t radeon_config; | |
186 | |
2951 | 187 #undef DEBUG |
2870 | 188 #if DEBUG |
189 #define RTRACE printk | |
190 #else | |
191 #define RTRACE(...) ((void)0) | |
192 #endif | |
193 | |
3122 | 194 static char *fourcc_format_name(int format) |
195 { | |
196 switch(format) | |
197 { | |
198 case IMGFMT_RGB8: return("RGB 8-bit"); | |
199 case IMGFMT_RGB15: return("RGB 15-bit"); | |
200 case IMGFMT_RGB16: return("RGB 16-bit"); | |
201 case IMGFMT_RGB24: return("RGB 24-bit"); | |
202 case IMGFMT_RGB32: return("RGB 32-bit"); | |
203 case IMGFMT_BGR8: return("BGR 8-bit"); | |
204 case IMGFMT_BGR15: return("BGR 15-bit"); | |
205 case IMGFMT_BGR16: return("BGR 16-bit"); | |
206 case IMGFMT_BGR24: return("BGR 24-bit"); | |
207 case IMGFMT_BGR32: return("BGR 32-bit"); | |
208 case IMGFMT_YVU9: return("Planar YVU9"); | |
209 case IMGFMT_IF09: return("Planar IF09"); | |
210 case IMGFMT_YV12: return("Planar YV12"); | |
211 case IMGFMT_I420: return("Planar I420"); | |
212 case IMGFMT_IYUV: return("Planar IYUV"); | |
213 case IMGFMT_CLPL: return("Planar CLPL"); | |
214 case IMGFMT_IYU1: return("Packed IYU1"); | |
215 case IMGFMT_IYU2: return("Packed IYU2"); | |
216 case IMGFMT_UYVY: return("Packed UYVY"); | |
217 case IMGFMT_UYNV: return("Packed UYNV"); | |
218 case IMGFMT_cyuv: return("Packed CYUV"); | |
219 case IMGFMT_YUY2: return("Packed YUY2"); | |
220 case IMGFMT_YUNV: return("Packed YUNV"); | |
221 case IMGFMT_YVYU: return("Packed YVYU"); | |
222 case IMGFMT_Y41P: return("Packed Y41P"); | |
223 case IMGFMT_Y211: return("Packed Y211"); | |
224 case IMGFMT_Y41T: return("Packed Y41T"); | |
225 case IMGFMT_Y42T: return("Packed Y42T"); | |
226 case IMGFMT_V422: return("Packed V422"); | |
227 case IMGFMT_V655: return("Packed V655"); | |
228 case IMGFMT_CLJR: return("Packed CLJR"); | |
229 case IMGFMT_YUVP: return("Packed YUVP"); | |
230 case IMGFMT_UYVP: return("Packed UYVP"); | |
231 /* case IMGFMT_MPEGPES: return("Mpeg PES");*/ | |
232 } | |
233 return("Unknown"); | |
234 } | |
235 | |
2870 | 236 |
237 /* | |
238 * IO macros | |
239 */ | |
240 | |
241 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
242 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
243 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
244 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
245 | |
246 static void radeon_vid_save_state( void ) | |
247 { | |
248 size_t i; | |
249 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
250 vregs[i].value = INREG(vregs[i].name); | |
251 } | |
252 | |
253 static void radeon_vid_restore_state( void ) | |
254 { | |
255 size_t i; | |
256 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
257 OUTREG(vregs[i].name,vregs[i].value); | |
258 } | |
259 | |
260 static void radeon_vid_stop_video( void ) | |
261 { | |
262 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
263 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
264 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
265 OUTREG(OV0_FILTER_CNTL, 0x0000000f); | |
266 /* | |
267 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
268 (saturation << 8) | | |
269 (saturation << 16)); | |
270 OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1); | |
271 OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey); | |
272 */ | |
273 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
274 OUTREG(OV0_TEST, 0); | |
275 } | |
276 | |
277 static void radeon_vid_display_video( void ) | |
278 { | |
279 int bes_flags; | |
3164 | 280 RTRACE(RVID_MSG"OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
281 RTRACE(RVID_MSG"OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs); | |
282 RTRACE(RVID_MSG"OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 283 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
3164 | 284 RTRACE(RVID_MSG"OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n" |
2951 | 285 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end); |
3164 | 286 RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n" |
2951 | 287 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init); |
2870 | 288 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
289 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
2965 | 290 |
2870 | 291 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
292 | |
3164 | 293 OUTREG(OV0_DEINTERLACE_PATTERN,0x900AAAAA); |
2870 | 294 |
295 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
296 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2965 | 297 |
2870 | 298 OUTREG(OV0_H_INC, besr.h_inc); |
299 OUTREG(OV0_STEP_BY, besr.step_by); | |
300 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
301 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
302 OUTREG(OV0_V_INC, besr.v_inc); | |
303 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
3164 | 304 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
2870 | 305 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
2944 | 306 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 307 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
308 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
309 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
3164 | 310 #if 1 |
3122 | 311 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
312 #endif | |
2870 | 313 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
314 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
315 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
316 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
317 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
318 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
319 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
320 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
321 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
3164 | 322 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
2870 | 323 |
324 bes_flags = SCALER_ENABLE | | |
325 SCALER_DOUBLE_BUFFER | | |
2965 | 326 SCALER_ADAPTIVE_DEINT | |
2870 | 327 SCALER_SMART_SWITCH | |
328 SCALER_HORZ_PICK_NEAREST; | |
329 switch(besr.fourcc) | |
330 { | |
331 case IMGFMT_RGB15: | |
332 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
333 case IMGFMT_RGB16: | |
334 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
335 case IMGFMT_RGB24: | |
336 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
337 case IMGFMT_RGB32: | |
338 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
3164 | 339 /* 4:1:0*/ |
340 case IMGFMT_IF09: | |
2870 | 341 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
3164 | 342 /* 4:2:0 */ |
3122 | 343 case IMGFMT_IYUV: |
2870 | 344 case IMGFMT_I420: |
3164 | 345 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
346 /* 4:2:2 */ | |
347 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
2870 | 348 case IMGFMT_YUY2: |
349 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
350 } | |
3164 | 351 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags); |
2870 | 352 OUTREG(OV0_SCALE_CNTL, bes_flags); |
353 /* | |
354 TODO: | |
355 brightness: -64 : +63 | |
356 saturation: 0 : 31 | |
357 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
358 (saturation << 8) | | |
359 (saturation << 16)); | |
360 OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16); | |
361 | |
362 */ | |
363 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
364 } | |
365 | |
2951 | 366 #define XXX_SRC_X 0 |
367 #define XXX_SRC_Y 0 | |
2870 | 368 |
2944 | 369 #define XXX_WIDTH config->src_width |
370 #define XXX_HEIGHT config->src_height | |
2870 | 371 |
2951 | 372 #define XXX_DRW_W config->dest_width |
373 #define XXX_DRW_H config->dest_height | |
2925 | 374 |
2870 | 375 static int radeon_vid_init_video( mga_vid_config_t *config ) |
376 { | |
3047
ef3b9b104648
Minor speedup of YUY2 decoding. Radeon it's tricked chip
nick
parents:
3020
diff
changeset
|
377 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 378 int is_420; |
3164 | 379 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 380 ,(uint32_t)config->version |
2951 | 381 ,(uint32_t)config->format |
2870 | 382 ,(uint32_t)config->card_type |
383 ,(uint32_t)config->ram_size | |
384 ,(uint32_t)config->src_width | |
385 ,(uint32_t)config->src_height | |
386 ,(uint32_t)config->x_org | |
387 ,(uint32_t)config->y_org | |
388 ,(uint32_t)config->dest_width | |
389 ,(uint32_t)config->dest_height | |
390 ,(uint32_t)config->frame_size | |
391 ,(uint32_t)config->num_frames); | |
2917 | 392 radeon_vid_stop_video(); |
3047
ef3b9b104648
Minor speedup of YUY2 decoding. Radeon it's tricked chip
nick
parents:
3020
diff
changeset
|
393 left = XXX_SRC_X << 16; |
ef3b9b104648
Minor speedup of YUY2 decoding. Radeon it's tricked chip
nick
parents:
3020
diff
changeset
|
394 top = XXX_SRC_Y << 16; |
ef3b9b104648
Minor speedup of YUY2 decoding. Radeon it's tricked chip
nick
parents:
3020
diff
changeset
|
395 src_h = config->src_height; |
ef3b9b104648
Minor speedup of YUY2 decoding. Radeon it's tricked chip
nick
parents:
3020
diff
changeset
|
396 src_w = config->src_width; |
2870 | 397 switch(config->format) |
398 { | |
399 case IMGFMT_RGB15: | |
400 case IMGFMT_BGR15: | |
401 case IMGFMT_RGB16: | |
402 case IMGFMT_BGR16: | |
403 case IMGFMT_RGB24: | |
404 case IMGFMT_BGR24: | |
405 case IMGFMT_RGB32: | |
406 case IMGFMT_BGR32: | |
3164 | 407 /* 4:1:0 */ |
408 case IMGFMT_IF09: | |
2870 | 409 case IMGFMT_YVU9: |
3164 | 410 /* 4:2:0 */ |
2870 | 411 case IMGFMT_IYUV: |
412 case IMGFMT_YV12: | |
413 case IMGFMT_I420: | |
3164 | 414 /* 4:2:2 */ |
415 case IMGFMT_UYVY: | |
2870 | 416 case IMGFMT_YUY2: |
417 break; | |
418 default: | |
3164 | 419 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
2870 | 420 return -1; |
421 } | |
3019 | 422 is_420 = 0; |
3122 | 423 if(config->format == IMGFMT_YV12 || |
424 config->format == IMGFMT_I420 || | |
425 config->format == IMGFMT_IYUV) is_420 = 1; | |
2951 | 426 switch(config->format) |
427 { | |
3164 | 428 /* 4:1:0 */ |
2951 | 429 case IMGFMT_YVU9: |
3164 | 430 case IMGFMT_IF09: |
431 /* 4:2:0 */ | |
2951 | 432 case IMGFMT_IYUV: |
3164 | 433 case IMGFMT_YV12: |
434 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
435 /* 4:2:2 */ | |
436 default: | |
2951 | 437 case IMGFMT_UYVY: |
438 case IMGFMT_YUY2: | |
439 case IMGFMT_RGB15: | |
440 case IMGFMT_BGR15: | |
441 case IMGFMT_RGB16: | |
3047
ef3b9b104648
Minor speedup of YUY2 decoding. Radeon it's tricked chip
nick
parents:
3020
diff
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442 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 443 case IMGFMT_RGB24: |
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444 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 445 case IMGFMT_RGB32: |
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446 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 447 } |
448 | |
2870 | 449 besr.fourcc = config->format; |
450 | |
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451 besr.v_inc = (src_h << 20) / XXX_DRW_H; |
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452 h_inc = (src_w << 12) / XXX_DRW_W; |
2944 | 453 step_by = 1; |
2870 | 454 |
2944 | 455 while(h_inc >= (2 << 12)) { |
456 step_by++; | |
457 h_inc >>= 1; | |
2870 | 458 } |
459 | |
460 /* keep everything in 16.16 */ | |
3164 | 461 besr.base_addr = radeon_mem_base; |
3019 | 462 if(is_420) |
463 { | |
3164 | 464 uint32_t d1line,d2line,d3line; |
465 d1line = top*pitch; | |
466 d2line = src_h*pitch+(d1line>>1); | |
467 d3line = d2line+((src_h*pitch)>>2); | |
468 d1line += (left >> 16) & ~15; | |
469 d2line += (left >> 17) & ~15; | |
470 d3line += (left >> 17) & ~15; | |
471 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
472 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
473 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
474 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
475 { | |
476 uint32_t tmp; | |
477 tmp = besr.vid_buf1_base_adrs; | |
478 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
479 besr.vid_buf2_base_adrs = tmp; | |
480 } | |
3019 | 481 } |
482 else | |
483 { | |
484 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
485 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0; | |
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486 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 487 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
488 } | |
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489 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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490 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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491 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 492 |
2951 | 493 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 494 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 495 ((tmp << 12) & 0xf0000000); |
2870 | 496 |
2951 | 497 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 498 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 499 ((tmp << 12) & 0x70000000); |
500 tmp = (top & 0x0000ffff) + 0x00018000; | |
3122 | 501 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
502 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
3019 | 503 |
504 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
3122 | 505 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
506 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
3019 | 507 |
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508 leftUV = (left >> 17) & 15; |
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509 left = (left >> 16) & 15; |
2944 | 510 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
511 besr.step_by = step_by | (step_by << 8); | |
3164 | 512 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
513 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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514 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
3122 | 515 if(is_420) |
516 { | |
517 src_h = (src_h + 1) >> 1; | |
518 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
519 } | |
520 else besr.p23_blank_lines_at_top = 0; | |
2870 | 521 besr.vid_buf_pitch0_value = pitch; |
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522 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
3164 | 523 RTRACE(RVID_MSG"BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
524 RTRACE(RVID_MSG"BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); | |
525 RTRACE(RVID_MSG"BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 526 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
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527 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
3164 | 528 src_w>>=1; |
529 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
530 besr.p3_x_start_end = besr.p2_x_start_end; | |
2870 | 531 return 0; |
532 } | |
533 | |
534 static void radeon_vid_frame_sel(int frame) | |
535 { | |
3066 | 536 uint32_t off0,off1,off2; |
537 if(frame%2) | |
538 { | |
539 off0 = besr.vid_buf3_base_adrs; | |
540 off1 = besr.vid_buf4_base_adrs; | |
541 off2 = besr.vid_buf5_base_adrs; | |
542 } | |
543 else | |
544 { | |
545 off0 = besr.vid_buf0_base_adrs; | |
546 off1 = besr.vid_buf1_base_adrs; | |
547 off2 = besr.vid_buf2_base_adrs; | |
548 } | |
2917 | 549 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
550 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 551 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
552 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
553 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 554 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 555 } |
556 | |
2951 | 557 static int video_on = 0; |
558 | |
2870 | 559 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
560 { | |
561 int frame; | |
562 | |
563 switch(cmd) | |
564 { | |
565 case MGA_VID_CONFIG: | |
566 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base); | |
567 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base); | |
3164 | 568 RTRACE(RVID_MSG"Received configuration\n"); |
2870 | 569 |
570 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
571 { | |
3164 | 572 printk(RVID_MSG"failed copy from userspace\n"); |
3019 | 573 return -EFAULT; |
2870 | 574 } |
575 if(radeon_config.version != MGA_VID_VERSION){ | |
3164 | 576 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
3019 | 577 return -EFAULT; |
2870 | 578 } |
579 | |
580 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
3164 | 581 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
3019 | 582 return -EFAULT; |
2870 | 583 } |
584 | |
585 if(radeon_config.num_frames<1 || radeon_config.num_frames>4){ | |
3164 | 586 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
3019 | 587 return -EFAULT; |
2870 | 588 } |
589 | |
590 /* FIXME: Fake of G400 ;) or would be better G200 ??? */ | |
591 radeon_config.card_type = 0; | |
592 radeon_config.ram_size = radeon_ram_size; | |
3019 | 593 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
594 radeon_overlay_off &= 0xffff0000; | |
595 if(radeon_overlay_off < 0){ | |
3164 | 596 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
3019 | 597 return -EFAULT; |
598 } | |
3164 | 599 RTRACE(RVID_MSG"using video overlay at offset %p\n",radeon_overlay_off); |
2870 | 600 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
601 { | |
3164 | 602 printk(RVID_MSG"failed copy to userspace\n"); |
3019 | 603 return -EFAULT; |
2870 | 604 } |
3164 | 605 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
2870 | 606 return radeon_vid_init_video(&radeon_config); |
607 break; | |
608 | |
609 case MGA_VID_ON: | |
3164 | 610 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
611 radeon_vid_display_video(); | |
2951 | 612 video_on = 1; |
2870 | 613 break; |
614 | |
615 case MGA_VID_OFF: | |
3164 | 616 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
2951 | 617 if(video_on) radeon_vid_stop_video(); |
618 video_on = 0; | |
2870 | 619 break; |
620 | |
621 case MGA_VID_FSEL: | |
622 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
623 { | |
3164 | 624 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
2870 | 625 return(-EFAULT); |
626 } | |
627 radeon_vid_frame_sel(frame); | |
628 break; | |
629 | |
630 default: | |
3164 | 631 printk(RVID_MSG"Invalid ioctl\n"); |
2870 | 632 return (-EINVAL); |
633 } | |
634 | |
635 return 0; | |
636 } | |
637 | |
638 struct ati_card_id_s | |
639 { | |
3164 | 640 const int id; |
641 const char name[17]; | |
642 }; | |
643 | |
644 const struct ati_card_id_s ati_card_ids[]= | |
2870 | 645 { |
3164 | 646 #ifdef RAGE128 |
647 /* | |
648 This driver should be compatible with Rage128 (pro) chips. | |
649 (include adaptive deinterlacing!!!). | |
650 Moreover: the same logic can be used with Mach64 chips. | |
651 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
652 but they are incompatible by i/o ports. So if enthusiasts will want | |
653 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
654 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
655 fourccs (422 and 420 formats only). | |
656 */ | |
657 /* Rage128 Pro GL */ | |
658 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
659 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
660 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
661 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
662 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
663 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
664 /* Rage128 Pro VR */ | |
665 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
666 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
667 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
668 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
669 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
670 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
671 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
672 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
673 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
674 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
675 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
676 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
677 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
678 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
679 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
680 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
681 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
682 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
683 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
684 /* Rage128 GL */ | |
685 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
686 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
687 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
688 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
689 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
690 /* Rage128 VR */ | |
691 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
692 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
693 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
694 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
695 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
696 /* Rage128 M3 */ | |
697 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 LE" }, | |
698 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 LF" }, | |
699 /* Rage128 Pro Ultra */ | |
700 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128 U1" }, | |
701 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128 U2" }, | |
702 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128 U3" } | |
703 #else | |
704 /* Radeons (indeed: Rage 256 Pro ;) */ | |
2870 | 705 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
706 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
707 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
708 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
709 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
710 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
711 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
712 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
713 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
714 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
715 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
3164 | 716 #endif |
2870 | 717 }; |
718 | |
719 static int radeon_vid_config_card(void) | |
720 { | |
721 struct pci_dev *dev = NULL; | |
722 size_t i; | |
723 | |
724 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
725 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
726 break; | |
3122 | 727 if(!dev) |
2870 | 728 { |
3164 | 729 printk(RVID_MSG"No supported cards found\n"); |
2870 | 730 return FALSE; |
731 } | |
732 | |
733 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
734 radeon_mem_base = dev->resource[0].start; | |
735 | |
3164 | 736 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
737 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
2870 | 738 |
3122 | 739 /* video memory size */ |
740 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
741 | |
3164 | 742 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
3122 | 743 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
744 radeon_ram_size /= 0x100000; | |
3164 | 745 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
2870 | 746 |
747 return TRUE; | |
748 } | |
749 | |
750 | |
751 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
752 { | |
753 return -EINVAL; | |
754 } | |
755 | |
756 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
757 { | |
758 return -EINVAL; | |
759 } | |
760 | |
761 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
762 { | |
763 | |
3164 | 764 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
3019 | 765 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 766 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
767 { | |
3164 | 768 printk(RVID_MSG"error mapping video memory\n"); |
2870 | 769 return(-EAGAIN); |
770 } | |
771 | |
772 return(0); | |
773 } | |
774 | |
775 static int radeon_vid_release(struct inode *inode, struct file *file) | |
776 { | |
777 radeon_vid_in_use = 0; | |
778 radeon_vid_stop_video(); | |
779 | |
780 MOD_DEC_USE_COUNT; | |
781 return 0; | |
782 } | |
783 | |
784 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
785 { | |
786 return -ESPIPE; | |
787 } | |
788 | |
789 static int radeon_vid_open(struct inode *inode, struct file *file) | |
790 { | |
791 int minor = MINOR(inode->i_rdev); | |
792 | |
793 if(minor != 0) | |
794 return(-ENXIO); | |
795 | |
796 if(radeon_vid_in_use == 1) | |
797 return(-EBUSY); | |
798 | |
799 radeon_vid_in_use = 1; | |
800 MOD_INC_USE_COUNT; | |
801 return(0); | |
802 } | |
803 | |
804 #if LINUX_VERSION_CODE >= 0x020400 | |
805 static struct file_operations radeon_vid_fops = | |
806 { | |
807 llseek: radeon_vid_lseek, | |
808 read: radeon_vid_read, | |
809 write: radeon_vid_write, | |
810 ioctl: radeon_vid_ioctl, | |
811 mmap: radeon_vid_mmap, | |
812 open: radeon_vid_open, | |
813 release: radeon_vid_release | |
814 }; | |
815 #else | |
816 static struct file_operations radeon_vid_fops = | |
817 { | |
818 radeon_vid_lseek, | |
819 radeon_vid_read, | |
820 radeon_vid_write, | |
821 NULL, | |
822 NULL, | |
823 radeon_vid_ioctl, | |
824 radeon_vid_mmap, | |
825 radeon_vid_open, | |
826 NULL, | |
827 radeon_vid_release | |
828 }; | |
829 #endif | |
830 | |
831 /* | |
832 * Main Initialization Function | |
833 */ | |
834 | |
835 | |
836 static int radeon_vid_initialize(void) | |
837 { | |
838 radeon_vid_in_use = 0; | |
3164 | 839 #ifdef RAGE128 |
840 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
841 #else | |
842 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
843 #endif | |
2870 | 844 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
845 { | |
3164 | 846 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
2870 | 847 return -EIO; |
848 } | |
849 | |
850 if (!radeon_vid_config_card()) | |
851 { | |
3164 | 852 printk(RVID_MSG"can't configure this card\n"); |
2870 | 853 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
854 return -EINVAL; | |
855 } | |
856 radeon_vid_save_state(); | |
857 return(0); | |
858 } | |
859 | |
860 int init_module(void) | |
861 { | |
862 return radeon_vid_initialize(); | |
863 } | |
864 | |
865 void cleanup_module(void) | |
866 { | |
867 radeon_vid_restore_state(); | |
868 if(radeon_mmio_base) | |
869 iounmap(radeon_mmio_base); | |
870 | |
3164 | 871 RTRACE(RVID_MSG"Cleaning up module\n"); |
2870 | 872 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
873 } | |
874 |