Mercurial > mplayer.hg
annotate cpudetect.c @ 8209:51ed4c00f15b
cosmetics only (for better html output)
author | arpi |
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date | Sat, 16 Nov 2002 05:29:23 +0000 |
parents | 9fc45fe0d444 |
children | 1b2fc92980d9 |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
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17 #ifdef __FreeBSD__ |
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18 #include <sys/types.h> |
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19 #include <sys/sysctl.h> |
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20 #endif |
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21 |
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22 #ifdef __linux__ |
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23 #include <signal.h> |
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24 #endif |
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25 |
2272 | 26 //#define X86_FXSR_MAGIC |
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27 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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28 * help understanding how to use it. Thanks to the Mesa |
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29 * team for SSE support detection and more cpu detect code. |
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30 */ |
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31 |
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32 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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33 |
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34 static void check_os_katmai_support( void ); |
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35 |
2272 | 36 #if 1 |
37 // return TRUE if cpuid supported | |
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38 static int has_cpuid() |
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39 { |
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40 int a, c; |
2272 | 41 |
42 // code from libavcodec: | |
43 __asm__ __volatile__ ( | |
44 /* See if CPUID instruction is supported ... */ | |
45 /* ... Get copies of EFLAGS into eax and ecx */ | |
46 "pushf\n\t" | |
47 "popl %0\n\t" | |
48 "movl %0, %1\n\t" | |
49 | |
50 /* ... Toggle the ID bit in one copy and store */ | |
51 /* to the EFLAGS reg */ | |
52 "xorl $0x200000, %0\n\t" | |
53 "push %0\n\t" | |
54 "popf\n\t" | |
55 | |
56 /* ... Get the (hopefully modified) EFLAGS */ | |
57 "pushf\n\t" | |
58 "popl %0\n\t" | |
59 : "=a" (a), "=c" (c) | |
60 : | |
61 : "cc" | |
62 ); | |
63 | |
64 return (a!=c); | |
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65 } |
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66 #endif |
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67 |
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68 static void |
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69 do_cpuid(unsigned int ax, unsigned int *p) |
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70 { |
2272 | 71 #if 0 |
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72 __asm __volatile( |
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73 "cpuid;" |
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74 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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75 : "0" (ax) |
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76 ); |
2272 | 77 #else |
78 // code from libavcodec: | |
79 __asm __volatile | |
80 ("movl %%ebx, %%esi\n\t" | |
81 "cpuid\n\t" | |
82 "xchgl %%ebx, %%esi" | |
3403 | 83 : "=a" (p[0]), "=S" (p[1]), |
2272 | 84 "=c" (p[2]), "=d" (p[3]) |
85 : "0" (ax)); | |
86 #endif | |
87 | |
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88 } |
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89 |
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90 void GetCpuCaps( CpuCaps *caps) |
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91 { |
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92 unsigned int regs[4]; |
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93 unsigned int regs2[4]; |
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94 |
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95 caps->isX86=1; |
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96 |
3700 | 97 memset(caps, 0, sizeof(*caps)); |
2288 | 98 if (!has_cpuid()) { |
6134 | 99 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 100 return; |
101 } | |
102 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 103 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 104 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 105 if (regs[0]>=0x00000001) |
2280 | 106 { |
2303 | 107 char *tmpstr; |
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108 |
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109 do_cpuid(0x00000001, regs2); |
2301 | 110 |
2303 | 111 tmpstr=GetCpuFriendlyName(regs, regs2); |
5937 | 112 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
2303 | 113 free(tmpstr); |
2301 | 114 |
2288 | 115 caps->cpuType=(regs2[0] >> 8)&0xf; |
116 if(caps->cpuType==0xf){ | |
117 // use extended family (P4, IA64) | |
118 caps->cpuType=8+((regs2[0]>>20)&255); | |
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119 } |
3403 | 120 caps->cpuStepping=regs2[0] & 0xf; |
6135 | 121 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
3403 | 122 caps->cpuType, caps->cpuStepping); |
2288 | 123 |
124 // general feature flags: | |
2272 | 125 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
126 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
127 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 128 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
129 } | |
130 do_cpuid(0x80000000, regs); | |
131 if (regs[0]>=0x80000001) { | |
6134 | 132 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 133 do_cpuid(0x80000001, regs2); |
3840 | 134 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
135 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 136 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
137 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
138 } | |
139 #if 0 | |
5937 | 140 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 141 gCpuCaps.hasMMX, |
142 gCpuCaps.hasMMX2, | |
143 gCpuCaps.hasSSE, | |
144 gCpuCaps.hasSSE2, | |
145 gCpuCaps.has3DNow, | |
146 gCpuCaps.has3DNowExt ); | |
147 #endif | |
148 | |
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149 /* FIXME: Does SSE2 need more OS support, too? */ |
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150 #if defined(__linux__) || defined(__FreeBSD__) |
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151 if (caps->hasSSE) |
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152 check_os_katmai_support(); |
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153 if (!caps->hasSSE) |
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154 caps->hasSSE2 = 0; |
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155 #else |
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156 caps->hasSSE=0; |
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157 caps->hasSSE2 = 0; |
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158 #endif |
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159 // caps->has3DNow=1; |
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160 // caps->hasMMX2 = 0; |
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161 // caps->hasMMX = 0; |
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162 |
4829 | 163 #ifndef HAVE_MMX |
6134 | 164 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 165 caps->hasMMX=0; |
166 #endif | |
167 #ifndef HAVE_MMX2 | |
6134 | 168 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 169 caps->hasMMX2=0; |
170 #endif | |
171 #ifndef HAVE_SSE | |
6134 | 172 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 173 caps->hasSSE=0; |
174 #endif | |
175 #ifndef HAVE_SSE2 | |
6134 | 176 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 177 caps->hasSSE2=0; |
178 #endif | |
179 #ifndef HAVE_3DNOW | |
6134 | 180 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 181 caps->has3DNow=0; |
182 #endif | |
183 #ifndef HAVE_3DNOWEX | |
6134 | 184 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 185 caps->has3DNowExt=0; |
186 #endif | |
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187 } |
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188 |
2301 | 189 |
190 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
191 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
192 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
193 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
194 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
195 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
196 | |
197 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
198 #include "cputable.h" /* get cpuname and cpuvendors */ | |
199 char vendor[17]; | |
2303 | 200 char *retname; |
2301 | 201 int i; |
202 | |
2417 | 203 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 204 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 205 exit(1); |
206 } | |
207 | |
3837 | 208 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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209 |
2301 | 210 for(i=0; i<MAX_VENDORS; i++){ |
211 if(!strcmp(cpuvendors[i].string,vendor)){ | |
212 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
2303 | 213 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 214 } else { |
2303 | 215 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 216 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
217 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
218 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
219 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
220 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
221 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
222 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 223 "to the MPlayer-Developers, so we can add it to the list!\n"); |
224 } | |
225 } | |
226 } | |
227 | |
228 //printf("Detected CPU: %s\n", retname); | |
229 return retname; | |
230 } | |
231 | |
232 #undef CPUID_EXTFAMILY | |
233 #undef CPUID_EXTMODEL | |
234 #undef CPUID_TYPE | |
235 #undef CPUID_FAMILY | |
236 #undef CPUID_MODEL | |
237 #undef CPUID_STEPPING | |
238 | |
239 | |
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240 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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241 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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242 { |
6134 | 243 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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244 |
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245 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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246 * instructions are 3 bytes long. We must increment the instruction |
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247 * pointer manually to avoid repeated execution of the offending |
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248 * instruction. |
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249 * |
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250 * If the SIGILL is caused by a divide-by-zero when unmasked |
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251 * exceptions aren't supported, the SIMD FPU status and control |
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252 * word will be restored at the end of the test, so we don't need |
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253 * to worry about doing it here. Besides, we may not be able to... |
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254 */ |
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255 sc.eip += 3; |
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256 |
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257 gCpuCaps.hasSSE=0; |
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258 } |
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259 |
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260 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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261 { |
6134 | 262 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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263 |
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264 if ( sc.fpstate->magic != 0xffff ) { |
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265 /* Our signal context has the extended FPU state, so reset the |
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266 * divide-by-zero exception mask and clear the divide-by-zero |
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267 * exception bit. |
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268 */ |
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269 sc.fpstate->mxcsr |= 0x00000200; |
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270 sc.fpstate->mxcsr &= 0xfffffffb; |
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271 } else { |
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272 /* If we ever get here, we're completely hosed. |
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273 */ |
6134 | 274 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
275 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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276 } |
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277 } |
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278 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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279 |
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280 /* If we're running on a processor that can do SSE, let's see if we |
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281 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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282 * haven't been configured for a Pentium III but are running on one, |
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283 * and RedHat patched 2.2 kernels that have broken exception handling |
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284 * support for user space apps that do SSE. |
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285 */ |
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286 static void check_os_katmai_support( void ) |
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287 { |
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288 #if defined(__FreeBSD__) |
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289 int has_sse=0, ret; |
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290 size_t len=sizeof(has_sse); |
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291 |
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292 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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293 if (ret || !has_sse) |
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294 gCpuCaps.hasSSE=0; |
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295 |
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296 #elif defined(__linux__) |
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297 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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298 struct sigaction saved_sigill; |
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299 struct sigaction saved_sigfpe; |
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300 |
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301 /* Save the original signal handlers. |
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302 */ |
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303 sigaction( SIGILL, NULL, &saved_sigill ); |
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304 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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305 |
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306 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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307 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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308 |
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309 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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310 * supports the extended FPU save and restore required for SSE. If |
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311 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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312 * doesn't support Streaming SIMD Exceptions, even if the processor |
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313 * does. |
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314 */ |
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315 if ( gCpuCaps.hasSSE ) { |
6134 | 316 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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317 |
2272 | 318 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
319 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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320 |
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321 if ( gCpuCaps.hasSSE ) { |
6134 | 322 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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323 } else { |
6134 | 324 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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325 } |
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326 } |
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327 |
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328 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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329 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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330 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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331 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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332 * as expected, we're okay but we need to clean up after it. |
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333 * |
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334 * Are we being too stringent in our requirement that the OS support |
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335 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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336 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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337 * doesn't even support them. We at least know the user-space SSE |
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338 * support is good in kernels that do support unmasked exceptions, |
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339 * and therefore to be safe I'm going to leave this test in here. |
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340 */ |
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341 if ( gCpuCaps.hasSSE ) { |
6134 | 342 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
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343 |
2272 | 344 // test_os_katmai_exception_support(); |
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345 |
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346 if ( gCpuCaps.hasSSE ) { |
6134 | 347 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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348 } else { |
6134 | 349 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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350 } |
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351 } |
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352 |
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353 /* Restore the original signal handlers. |
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354 */ |
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355 sigaction( SIGILL, &saved_sigill, NULL ); |
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356 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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357 |
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358 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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359 * safe to go ahead and hook out the SSE code throughout Mesa. |
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360 */ |
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361 if ( gCpuCaps.hasSSE ) { |
6134 | 362 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
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363 } else { |
6134 | 364 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
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365 } |
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366 #else |
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367 /* We can't use POSIX signal handling to test the availability of |
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368 * SSE, so we disable it by default. |
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369 */ |
5937 | 370 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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371 gCpuCaps.hasSSE=0; |
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372 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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373 #else |
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374 /* Do nothing on other platforms for now. |
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375 */ |
6134 | 376 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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377 gCpuCaps.hasSSE=0; |
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378 #endif /* __linux__ */ |
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379 } |
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380 #else /* ARCH_X86 */ |
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381 |
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382 void GetCpuCaps( CpuCaps *caps) |
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383 { |
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384 caps->cpuType=0; |
3403 | 385 caps->cpuStepping=0; |
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386 caps->hasMMX=0; |
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387 caps->hasMMX2=0; |
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388 caps->has3DNow=0; |
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389 caps->has3DNowExt=0; |
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390 caps->hasSSE=0; |
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391 caps->hasSSE2=0; |
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392 caps->isX86=0; |
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393 } |
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394 #endif /* !ARCH_X86 */ |