annotate cpudetect.c @ 6135:53a0e8f92bbd

more cpudetect cosmetics
author arpi
date Mon, 20 May 2002 01:00:51 +0000
parents 2f59920361ff
children 9fc45fe0d444
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1 #include "config.h"
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2 #include "cpudetect.h"
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3 #include "mp_msg.h"
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4
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5 CpuCaps gCpuCaps;
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6
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7 #ifdef HAVE_MALLOC_H
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8 #include <malloc.h>
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9 #endif
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10 #include <stdlib.h>
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11
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12 #ifdef ARCH_X86
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13
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14 #include <stdio.h>
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15
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16 #ifdef __FreeBSD__
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17 #include <sys/types.h>
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18 #include <sys/sysctl.h>
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19 #endif
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20
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21 #ifdef __linux__
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22 #include <signal.h>
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23 #endif
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24
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25 //#define X86_FXSR_MAGIC
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26 /* Thanks to the FreeBSD project for some of this cpuid code, and
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27 * help understanding how to use it. Thanks to the Mesa
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28 * team for SSE support detection and more cpu detect code.
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29 */
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30
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31 /* I believe this code works. However, it has only been used on a PII and PIII */
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32
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33 static void check_os_katmai_support( void );
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34
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35 #if 1
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36 // return TRUE if cpuid supported
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37 static int has_cpuid()
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38 {
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39 int a, c;
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40
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41 // code from libavcodec:
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42 __asm__ __volatile__ (
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43 /* See if CPUID instruction is supported ... */
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44 /* ... Get copies of EFLAGS into eax and ecx */
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45 "pushf\n\t"
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46 "popl %0\n\t"
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47 "movl %0, %1\n\t"
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48
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49 /* ... Toggle the ID bit in one copy and store */
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50 /* to the EFLAGS reg */
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51 "xorl $0x200000, %0\n\t"
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52 "push %0\n\t"
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53 "popf\n\t"
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54
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55 /* ... Get the (hopefully modified) EFLAGS */
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56 "pushf\n\t"
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57 "popl %0\n\t"
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58 : "=a" (a), "=c" (c)
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59 :
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60 : "cc"
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61 );
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62
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63 return (a!=c);
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64 }
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65 #endif
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66
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67 static void
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68 do_cpuid(unsigned int ax, unsigned int *p)
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69 {
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70 #if 0
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71 __asm __volatile(
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72 "cpuid;"
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73 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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74 : "0" (ax)
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75 );
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76 #else
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77 // code from libavcodec:
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78 __asm __volatile
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79 ("movl %%ebx, %%esi\n\t"
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80 "cpuid\n\t"
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81 "xchgl %%ebx, %%esi"
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82 : "=a" (p[0]), "=S" (p[1]),
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83 "=c" (p[2]), "=d" (p[3])
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84 : "0" (ax));
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85 #endif
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86
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87 }
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88
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89 void GetCpuCaps( CpuCaps *caps)
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90 {
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91 unsigned int regs[4];
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92 unsigned int regs2[4];
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93
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94 caps->isX86=1;
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95
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96 memset(caps, 0, sizeof(*caps));
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97 if (!has_cpuid()) {
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98 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
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99 return;
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100 }
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101 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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102 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
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103 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
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104 if (regs[0]>=0x00000001)
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105 {
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106 char *tmpstr;
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107
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108 do_cpuid(0x00000001, regs2);
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109
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110 tmpstr=GetCpuFriendlyName(regs, regs2);
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111 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
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112 free(tmpstr);
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113
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114 caps->cpuType=(regs2[0] >> 8)&0xf;
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115 if(caps->cpuType==0xf){
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116 // use extended family (P4, IA64)
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117 caps->cpuType=8+((regs2[0]>>20)&255);
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118 }
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119 caps->cpuStepping=regs2[0] & 0xf;
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120 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
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121 caps->cpuType, caps->cpuStepping);
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122
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123 // general feature flags:
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124 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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125 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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126 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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127 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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128 }
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129 do_cpuid(0x80000000, regs);
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130 if (regs[0]>=0x80000001) {
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131 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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132 do_cpuid(0x80000001, regs2);
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133 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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134 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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135 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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136 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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137 }
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138 #if 0
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139 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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140 gCpuCaps.hasMMX,
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141 gCpuCaps.hasMMX2,
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142 gCpuCaps.hasSSE,
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143 gCpuCaps.hasSSE2,
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144 gCpuCaps.has3DNow,
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145 gCpuCaps.has3DNowExt );
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146 #endif
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147
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148 /* FIXME: Does SSE2 need more OS support, too? */
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149 #if defined(__linux__) || defined(__FreeBSD__)
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150 if (caps->hasSSE)
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151 check_os_katmai_support();
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152 if (!caps->hasSSE)
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153 caps->hasSSE2 = 0;
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154 #else
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155 caps->hasSSE=0;
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156 caps->hasSSE2 = 0;
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157 #endif
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158 // caps->has3DNow=1;
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159 // caps->hasMMX2 = 0;
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160 // caps->hasMMX = 0;
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161
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162 #ifndef HAVE_MMX
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163 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
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164 caps->hasMMX=0;
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165 #endif
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166 #ifndef HAVE_MMX2
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167 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
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168 caps->hasMMX2=0;
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169 #endif
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170 #ifndef HAVE_SSE
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171 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
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172 caps->hasSSE=0;
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173 #endif
35ed5387b804 dont ignore --disable-mmx, ...
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174 #ifndef HAVE_SSE2
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175 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
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176 caps->hasSSE2=0;
35ed5387b804 dont ignore --disable-mmx, ...
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177 #endif
35ed5387b804 dont ignore --disable-mmx, ...
michael
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diff changeset
178 #ifndef HAVE_3DNOW
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179 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
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180 caps->has3DNow=0;
35ed5387b804 dont ignore --disable-mmx, ...
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181 #endif
35ed5387b804 dont ignore --disable-mmx, ...
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parents: 3850
diff changeset
182 #ifndef HAVE_3DNOWEX
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183 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
4829
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184 caps->has3DNowExt=0;
35ed5387b804 dont ignore --disable-mmx, ...
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185 #endif
2268
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186 }
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187
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188
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189 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
b4c4c832cce7 Detect and show cpu name.
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190 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
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191 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
b4c4c832cce7 Detect and show cpu name.
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192 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
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193 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
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194 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
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195
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196 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
b4c4c832cce7 Detect and show cpu name.
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197 #include "cputable.h" /* get cpuname and cpuvendors */
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198 char vendor[17];
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199 char *retname;
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200 int i;
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201
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202 if (NULL==(retname=(char*)malloc(256))) {
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203 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
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204 exit(1);
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205 }
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206
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parents: 3700
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207 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
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208
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209 for(i=0; i<MAX_VENDORS; i++){
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210 if(!strcmp(cpuvendors[i].string,vendor)){
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211 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
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parents: 2301
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212 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
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213 } else {
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214 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
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215 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
4b18bf35f153 printf to mp_msg
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216 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string);
4b18bf35f153 printf to mp_msg
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217 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE);
4b18bf35f153 printf to mp_msg
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218 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
4b18bf35f153 printf to mp_msg
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219 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
4b18bf35f153 printf to mp_msg
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220 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
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221 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
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b4c4c832cce7 Detect and show cpu name.
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222 "to the MPlayer-Developers, so we can add it to the list!\n");
b4c4c832cce7 Detect and show cpu name.
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223 }
b4c4c832cce7 Detect and show cpu name.
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224 }
b4c4c832cce7 Detect and show cpu name.
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225 }
b4c4c832cce7 Detect and show cpu name.
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226
b4c4c832cce7 Detect and show cpu name.
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227 //printf("Detected CPU: %s\n", retname);
b4c4c832cce7 Detect and show cpu name.
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228 return retname;
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229 }
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230
b4c4c832cce7 Detect and show cpu name.
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231 #undef CPUID_EXTFAMILY
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232 #undef CPUID_EXTMODEL
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233 #undef CPUID_TYPE
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234 #undef CPUID_FAMILY
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235 #undef CPUID_MODEL
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236 #undef CPUID_STEPPING
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237
b4c4c832cce7 Detect and show cpu name.
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238
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arpi
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diff changeset
239 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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240 static void sigill_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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241 {
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242 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
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243
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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244 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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245 * instructions are 3 bytes long. We must increment the instruction
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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246 * pointer manually to avoid repeated execution of the offending
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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247 * instruction.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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248 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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249 * If the SIGILL is caused by a divide-by-zero when unmasked
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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250 * exceptions aren't supported, the SIMD FPU status and control
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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251 * word will be restored at the end of the test, so we don't need
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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252 * to worry about doing it here. Besides, we may not be able to...
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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253 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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254 sc.eip += 3;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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255
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
256 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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257 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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258
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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259 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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260 {
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261 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
2268
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262
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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263 if ( sc.fpstate->magic != 0xffff ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
264 /* Our signal context has the extended FPU state, so reset the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
265 * divide-by-zero exception mask and clear the divide-by-zero
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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266 * exception bit.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
267 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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268 sc.fpstate->mxcsr |= 0x00000200;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
269 sc.fpstate->mxcsr &= 0xfffffffb;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
270 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
271 /* If we ever get here, we're completely hosed.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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272 */
6134
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273 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
2f59920361ff cosmetics on CPU detection messages
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274 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
2268
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275 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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276 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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277 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
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arpi
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278
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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279 /* If we're running on a processor that can do SSE, let's see if we
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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280 * are allowed to or not. This will catch 2.4.0 or later kernels that
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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281 * haven't been configured for a Pentium III but are running on one,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
282 * and RedHat patched 2.2 kernels that have broken exception handling
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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283 * support for user space apps that do SSE.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
284 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
285 static void check_os_katmai_support( void )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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286 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
287 #if defined(__FreeBSD__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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288 int has_sse=0, ret;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
289 size_t len=sizeof(has_sse);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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290
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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291 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
292 if (ret || !has_sse)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
293 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
294
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
295 #elif defined(__linux__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
296 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
297 struct sigaction saved_sigill;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
298 struct sigaction saved_sigfpe;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
299
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
300 /* Save the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
301 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
302 sigaction( SIGILL, NULL, &saved_sigill );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
303 sigaction( SIGFPE, NULL, &saved_sigfpe );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
304
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
305 signal( SIGILL, (void (*)(int))sigill_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
306 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
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arpi
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diff changeset
307
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
308 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
309 * supports the extended FPU save and restore required for SSE. If
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
310 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
311 * doesn't support Streaming SIMD Exceptions, even if the processor
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
312 * does.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
313 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
314 if ( gCpuCaps.hasSSE ) {
6134
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arpi
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diff changeset
315 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
2268
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arpi
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diff changeset
316
2272
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317 // __asm __volatile ("xorps %%xmm0, %%xmm0");
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318 __asm __volatile ("xorps %xmm0, %xmm0");
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319
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320 if ( gCpuCaps.hasSSE ) {
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321 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
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322 } else {
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323 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
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324 }
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325 }
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326
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327 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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328 * it supports unmasked SIMD FPU exceptions. If we unmask the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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329 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
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330 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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331 * as expected, we're okay but we need to clean up after it.
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332 *
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333 * Are we being too stringent in our requirement that the OS support
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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334 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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335 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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336 * doesn't even support them. We at least know the user-space SSE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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337 * support is good in kernels that do support unmasked exceptions,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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338 * and therefore to be safe I'm going to leave this test in here.
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339 */
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340 if ( gCpuCaps.hasSSE ) {
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341 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
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342
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343 // test_os_katmai_exception_support();
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344
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345 if ( gCpuCaps.hasSSE ) {
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346 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
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347 } else {
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348 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
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349 }
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350 }
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351
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352 /* Restore the original signal handlers.
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353 */
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354 sigaction( SIGILL, &saved_sigill, NULL );
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355 sigaction( SIGFPE, &saved_sigfpe, NULL );
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356
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357 /* If we've gotten to here and the XMM CPUID bit is still set, we're
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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358 * safe to go ahead and hook out the SSE code throughout Mesa.
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359 */
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360 if ( gCpuCaps.hasSSE ) {
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361 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
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362 } else {
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363 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
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364 }
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365 #else
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366 /* We can't use POSIX signal handling to test the availability of
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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367 * SSE, so we disable it by default.
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368 */
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369 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
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370 gCpuCaps.hasSSE=0;
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371 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
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372 #else
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373 /* Do nothing on other platforms for now.
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374 */
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375 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
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376 gCpuCaps.hasSSE=0;
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377 #endif /* __linux__ */
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378 }
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379 #else /* ARCH_X86 */
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380
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381 void GetCpuCaps( CpuCaps *caps)
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382 {
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383 caps->cpuType=0;
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384 caps->cpuStepping=0;
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385 caps->hasMMX=0;
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386 caps->hasMMX2=0;
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387 caps->has3DNow=0;
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388 caps->has3DNowExt=0;
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389 caps->hasSSE=0;
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390 caps->hasSSE2=0;
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391 caps->isX86=0;
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392 }
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393 #endif /* !ARCH_X86 */