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1 /*
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2 * drivers/video/radeonfb.c
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3 * framebuffer driver for ATI Radeon chipset video boards
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4 *
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5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
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6 *
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7 *
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8 * ChangeLog:
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9 * 2000-08-03 initial version 0.0.1
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10 * 2000-09-10 more bug fixes, public release 0.0.5
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11 * 2001-02-19 mode bug fixes, 0.0.7
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12 * 2001-07-05 fixed scrolling issues, engine initialization,
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13 * and minor mode tweaking, 0.0.9
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14 *
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1912
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15 * 2001-09-07 Radeon VE support
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1913
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16 * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
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17 * (limitations: on dualhead Radeons (VE, M6, M7)
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18 * driver works only on second head (DVI port).
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19 * TVout is not supported too. M6 & M7 chips
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20 * currently are not supported. Driver has a lot
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21 * of other bugs. Probably they can be solved by
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22 * importing XFree86 code, which has ATI's support).,
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23 * 0.0.11
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1914
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24 * 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
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25 * console switching fixes, blanking fixes,
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26 * 0.1.0-ve.0
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27 * 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>),
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28 * Fixed bug of rom bios detection on VE (by NK),
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29 * Minor code cleanup (by NK),
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30 * Enable CRT port on VE (by NK),
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31 * Disable SURFACE_CNTL because mplayer doesn't work
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32 * propertly (by NK)
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33 * 0.1.0-ve.1
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34 * 2001-09-25 MTRR support (by NK)
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35 * 0.1.0-ve.2
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36 * Special thanks to ATI DevRel team for their hardware donations.
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37 *
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38 * LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in
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39 * dual monitor configuration. TVout is not supported too.
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40 * Probably these problems can be solved by importing XFree86 code, which
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41 * has ATI's support.
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42 *
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43 * Mini-HOWTO: This driver doesn't accept any options. It only switches your
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44 * video card to graphics mode. Standard way to change video modes and other
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45 * video attributes is using 'fbset' utility.
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46 * Sample:
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47 *
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48 * #!/bin/sh
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49 * fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767
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50 *
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51 */
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52
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1966
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53 #define RADEON_VERSION "0.1.0-ve.2"
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54
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55 #include <linux/config.h>
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56 #include <linux/module.h>
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57 #include <linux/kernel.h>
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58 #include <linux/errno.h>
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59 #include <linux/string.h>
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60 #include <linux/mm.h>
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61 #include <linux/tty.h>
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1966
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62 #include <linux/slab.h>
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63 #include <linux/delay.h>
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64 #include <linux/fb.h>
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65 #include <linux/console.h>
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66 #include <linux/selection.h>
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67 #include <linux/ioport.h>
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68 #include <linux/init.h>
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69 #include <linux/pci.h>
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70
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71 #include <asm/io.h>
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72
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73 #include <video/fbcon.h>
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74 #include <video/fbcon-cfb8.h>
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75 #include <video/fbcon-cfb16.h>
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76 #include <video/fbcon-cfb24.h>
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77 #include <video/fbcon-cfb32.h>
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78
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1951
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79 #ifdef CONFIG_MTRR
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80 #include <asm/mtrr.h>
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81 #endif
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82
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1911
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83 #include "radeon.h"
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84
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85
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86 #define DEBUG 0
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87
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88 #if DEBUG
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89 #define RTRACE printk
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90 #else
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91 #define RTRACE if(0) printk
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92 #endif
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93
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94
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95
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96 enum radeon_chips {
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97 RADEON_QD,
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98 RADEON_QE,
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99 RADEON_QF,
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100 RADEON_QG,
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101 RADEON_QY,
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102 RADEON_QZ,
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103 RADEON_LY,
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104 RADEON_LZ,
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105 RADEON_LW,
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106 R200_QL,
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107 RV200_QW
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108 };
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109
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110 enum radeon_montype
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111 {
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112 MT_NONE,
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113 MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
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114 MT_LCD, /* Liquid Crystal Display */
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115 MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
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116 MT_CTV, /* Composite TV out (not in VE) */
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117 MT_STV /* S-Video TV out (probably in VE only) */
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118 };
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119
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120 enum radeon_ddctype
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121 {
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122 DDC_NONE_DETECTED,
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123 DDC_MONID,
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124 DDC_DVI,
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125 DDC_VGA,
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126 DDC_CRT2
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127 };
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128
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129 enum radeon_connectortype
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130 {
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131 CONNECTOR_NONE,
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132 CONNECTOR_PROPRIETARY,
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133 CONNECTOR_CRT,
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134 CONNECTOR_DVI_I,
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135 CONNECTOR_DVI_D
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136 };
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137
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138 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
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139 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
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140 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
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141 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
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142 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
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1913
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143 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
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144 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
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145 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
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146 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
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147 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
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148 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_R200_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, R200_QL},
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149 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RV200_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RV200_QW},
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150 { 0, }
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151 };
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152 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
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153
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154
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155 typedef struct {
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156 u16 reg;
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157 u32 val;
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158 } reg_val;
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159
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160
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161 /* these common regs are cleared before mode setting so they do not
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162 * interfere with anything
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163 */
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164 reg_val common_regs[] = {
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165 { OVR_CLR, 0 },
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166 { OVR_WID_LEFT_RIGHT, 0 },
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167 { OVR_WID_TOP_BOTTOM, 0 },
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168 { OV0_SCALE_CNTL, 0 },
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169 { SUBPIC_CNTL, 0 },
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170 { VIPH_CONTROL, 0 },
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171 { I2C_CNTL_1, 0 },
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172 { GEN_INT_CNTL, 0 },
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173 { CAP0_TRIG_CNTL, 0 },
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174 };
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175
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176 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
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177
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178 typedef struct {
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179 u8 clock_chip_type;
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180 u8 struct_size;
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181 u8 accelerator_entry;
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182 u8 VGA_entry;
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183 u16 VGA_table_offset;
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184 u16 POST_table_offset;
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185 u16 XCLK;
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186 u16 MCLK;
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187 u8 num_PLL_blocks;
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188 u8 size_PLL_blocks;
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189 u16 PCLK_ref_freq;
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190 u16 PCLK_ref_divider;
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191 u32 PCLK_min_freq;
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192 u32 PCLK_max_freq;
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193 u16 MCLK_ref_freq;
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194 u16 MCLK_ref_divider;
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195 u32 MCLK_min_freq;
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196 u32 MCLK_max_freq;
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197 u16 XCLK_ref_freq;
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198 u16 XCLK_ref_divider;
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199 u32 XCLK_min_freq;
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200 u32 XCLK_max_freq;
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201 } __attribute__ ((packed)) PLL_BLOCK;
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202
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203
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204 struct pll_info {
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205 int ppll_max;
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206 int ppll_min;
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207 int xclk;
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208 int ref_div;
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209 int ref_clk;
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210 };
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211
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212
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213 struct ram_info {
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214 int ml;
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215 int mb;
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216 int trcd;
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217 int trp;
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218 int twr;
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219 int cl;
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220 int tr2w;
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221 int loop_latency;
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222 int rloop;
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223 };
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224
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225
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226 struct radeon_regs {
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227 u32 crtc_h_total_disp;
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228 u32 crtc_h_sync_strt_wid;
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229 u32 crtc_v_total_disp;
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230 u32 crtc_v_sync_strt_wid;
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231 u32 crtc_pitch;
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232 u32 flags;
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233 u32 pix_clock;
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234 int xres, yres;
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235 int bpp;
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236 u32 crtc_gen_cntl;
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237 u32 crtc_ext_cntl;
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238 #if defined(__BIG_ENDIAN)
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239 u32 surface_cntl;
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240 #endif
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241 u32 dac_cntl;
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242 u32 dda_config;
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243 u32 dda_on_off;
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244 u32 ppll_div_3;
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245 u32 ppll_ref_div;
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246 };
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247
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248
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249 struct radeonfb_info {
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250 struct fb_info info;
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251
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252 struct radeon_regs state;
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253 struct radeon_regs init_state;
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254
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255 char name[17];
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256 char ram_type[12];
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257
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258 int hasCRTC2;
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259 int crtDispType;
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260 int dviDispType;
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261 int hasTVout;
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262 int isM7;
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263 int isR200;
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264
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265 u32 mmio_base_phys;
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266 u32 fb_base_phys;
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267
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268 u32 mmio_base;
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269 u32 fb_base;
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270
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271 struct pci_dev *pdev;
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272
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273 struct display disp;
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274 int currcon;
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275 struct display *currcon_display;
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276
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277 struct { u8 red, green, blue, pad; } palette[256];
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278
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279 int chipset;
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280 int video_ram;
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281 u8 rev;
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282 int pitch, bpp, depth;
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283 int xres, yres, pixclock;
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284
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285 u32 dp_gui_master_cntl;
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286
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287 struct pll_info pll;
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288 int pll_output_freq, post_div, fb_div;
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289
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290 struct ram_info ram;
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291
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292 u32 hack_crtc_ext_cntl;
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293 u32 hack_crtc_v_sync_strt_wid;
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294 #ifdef CONFIG_MTRR
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295 struct { int vram; int vram_valid; } mtrr;
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296 #endif
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297 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
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298 union {
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299 #if defined(FBCON_HAS_CFB16)
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300 u_int16_t cfb16[16];
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301 #endif
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302 #if defined(FBCON_HAS_CFB24)
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303 u_int32_t cfb24[16];
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304 #endif
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305 #if defined(FBCON_HAS_CFB32)
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306 u_int32_t cfb32[16];
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307 #endif
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308 } con_cmap;
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309 #endif
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310 };
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311
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312
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313 static struct fb_var_screeninfo radeonfb_default_var = {
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314 640, 480, 640, 480, 0, 0, 8, 0,
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315 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
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316 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
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317 0, FB_VMODE_NONINTERLACED
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318 };
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319
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320
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321 /*
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322 * IO macros
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323 */
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324
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325 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
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326 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
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327 #define INREG(addr) readl((rinfo->mmio_base)+addr)
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328 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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329
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330 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
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331 OUTREG(CLOCK_CNTL_DATA, val)
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332 #define OUTPLLP(addr,val,mask) \
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333 do { \
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334 unsigned int _tmp = INPLL(addr); \
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335 _tmp &= (mask); \
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336 _tmp |= (val); \
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337 OUTPLL(addr, _tmp); \
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338 } while (0)
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339
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340 #define OUTREGP(addr,val,mask) \
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341 do { \
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342 unsigned int _tmp = INREG(addr); \
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343 _tmp &= (mask); \
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344 _tmp |= (val); \
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345 OUTREG(addr, _tmp); \
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346 } while (0)
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347
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348
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349 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
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350 {
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351 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
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352 return (INREG(CLOCK_CNTL_DATA));
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353 }
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354
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355 #define INPLL(addr) _INPLL(rinfo, addr)
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356
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357
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358 /*
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359 * 2D engine routines
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360 */
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361
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362 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
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363 {
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364 int i;
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365
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366 /* initiate flush */
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367 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
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368 ~RB2D_DC_FLUSH_ALL);
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369
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370 for (i=0; i < 2000000; i++) {
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371 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
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372 break;
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373 }
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374 }
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375
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376
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377 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
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378 {
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379 int i;
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380
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381 for (i=0; i<2000000; i++)
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382 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
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383 return;
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384 }
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385
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386
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387 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
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388 {
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389 int i;
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390
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391 /* ensure FIFO is empty before waiting for idle */
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392 _radeon_fifo_wait (rinfo, 64);
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393
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394 for (i=0; i<2000000; i++) {
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395 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
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396 radeon_engine_flush (rinfo);
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397 return;
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398 }
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399 }
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400 }
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401
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402
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403 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
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404 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
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405
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406
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407
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408 /*
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409 * helper routines
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410 */
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411
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412 static __inline__ u32 radeon_get_dstbpp(u16 depth)
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413 {
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414 switch (depth) {
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415 case 8:
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416 return DST_8BPP;
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417 case 15:
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418 return DST_15BPP;
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419 case 16:
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420 return DST_16BPP;
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421 case 24:
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422 return DST_24BPP;
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423 case 32:
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424 return DST_32BPP;
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425 default:
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426 return 0;
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427 }
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428 }
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429
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430
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431 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
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432 {
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433 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
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434
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435 radeon_engine_flush (rinfo);
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436
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437 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
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438 mclk_cntl = INPLL(MCLK_CNTL);
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439
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440 OUTPLL(MCLK_CNTL, (mclk_cntl |
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441 FORCEON_MCLKA |
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442 FORCEON_MCLKB |
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443 FORCEON_YCLKA |
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444 FORCEON_YCLKB |
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445 FORCEON_MC |
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446 FORCEON_AIC));
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447 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
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448
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449 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
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450 SOFT_RESET_CP |
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451 SOFT_RESET_HI |
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452 SOFT_RESET_SE |
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453 SOFT_RESET_RE |
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454 SOFT_RESET_PP |
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455 SOFT_RESET_E2 |
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456 SOFT_RESET_RB |
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457 SOFT_RESET_HDP);
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458 INREG(RBBM_SOFT_RESET);
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459 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
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460 ~(SOFT_RESET_CP |
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461 SOFT_RESET_HI |
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462 SOFT_RESET_SE |
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463 SOFT_RESET_RE |
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464 SOFT_RESET_PP |
|
|
465 SOFT_RESET_E2 |
|
|
466 SOFT_RESET_RB |
|
|
467 SOFT_RESET_HDP));
|
|
468 INREG(RBBM_SOFT_RESET);
|
|
469
|
|
470 OUTPLL(MCLK_CNTL, mclk_cntl);
|
|
471 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
|
|
472 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
|
|
473
|
|
474 return;
|
|
475 }
|
|
476
|
|
477 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
|
|
478
|
|
479
|
|
480 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
|
|
481 {
|
|
482 switch (post_div) {
|
|
483 case 1:
|
|
484 return 0x00;
|
|
485 case 2:
|
|
486 return 0x01;
|
|
487 case 3:
|
|
488 return 0x04;
|
|
489 case 4:
|
|
490 return 0x02;
|
|
491 case 6:
|
|
492 return 0x06;
|
|
493 case 8:
|
|
494 return 0x03;
|
|
495 case 12:
|
|
496 return 0x07;
|
|
497 default:
|
|
498 return 0x02;
|
|
499 }
|
|
500 }
|
|
501
|
|
502
|
|
503
|
|
504 static __inline__ int round_div(int num, int den)
|
|
505 {
|
|
506 return (num + (den / 2)) / den;
|
|
507 }
|
|
508
|
|
509
|
|
510
|
|
511 static __inline__ int min_bits_req(int val)
|
|
512 {
|
|
513 int bits_req = 0;
|
|
514
|
|
515 if (val == 0)
|
|
516 bits_req = 1;
|
|
517
|
|
518 while (val) {
|
|
519 val >>= 1;
|
|
520 bits_req++;
|
|
521 }
|
|
522
|
|
523 return (bits_req);
|
|
524 }
|
|
525
|
|
526
|
|
527 static __inline__ int _max(int val1, int val2)
|
|
528 {
|
|
529 if (val1 >= val2)
|
|
530 return val1;
|
|
531 else
|
|
532 return val2;
|
|
533 }
|
|
534
|
|
535
|
|
536
|
|
537 /*
|
|
538 * globals
|
|
539 */
|
|
540
|
|
541 static char fontname[40] __initdata;
|
|
542 static char *mode_option __initdata;
|
|
543 static char noaccel __initdata = 0;
|
1951
|
544 static int nomtrr __initdata = 0;
|
1911
|
545
|
1914
|
546 #if 0
|
1911
|
547 #ifdef FBCON_HAS_CFB8
|
|
548 static struct display_switch fbcon_radeon8;
|
|
549 #endif
|
1914
|
550 #endif
|
1911
|
551
|
1951
|
552 #ifdef CONFIG_MTRR
|
|
553 static int mtrr = 1;
|
|
554 #endif
|
|
555
|
1911
|
556 /*
|
|
557 * prototypes
|
|
558 */
|
|
559
|
|
560 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
561 struct fb_info *info);
|
|
562 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
563 struct fb_info *info);
|
|
564 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
565 struct fb_info *info);
|
|
566 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
567 struct fb_info *info);
|
|
568 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
569 struct fb_info *info);
|
|
570 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
571 struct fb_info *info);
|
|
572 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
573 unsigned long arg, int con, struct fb_info *info);
|
|
574 static int radeonfb_switch (int con, struct fb_info *info);
|
|
575 static int radeonfb_updatevar (int con, struct fb_info *info);
|
|
576 static void radeonfb_blank (int blank, struct fb_info *info);
|
|
577 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
|
|
578 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
579 unsigned *blue, unsigned *transp,
|
|
580 struct fb_info *info);
|
|
581 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
582 unsigned blue, unsigned transp, struct fb_info *info);
|
1914
|
583 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
|
1911
|
584 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
585 struct radeon_regs *save);
|
|
586 static void radeon_engine_init (struct radeonfb_info *rinfo);
|
|
587 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
588 struct fb_var_screeninfo *mode);
|
|
589 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
590 struct radeon_regs *mode);
|
|
591 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
|
|
592 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
|
|
593 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
|
|
594 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
595 const struct pci_device_id *ent);
|
|
596 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
|
|
597 static char *radeon_find_rom(struct radeonfb_info *rinfo);
|
|
598 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
|
1914
|
599 static void do_install_cmap(int con, struct fb_info *info);
|
|
600 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
601 struct fb_var_screeninfo *var,
|
|
602 struct fb_var_screeninfo *v,
|
|
603 int nom, int den);
|
1911
|
604
|
|
605 static struct fb_ops radeon_fb_ops = {
|
|
606 fb_get_fix: radeonfb_get_fix,
|
|
607 fb_get_var: radeonfb_get_var,
|
|
608 fb_set_var: radeonfb_set_var,
|
|
609 fb_get_cmap: radeonfb_get_cmap,
|
|
610 fb_set_cmap: radeonfb_set_cmap,
|
|
611 fb_pan_display: radeonfb_pan_display,
|
|
612 fb_ioctl: radeonfb_ioctl,
|
|
613 };
|
|
614
|
|
615
|
|
616 static struct pci_driver radeonfb_driver = {
|
|
617 name: "radeonfb",
|
|
618 id_table: radeonfb_pci_table,
|
|
619 probe: radeonfb_pci_register,
|
|
620 remove: radeonfb_pci_unregister,
|
|
621 };
|
|
622
|
|
623
|
|
624 int __init radeonfb_init (void)
|
|
625 {
|
1951
|
626 #ifdef CONFIG_MTRR
|
|
627 if (nomtrr) {
|
|
628 mtrr = 0;
|
|
629 printk("radeonfb: Parameter NOMTRR set\n");
|
|
630 }
|
|
631 #endif
|
|
632 return pci_module_init (&radeonfb_driver);
|
1911
|
633 }
|
|
634
|
|
635
|
|
636 void __exit radeonfb_exit (void)
|
|
637 {
|
|
638 pci_unregister_driver (&radeonfb_driver);
|
|
639 }
|
|
640
|
|
641
|
|
642 int __init radeonfb_setup (char *options)
|
|
643 {
|
|
644 char *this_opt;
|
|
645
|
|
646 if (!options || !*options)
|
|
647 return 0;
|
|
648
|
|
649 for (this_opt = strtok (options, ","); this_opt;
|
|
650 this_opt = strtok (NULL, ",")) {
|
|
651 if (!strncmp (this_opt, "font:", 5)) {
|
|
652 char *p;
|
|
653 int i;
|
|
654
|
|
655 p = this_opt + 5;
|
|
656 for (i=0; i<sizeof (fontname) - 1; i++)
|
|
657 if (!*p || *p == ' ' || *p == ',')
|
|
658 break;
|
|
659 memcpy(fontname, this_opt + 5, i);
|
|
660 } else if (!strncmp(this_opt, "noaccel", 7)) {
|
|
661 noaccel = 1;
|
|
662 }
|
1951
|
663 #ifdef CONFIG_MTRR
|
|
664 else if(!strncmp(this_opt, "nomtrr", 6)) {
|
|
665 mtrr = 0;
|
|
666 }
|
|
667 #endif
|
1911
|
668 else mode_option = this_opt;
|
|
669 }
|
|
670
|
|
671 return 0;
|
|
672 }
|
|
673
|
|
674 #ifdef MODULE
|
|
675 module_init(radeonfb_init);
|
|
676 module_exit(radeonfb_exit);
|
|
677 #endif
|
|
678
|
|
679
|
1915
|
680 MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)");
|
|
681 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION);
|
1951
|
682 #ifdef CONFIG_MTRR
|
|
683 MODULE_PARM(nomtrr, "i");
|
|
684 MODULE_PARM_DESC(nomtrr, "Don't touch MTRR (touch=0(default))");
|
|
685 #endif
|
1911
|
686
|
1915
|
687 static char * GET_MON_NAME(int type)
|
|
688 {
|
|
689 char *pret;
|
|
690 switch(type)
|
|
691 {
|
|
692 case MT_NONE: pret = "no"; break;
|
|
693 case MT_CRT: pret = "CRT"; break;
|
|
694 case MT_DFP: pret = "DFP"; break;
|
|
695 case MT_LCD: pret = "LCD"; break;
|
|
696 case MT_CTV: pret = "CTV"; break;
|
|
697 case MT_STV: pret = "STV"; break;
|
|
698 default: pret = "Unknown";
|
|
699 }
|
|
700 return pret;
|
|
701 }
|
1911
|
702
|
|
703
|
|
704 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
705 const struct pci_device_id *ent)
|
|
706 {
|
|
707 struct radeonfb_info *rinfo;
|
|
708 u32 tmp;
|
|
709 int i, j;
|
|
710 char *bios_seg = NULL;
|
|
711
|
|
712 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
|
|
713 if (!rinfo) {
|
|
714 printk ("radeonfb: could not allocate memory\n");
|
|
715 return -ENODEV;
|
|
716 }
|
|
717
|
|
718 memset (rinfo, 0, sizeof (struct radeonfb_info));
|
|
719
|
|
720 /* enable device */
|
|
721 {
|
|
722 int err;
|
|
723
|
|
724 if ((err = pci_enable_device(pdev))) {
|
|
725 printk("radeonfb: cannot enable device\n");
|
|
726 kfree (rinfo);
|
|
727 return -ENODEV;
|
|
728 }
|
|
729 }
|
|
730
|
|
731 /* set base addrs */
|
|
732 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
|
|
733 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
|
|
734
|
|
735 /* request the mem regions */
|
|
736 if (!request_mem_region (rinfo->fb_base_phys,
|
|
737 pci_resource_len(pdev, 0), "radeonfb")) {
|
|
738 printk ("radeonfb: cannot reserve FB region\n");
|
|
739 kfree (rinfo);
|
|
740 return -ENODEV;
|
|
741 }
|
|
742
|
|
743 if (!request_mem_region (rinfo->mmio_base_phys,
|
|
744 pci_resource_len(pdev, 2), "radeonfb")) {
|
|
745 printk ("radeonfb: cannot reserve MMIO region\n");
|
|
746 release_mem_region (rinfo->fb_base_phys,
|
|
747 pci_resource_len(pdev, 0));
|
|
748 kfree (rinfo);
|
|
749 return -ENODEV;
|
|
750 }
|
|
751
|
|
752 /* map the regions */
|
|
753 rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
|
|
754 RADEON_REGSIZE);
|
|
755 if (!rinfo->mmio_base) {
|
|
756 printk ("radeonfb: cannot map MMIO\n");
|
|
757 release_mem_region (rinfo->mmio_base_phys,
|
|
758 pci_resource_len(pdev, 2));
|
|
759 release_mem_region (rinfo->fb_base_phys,
|
|
760 pci_resource_len(pdev, 0));
|
|
761 kfree (rinfo);
|
|
762 return -ENODEV;
|
|
763 }
|
|
764
|
|
765 /* chipset */
|
|
766 switch (pdev->device) {
|
|
767 case PCI_DEVICE_ID_RADEON_QD:
|
|
768 strcpy(rinfo->name, "Radeon QD ");
|
|
769 break;
|
|
770 case PCI_DEVICE_ID_RADEON_QE:
|
|
771 strcpy(rinfo->name, "Radeon QE ");
|
|
772 break;
|
|
773 case PCI_DEVICE_ID_RADEON_QF:
|
|
774 strcpy(rinfo->name, "Radeon QF ");
|
|
775 break;
|
|
776 case PCI_DEVICE_ID_RADEON_QG:
|
|
777 strcpy(rinfo->name, "Radeon QG ");
|
|
778 break;
|
1913
|
779 case PCI_DEVICE_ID_RADEON_QY:
|
1915
|
780 rinfo->hasCRTC2 = 1;
|
|
781 strcpy(rinfo->name, "Radeon VE QY ");
|
1913
|
782 break;
|
|
783 case PCI_DEVICE_ID_RADEON_QZ:
|
1915
|
784 rinfo->hasCRTC2 = 1;
|
|
785 strcpy(rinfo->name, "Radeon VE QZ ");
|
|
786 break;
|
|
787 case PCI_DEVICE_ID_RADEON_LY:
|
|
788 rinfo->hasCRTC2 = 1;
|
|
789 strcpy(rinfo->name, "Radeon M6 LY ");
|
|
790 break;
|
|
791 case PCI_DEVICE_ID_RADEON_LZ:
|
|
792 rinfo->hasCRTC2 = 1;
|
|
793 strcpy(rinfo->name, "Radeon M6 LZ ");
|
|
794 break;
|
|
795 case PCI_DEVICE_ID_RADEON_LW:
|
|
796 /* Note: Only difference between VE,M6 and M7 is initialization CRTC2
|
|
797 registers in dual monitor configuration!!! */
|
|
798 rinfo->hasCRTC2 = 1;
|
|
799 rinfo->isM7 = 1;
|
|
800 strcpy(rinfo->name, "Radeon M7 LW ");
|
1912
|
801 break;
|
1967
|
802 case PCI_DEVICE_ID_R200_QL:
|
|
803 rinfo->hasCRTC2 = 1;
|
|
804 rinfo->isR200 = 1;
|
1969
|
805 strcpy(rinfo->name, "Radeon2 8500 QL ");
|
1967
|
806 break;
|
|
807 case PCI_DEVICE_ID_RV200_QW:
|
|
808 rinfo->hasCRTC2 = 1;
|
|
809 rinfo->isM7 = 1;
|
|
810 strcpy(rinfo->name, "Radeon2 7500 QW ");
|
|
811 break;
|
1911
|
812 default:
|
1915
|
813 release_mem_region (rinfo->mmio_base_phys,
|
|
814 pci_resource_len(pdev, 2));
|
|
815 release_mem_region (rinfo->fb_base_phys,
|
|
816 pci_resource_len(pdev, 0));
|
|
817 kfree (rinfo);
|
1911
|
818 return -ENODEV;
|
|
819 }
|
|
820
|
|
821 /* framebuffer size */
|
|
822 tmp = INREG(CONFIG_MEMSIZE);
|
|
823
|
|
824 /* mem size is bits [28:0], mask off the rest */
|
|
825 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
|
826
|
|
827 /* ram type */
|
|
828 tmp = INREG(MEM_SDRAM_MODE_REG);
|
|
829 switch ((MEM_CFG_TYPE & tmp) >> 30) {
|
|
830 case 0:
|
|
831 /* SDR SGRAM (2:1) */
|
|
832 strcpy(rinfo->ram_type, "SDR SGRAM");
|
|
833 rinfo->ram.ml = 4;
|
|
834 rinfo->ram.mb = 4;
|
|
835 rinfo->ram.trcd = 1;
|
|
836 rinfo->ram.trp = 2;
|
|
837 rinfo->ram.twr = 1;
|
|
838 rinfo->ram.cl = 2;
|
|
839 rinfo->ram.loop_latency = 16;
|
|
840 rinfo->ram.rloop = 16;
|
|
841
|
|
842 break;
|
|
843 case 1:
|
|
844 /* DDR SGRAM */
|
|
845 strcpy(rinfo->ram_type, "DDR SGRAM");
|
|
846 rinfo->ram.ml = 4;
|
|
847 rinfo->ram.mb = 4;
|
|
848 rinfo->ram.trcd = 3;
|
|
849 rinfo->ram.trp = 3;
|
|
850 rinfo->ram.twr = 2;
|
|
851 rinfo->ram.cl = 3;
|
|
852 rinfo->ram.tr2w = 1;
|
|
853 rinfo->ram.loop_latency = 16;
|
|
854 rinfo->ram.rloop = 16;
|
|
855
|
|
856 break;
|
|
857 default:
|
|
858 /* 64-bit SDR SGRAM */
|
|
859 strcpy(rinfo->ram_type, "SDR SGRAM 64");
|
|
860 rinfo->ram.ml = 4;
|
|
861 rinfo->ram.mb = 8;
|
|
862 rinfo->ram.trcd = 3;
|
|
863 rinfo->ram.trp = 3;
|
|
864 rinfo->ram.twr = 1;
|
|
865 rinfo->ram.cl = 3;
|
|
866 rinfo->ram.tr2w = 1;
|
|
867 rinfo->ram.loop_latency = 17;
|
|
868 rinfo->ram.rloop = 17;
|
|
869
|
|
870 break;
|
|
871 }
|
|
872
|
|
873 bios_seg = radeon_find_rom(rinfo);
|
|
874 radeon_get_pllinfo(rinfo, bios_seg);
|
|
875
|
|
876 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
|
|
877 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
|
|
878
|
|
879 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
|
880
|
1915
|
881 /*****
|
|
882 VE and M6 have both DVI and CRT ports (for M6 DVI port can be switch to
|
|
883 DFP port). The DVI port can also be conneted to a CRT with an adapter.
|
|
884 Here is the definition of ports for this driver---
|
|
885 (1) If both port are connected, DVI port will be treated as the Primary
|
|
886 port (uses CRTC1) and CRT port will be treated as the Secondary port
|
|
887 (uses CRTC2)
|
|
888 (2) If only one port is connected, it will treated as the Primary port
|
|
889 (??? uses CRTC1 ???)
|
|
890 *****/
|
|
891 if(rinfo->hasCRTC2) {
|
|
892 /* Using BIOS scratch registers works with for VE/M6,
|
|
893 no such registers in regular RADEON!!!*/
|
|
894 tmp = INREG(RADEON_BIOS_4_SCRATCH);
|
|
895 /*check Primary (DVI/DFP port)*/
|
|
896 if(tmp & 0x08) rinfo->dviDispType = MT_DFP;
|
|
897 else if(tmp & 0x04) rinfo->dviDispType = MT_LCD;
|
|
898 else if(tmp & 0x0200) rinfo->dviDispType = MT_CRT;
|
|
899 else if(tmp & 0x10) rinfo->dviDispType = MT_CTV;
|
|
900 else if(tmp & 0x20) rinfo->dviDispType = MT_STV;
|
|
901 /*check Secondary (CRT port).*/
|
|
902 if(tmp & 0x02) rinfo->crtDispType = MT_CRT;
|
|
903 else if(tmp & 0x800) rinfo->crtDispType = MT_DFP;
|
|
904 else if(tmp & 0x400) rinfo->crtDispType = MT_LCD;
|
|
905 else if(tmp & 0x1000) rinfo->crtDispType = MT_CTV;
|
|
906 else if(tmp & 0x2000) rinfo->crtDispType = MT_STV;
|
|
907 if(rinfo->dviDispType == MT_NONE &&
|
|
908 rinfo->crtDispType == MT_NONE) {
|
|
909 printk("radeonfb: No monitor detected!!!\n");
|
|
910 release_mem_region (rinfo->mmio_base_phys,
|
|
911 pci_resource_len(pdev, 2));
|
|
912 release_mem_region (rinfo->fb_base_phys,
|
|
913 pci_resource_len(pdev, 0));
|
|
914 kfree (rinfo);
|
|
915 return -ENODEV;
|
|
916 }
|
|
917 }
|
|
918 else {
|
|
919 /*Regular Radeon ASIC, only one CRTC, but it could be
|
|
920 used for DFP with a DVI output, like AIW board*/
|
|
921 rinfo->dviDispType = MT_NONE;
|
|
922 tmp = INREG(FP_GEN_CNTL);
|
|
923 if(tmp & FP_EN_TMDS) rinfo->crtDispType = MT_DFP;
|
|
924 else rinfo->crtDispType = MT_CRT;
|
|
925 }
|
|
926
|
|
927 if(bios_seg) {
|
|
928 /*
|
|
929 FIXME!!! TVout support currently is incomplete
|
|
930 On Radeon VE TVout is recognized as STV monitor on DVI port.
|
|
931 */
|
|
932 char * bios_ptr = bios_seg + 0x48L;
|
|
933 rinfo->hasTVout = readw(bios_ptr+0x32);
|
|
934 }
|
|
935
|
1911
|
936 rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
|
937 rinfo->video_ram);
|
|
938 if (!rinfo->fb_base) {
|
|
939 printk ("radeonfb: cannot map FB\n");
|
|
940 iounmap ((void*)rinfo->mmio_base);
|
|
941 release_mem_region (rinfo->mmio_base_phys,
|
|
942 pci_resource_len(pdev, 2));
|
|
943 release_mem_region (rinfo->fb_base_phys,
|
|
944 pci_resource_len(pdev, 0));
|
|
945 kfree (rinfo);
|
|
946 return -ENODEV;
|
|
947 }
|
|
948
|
|
949 /* XXX turn off accel for now, blts aren't working right */
|
|
950 noaccel = 1;
|
|
951
|
|
952 /* set all the vital stuff */
|
|
953 radeon_set_fbinfo (rinfo);
|
|
954
|
|
955 /* save current mode regs before we switch into the new one
|
|
956 * so we can restore this upon __exit
|
|
957 */
|
|
958 radeon_save_state (rinfo, &rinfo->init_state);
|
|
959
|
|
960 /* init palette */
|
|
961 for (i=0; i<16; i++) {
|
|
962 j = color_table[i];
|
|
963 rinfo->palette[i].red = default_red[j];
|
|
964 rinfo->palette[i].green = default_grn[j];
|
|
965 rinfo->palette[i].blue = default_blu[j];
|
|
966 }
|
|
967
|
|
968 pdev->driver_data = rinfo;
|
|
969
|
|
970 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
|
|
971 printk ("radeonfb: could not register framebuffer\n");
|
|
972 iounmap ((void*)rinfo->fb_base);
|
|
973 iounmap ((void*)rinfo->mmio_base);
|
|
974 release_mem_region (rinfo->mmio_base_phys,
|
|
975 pci_resource_len(pdev, 2));
|
|
976 release_mem_region (rinfo->fb_base_phys,
|
|
977 pci_resource_len(pdev, 0));
|
|
978 kfree (rinfo);
|
|
979 return -ENODEV;
|
|
980 }
|
|
981
|
|
982 if (!noaccel) {
|
|
983 /* initialize the engine */
|
|
984 radeon_engine_init (rinfo);
|
|
985 }
|
|
986
|
1915
|
987 printk ("radeonfb: ATI %s %s %d MB\n",rinfo->name,rinfo->ram_type,
|
1911
|
988 (rinfo->video_ram/(1024*1024)));
|
1915
|
989 if(rinfo->hasCRTC2) {
|
|
990 printk("radeonfb: DVI port has %s monitor connected\n",GET_MON_NAME(rinfo->dviDispType));
|
|
991 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
992 }
|
|
993 else
|
|
994 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
995 printk("radeonfb: This card has %sTVout\n",rinfo->hasTVout ? "" : "no ");
|
1951
|
996 #ifdef CONFIG_MTRR
|
|
997 if (mtrr) {
|
|
998 rinfo->mtrr.vram = mtrr_add(rinfo->fb_base_phys,
|
|
999 rinfo->video_ram, MTRR_TYPE_WRCOMB, 1);
|
|
1000 rinfo->mtrr.vram_valid = 1;
|
|
1001 /* let there be speed */
|
|
1002 printk("radeonfb: MTRR set to ON\n");
|
|
1003 }
|
|
1004 #endif /* CONFIG_MTRR */
|
1911
|
1005
|
|
1006 return 0;
|
|
1007 }
|
|
1008
|
|
1009
|
|
1010
|
|
1011 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
|
|
1012 {
|
|
1013 struct radeonfb_info *rinfo = pdev->driver_data;
|
|
1014
|
|
1015 if (!rinfo)
|
|
1016 return;
|
|
1017
|
|
1018 /* restore original state */
|
|
1019 radeon_write_mode (rinfo, &rinfo->init_state);
|
|
1020
|
|
1021 unregister_framebuffer ((struct fb_info *) rinfo);
|
1951
|
1022 #ifdef CONFIG_MTRR
|
|
1023 if (rinfo->mtrr.vram_valid)
|
|
1024 mtrr_del(rinfo->mtrr.vram, rinfo->fb_base_phys,
|
|
1025 rinfo->video_ram);
|
|
1026 #endif /* CONFIG_MTRR */
|
1911
|
1027 iounmap ((void*)rinfo->mmio_base);
|
|
1028 iounmap ((void*)rinfo->fb_base);
|
|
1029
|
|
1030 release_mem_region (rinfo->mmio_base_phys,
|
|
1031 pci_resource_len(pdev, 2));
|
|
1032 release_mem_region (rinfo->fb_base_phys,
|
|
1033 pci_resource_len(pdev, 0));
|
|
1034
|
|
1035 kfree (rinfo);
|
|
1036 }
|
|
1037
|
|
1038
|
|
1039
|
|
1040 static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
|
1041 {
|
1914
|
1042 #if defined(__i386__)
|
1911
|
1043 u32 segstart;
|
|
1044 char *rom_base;
|
|
1045 char *rom;
|
|
1046 int stage;
|
1915
|
1047 int i,j;
|
1911
|
1048 char aty_rom_sig[] = "761295520";
|
1915
|
1049 char *radeon_sig[] = {
|
|
1050 "RG6",
|
|
1051 "RADEON"
|
|
1052 };
|
1911
|
1053
|
|
1054 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
|
1055 stage = 1;
|
|
1056
|
|
1057 rom_base = (char *)ioremap(segstart, 0x1000);
|
|
1058
|
|
1059 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
|
|
1060 stage = 2;
|
|
1061
|
|
1062
|
|
1063 if (stage != 2) {
|
|
1064 iounmap(rom_base);
|
|
1065 continue;
|
|
1066 }
|
|
1067
|
|
1068 rom = rom_base;
|
|
1069
|
|
1070 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
|
|
1071 if (aty_rom_sig[0] == *rom)
|
|
1072 if (strncmp(aty_rom_sig, rom,
|
|
1073 strlen(aty_rom_sig)) == 0)
|
|
1074 stage = 3;
|
|
1075 rom++;
|
|
1076 }
|
|
1077 if (stage != 3) {
|
|
1078 iounmap(rom_base);
|
|
1079 continue;
|
|
1080 }
|
|
1081 rom = rom_base;
|
|
1082
|
|
1083 for (i = 0; (i < 512) && (stage != 4); i++) {
|
1915
|
1084 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
|
|
1085 if (radeon_sig[j][0] == *rom)
|
|
1086 if (strncmp(radeon_sig[j], rom,
|
|
1087 strlen(radeon_sig[j])) == 0) {
|
|
1088 stage = 4;
|
|
1089 break;
|
|
1090 }
|
|
1091 }
|
1911
|
1092 rom++;
|
|
1093 }
|
|
1094 if (stage != 4) {
|
|
1095 iounmap(rom_base);
|
|
1096 continue;
|
|
1097 }
|
|
1098
|
|
1099 return rom_base;
|
|
1100 }
|
|
1101 #endif
|
|
1102 return NULL;
|
|
1103 }
|
|
1104
|
|
1105
|
|
1106
|
|
1107 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
|
|
1108 {
|
|
1109 void *bios_header;
|
|
1110 void *header_ptr;
|
|
1111 u16 bios_header_offset, pll_info_offset;
|
|
1112 PLL_BLOCK pll;
|
|
1113
|
|
1114 if (bios_seg) {
|
|
1115 bios_header = bios_seg + 0x48L;
|
|
1116 header_ptr = bios_header;
|
|
1117
|
|
1118 bios_header_offset = readw(header_ptr);
|
|
1119 bios_header = bios_seg + bios_header_offset;
|
|
1120 bios_header += 0x30;
|
|
1121
|
|
1122 header_ptr = bios_header;
|
|
1123 pll_info_offset = readw(header_ptr);
|
|
1124 header_ptr = bios_seg + pll_info_offset;
|
|
1125
|
|
1126 memcpy_fromio(&pll, header_ptr, 50);
|
|
1127
|
|
1128 rinfo->pll.xclk = (u32)pll.XCLK;
|
|
1129 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
|
|
1130 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
|
|
1131 rinfo->pll.ppll_min = pll.PCLK_min_freq;
|
|
1132 rinfo->pll.ppll_max = pll.PCLK_max_freq;
|
|
1133 } else {
|
|
1134 /* no BIOS or BIOS not found, use defaults */
|
|
1135
|
|
1136 rinfo->pll.ppll_max = 35000;
|
|
1137 rinfo->pll.ppll_min = 12000;
|
|
1138 rinfo->pll.xclk = 16600;
|
|
1139 rinfo->pll.ref_div = 67;
|
|
1140 rinfo->pll.ref_clk = 2700;
|
|
1141 }
|
|
1142 }
|
|
1143
|
|
1144 static void radeon_engine_init (struct radeonfb_info *rinfo)
|
|
1145 {
|
|
1146 u32 temp;
|
|
1147
|
|
1148 /* disable 3D engine */
|
|
1149 OUTREG(RB3D_CNTL, 0);
|
|
1150
|
|
1151 radeon_engine_reset ();
|
|
1152
|
|
1153 radeon_fifo_wait (1);
|
|
1154 OUTREG(DSTCACHE_MODE, 0);
|
|
1155
|
|
1156 /* XXX */
|
|
1157 rinfo->pitch = ((rinfo->xres * (rinfo->depth / 8) + 0x3f)) >> 6;
|
|
1158
|
|
1159 radeon_fifo_wait (1);
|
|
1160 temp = INREG(DEFAULT_PITCH_OFFSET);
|
|
1161 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
|
|
1162 (rinfo->pitch << 0x16)));
|
|
1163
|
|
1164 radeon_fifo_wait (1);
|
|
1165 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
1166
|
|
1167 radeon_fifo_wait (1);
|
|
1168 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
|
|
1169 DEFAULT_SC_BOTTOM_MAX));
|
|
1170
|
|
1171 temp = radeon_get_dstbpp(rinfo->depth);
|
|
1172 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
|
|
1173 radeon_fifo_wait (1);
|
|
1174 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
1175 GMC_BRUSH_SOLID_COLOR |
|
|
1176 GMC_SRC_DATATYPE_COLOR));
|
|
1177
|
|
1178 radeon_fifo_wait (7);
|
|
1179
|
|
1180 /* clear line drawing regs */
|
|
1181 OUTREG(DST_LINE_START, 0);
|
|
1182 OUTREG(DST_LINE_END, 0);
|
|
1183
|
|
1184 /* set brush color regs */
|
|
1185 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
1186 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
1187
|
|
1188 /* set source color regs */
|
|
1189 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
1190 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
1191
|
|
1192 /* default write mask */
|
|
1193 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
1194
|
|
1195 radeon_engine_idle ();
|
|
1196 }
|
|
1197
|
|
1198
|
|
1199
|
|
1200 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
|
|
1201 {
|
|
1202 struct fb_info *info;
|
|
1203
|
|
1204 info = &rinfo->info;
|
|
1205
|
|
1206 strcpy (info->modename, rinfo->name);
|
|
1207 info->node = -1;
|
|
1208 info->flags = FBINFO_FLAG_DEFAULT;
|
|
1209 info->fbops = &radeon_fb_ops;
|
|
1210 info->display_fg = NULL;
|
|
1211 strncpy (info->fontname, fontname, sizeof (info->fontname));
|
|
1212 info->fontname[sizeof (info->fontname) - 1] = 0;
|
|
1213 info->changevar = NULL;
|
|
1214 info->switch_con = radeonfb_switch;
|
|
1215 info->updatevar = radeonfb_updatevar;
|
|
1216 info->blank = radeonfb_blank;
|
|
1217
|
|
1218 if (radeon_init_disp (rinfo) < 0)
|
|
1219 return -1;
|
|
1220
|
|
1221 return 0;
|
|
1222 }
|
|
1223
|
|
1224
|
|
1225
|
|
1226 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
|
|
1227 {
|
|
1228 struct fb_info *info;
|
|
1229 struct display *disp;
|
|
1230
|
|
1231 info = &rinfo->info;
|
|
1232 disp = &rinfo->disp;
|
|
1233
|
|
1234 disp->var = radeonfb_default_var;
|
|
1235 info->disp = disp;
|
|
1236
|
1914
|
1237 radeon_set_dispsw (rinfo, disp);
|
1911
|
1238
|
|
1239 if (noaccel)
|
|
1240 disp->scrollmode = SCROLL_YREDRAW;
|
|
1241 else
|
|
1242 disp->scrollmode = 0;
|
|
1243
|
|
1244 rinfo->currcon_display = disp;
|
|
1245
|
|
1246 if ((radeon_init_disp_var (rinfo)) < 0)
|
|
1247 return -1;
|
|
1248
|
|
1249 return 0;
|
|
1250 }
|
|
1251
|
|
1252
|
|
1253
|
|
1254 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
|
|
1255 {
|
|
1256 #ifndef MODULE
|
|
1257 if (mode_option)
|
|
1258 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
|
|
1259 NULL, 0, NULL, 8);
|
|
1260 else
|
|
1261 #endif
|
|
1262 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
|
|
1263 NULL, 0, NULL, 0);
|
|
1264
|
|
1265 if (noaccel)
|
|
1266 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
|
|
1267 else
|
|
1268 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
|
|
1269
|
|
1270 return 0;
|
|
1271 }
|
|
1272
|
|
1273
|
1914
|
1274 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
|
1911
|
1275 {
|
|
1276 int accel;
|
|
1277
|
|
1278 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
|
|
1279
|
|
1280 disp->dispsw_data = NULL;
|
|
1281
|
|
1282 disp->screen_base = (char*)rinfo->fb_base;
|
|
1283 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
1284 disp->type_aux = 0;
|
|
1285 disp->ypanstep = 1;
|
|
1286 disp->ywrapstep = 0;
|
|
1287 disp->can_soft_blank = 1;
|
|
1288 disp->inverse = 0;
|
|
1289
|
|
1290 rinfo->depth = disp->var.bits_per_pixel;
|
|
1291 switch (disp->var.bits_per_pixel) {
|
|
1292 #ifdef FBCON_HAS_CFB8
|
|
1293 case 8:
|
1914
|
1294 disp->dispsw = &fbcon_cfb8;
|
1911
|
1295 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1296 disp->line_length = disp->var.xres_virtual;
|
|
1297 break;
|
|
1298 #endif
|
|
1299 #ifdef FBCON_HAS_CFB16
|
|
1300 case 16:
|
|
1301 disp->dispsw = &fbcon_cfb16;
|
|
1302 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
1303 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1304 disp->line_length = disp->var.xres_virtual * 2;
|
|
1305 break;
|
|
1306 #endif
|
|
1307 #ifdef FBCON_HAS_CFB32
|
1914
|
1308 case 24:
|
|
1309 disp->dispsw = &fbcon_cfb24;
|
|
1310 disp->dispsw_data = &rinfo->con_cmap.cfb24;
|
|
1311 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1312 disp->line_length = disp->var.xres_virtual * 4;
|
|
1313 break;
|
|
1314 #endif
|
|
1315 #ifdef FBCON_HAS_CFB32
|
1911
|
1316 case 32:
|
|
1317 disp->dispsw = &fbcon_cfb32;
|
|
1318 disp->dispsw_data = &rinfo->con_cmap.cfb32;
|
|
1319 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1320 disp->line_length = disp->var.xres_virtual * 4;
|
|
1321 break;
|
|
1322 #endif
|
|
1323 default:
|
|
1324 printk ("radeonfb: setting fbcon_dummy renderer\n");
|
|
1325 disp->dispsw = &fbcon_dummy;
|
|
1326 }
|
|
1327
|
|
1328 return;
|
|
1329 }
|
|
1330
|
|
1331
|
|
1332
|
|
1333 /*
|
|
1334 * fb ops
|
|
1335 */
|
|
1336
|
|
1337 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
1338 struct fb_info *info)
|
|
1339 {
|
|
1340 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1341 struct display *disp;
|
|
1342
|
|
1343 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1344
|
|
1345 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
|
|
1346 strcpy (fix->id, rinfo->name);
|
|
1347
|
|
1348 fix->smem_start = rinfo->fb_base_phys;
|
|
1349 fix->smem_len = rinfo->video_ram;
|
|
1350
|
|
1351 fix->type = disp->type;
|
|
1352 fix->type_aux = disp->type_aux;
|
|
1353 fix->visual = disp->visual;
|
|
1354
|
|
1355 fix->xpanstep = 1;
|
|
1356 fix->ypanstep = 1;
|
|
1357 fix->ywrapstep = 0;
|
|
1358
|
|
1359 fix->line_length = disp->line_length;
|
|
1360
|
|
1361 fix->mmio_start = rinfo->mmio_base_phys;
|
|
1362 fix->mmio_len = RADEON_REGSIZE;
|
|
1363 if (noaccel)
|
|
1364 fix->accel = FB_ACCEL_NONE;
|
|
1365 else
|
|
1366 fix->accel = 40; /* XXX */
|
|
1367
|
|
1368 return 0;
|
|
1369 }
|
|
1370
|
|
1371
|
|
1372
|
|
1373 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
1374 struct fb_info *info)
|
|
1375 {
|
|
1376 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1377
|
|
1378 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
|
|
1379
|
|
1380 return 0;
|
|
1381 }
|
|
1382
|
|
1383
|
|
1384
|
|
1385 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
1386 struct fb_info *info)
|
|
1387 {
|
|
1388 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1389 struct display *disp;
|
|
1390 struct fb_var_screeninfo v;
|
1914
|
1391 int nom, den, accel;
|
1911
|
1392 unsigned chgvar = 0;
|
|
1393
|
|
1394 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1395
|
|
1396 accel = var->accel_flags & FB_ACCELF_TEXT;
|
|
1397
|
|
1398 if (con >= 0) {
|
|
1399 chgvar = ((disp->var.xres != var->xres) ||
|
|
1400 (disp->var.yres != var->yres) ||
|
|
1401 (disp->var.xres_virtual != var->xres_virtual) ||
|
|
1402 (disp->var.yres_virtual != var->yres_virtual) ||
|
1914
|
1403 (disp->var.bits_per_pixel != var->bits_per_pixel) ||
|
1911
|
1404 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
|
|
1405 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
|
|
1406 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
|
|
1407 }
|
|
1408
|
|
1409 memcpy (&v, var, sizeof (v));
|
|
1410
|
|
1411 switch (v.bits_per_pixel) {
|
|
1412 #ifdef FBCON_HAS_CFB8
|
|
1413 case 8:
|
|
1414 nom = den = 1;
|
|
1415 disp->line_length = v.xres_virtual;
|
|
1416 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
1417 v.red.offset = v.green.offset = v.blue.offset = 0;
|
|
1418 v.red.length = v.green.length = v.blue.length = 8;
|
1914
|
1419 v.transp.offset = v.transp.length = 0;
|
1911
|
1420 break;
|
|
1421 #endif
|
|
1422
|
|
1423 #ifdef FBCON_HAS_CFB16
|
|
1424 case 16:
|
|
1425 nom = 2;
|
|
1426 den = 1;
|
|
1427 disp->line_length = v.xres_virtual * 2;
|
|
1428 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1429 v.red.offset = 11;
|
|
1430 v.green.offset = 5;
|
|
1431 v.blue.offset = 0;
|
|
1432 v.red.length = 5;
|
|
1433 v.green.length = 6;
|
|
1434 v.blue.length = 5;
|
1914
|
1435 v.transp.offset = v.transp.length = 0;
|
1911
|
1436 break;
|
|
1437 #endif
|
|
1438
|
1914
|
1439 #ifdef FBCON_HAS_CFB24
|
|
1440 case 24:
|
|
1441 nom = 4;
|
|
1442 den = 1;
|
|
1443 disp->line_length = v.xres_virtual * 3;
|
|
1444 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1445 v.red.offset = 16;
|
|
1446 v.green.offset = 8;
|
|
1447 v.blue.offset = 0;
|
|
1448 v.red.length = v.blue.length = v.green.length = 8;
|
|
1449 v.transp.offset = v.transp.length = 0;
|
|
1450 break;
|
|
1451 #endif
|
1911
|
1452 #ifdef FBCON_HAS_CFB32
|
|
1453 case 32:
|
|
1454 nom = 4;
|
|
1455 den = 1;
|
|
1456 disp->line_length = v.xres_virtual * 4;
|
|
1457 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
1458 v.red.offset = 16;
|
|
1459 v.green.offset = 8;
|
|
1460 v.blue.offset = 0;
|
|
1461 v.red.length = v.blue.length = v.green.length = 8;
|
1914
|
1462 v.transp.offset = 24;
|
|
1463 v.transp.length = 8;
|
1911
|
1464 break;
|
|
1465 #endif
|
|
1466 default:
|
|
1467 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
|
|
1468 var->xres, var->yres, var->bits_per_pixel);
|
|
1469 return -EINVAL;
|
|
1470 }
|
|
1471
|
1914
|
1472 if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
|
|
1473 return -EINVAL;
|
1911
|
1474
|
|
1475 if (v.xoffset < 0)
|
|
1476 v.xoffset = 0;
|
|
1477 if (v.yoffset < 0)
|
|
1478 v.yoffset = 0;
|
|
1479
|
|
1480 if (v.xoffset > v.xres_virtual - v.xres)
|
|
1481 v.xoffset = v.xres_virtual - v.xres - 1;
|
|
1482
|
|
1483 if (v.yoffset > v.yres_virtual - v.yres)
|
|
1484 v.yoffset = v.yres_virtual - v.yres - 1;
|
|
1485
|
|
1486 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
|
|
1487 v.transp.offset = v.transp.length =
|
|
1488 v.transp.msb_right = 0;
|
|
1489
|
|
1490 switch (v.activate & FB_ACTIVATE_MASK) {
|
|
1491 case FB_ACTIVATE_TEST:
|
|
1492 return 0;
|
|
1493 case FB_ACTIVATE_NXTOPEN:
|
|
1494 case FB_ACTIVATE_NOW:
|
|
1495 break;
|
|
1496 default:
|
|
1497 return -EINVAL;
|
|
1498 }
|
|
1499
|
|
1500 memcpy (&disp->var, &v, sizeof (v));
|
|
1501
|
1914
|
1502 if (chgvar) {
|
|
1503 radeon_set_dispsw(rinfo, disp);
|
|
1504
|
|
1505 if (noaccel)
|
|
1506 disp->scrollmode = SCROLL_YREDRAW;
|
|
1507 else
|
|
1508 disp->scrollmode = 0;
|
|
1509
|
|
1510 if (info && info->changevar)
|
|
1511 info->changevar(con);
|
|
1512 }
|
|
1513
|
1911
|
1514 radeon_load_video_mode (rinfo, &v);
|
|
1515
|
1914
|
1516 do_install_cmap(con, info);
|
|
1517
|
1911
|
1518 return 0;
|
|
1519 }
|
|
1520
|
|
1521
|
|
1522
|
|
1523 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1524 struct fb_info *info)
|
|
1525 {
|
|
1526 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1527 struct display *disp;
|
|
1528
|
|
1529 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1530
|
|
1531 if (con == rinfo->currcon) {
|
|
1532 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
|
|
1533 return rc;
|
|
1534 } else if (disp->cmap.len)
|
|
1535 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
|
|
1536 else
|
|
1537 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
|
|
1538 cmap, kspc ? 0 : 2);
|
|
1539
|
|
1540 return 0;
|
|
1541 }
|
|
1542
|
|
1543
|
|
1544
|
|
1545 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
1546 struct fb_info *info)
|
|
1547 {
|
|
1548 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1549 struct display *disp;
|
|
1550 unsigned int cmap_len;
|
|
1551
|
|
1552 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1553
|
|
1554 cmap_len = radeon_get_cmap_len (&disp->var);
|
|
1555 if (disp->cmap.len != cmap_len) {
|
|
1556 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
|
|
1557 if (err)
|
|
1558 return err;
|
|
1559 }
|
|
1560
|
|
1561 if (con == rinfo->currcon) {
|
|
1562 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
|
|
1563 return rc;
|
|
1564 } else
|
|
1565 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
|
|
1566
|
|
1567 return 0;
|
|
1568 }
|
|
1569
|
|
1570
|
|
1571
|
|
1572 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
1573 struct fb_info *info)
|
|
1574 {
|
|
1575 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1576 u32 offset, xoffset, yoffset;
|
|
1577
|
|
1578 xoffset = (var->xoffset + 7) & ~7;
|
|
1579 yoffset = var->yoffset;
|
1911
|
1580
|
1914
|
1581 if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
|
|
1582 var->yres_virtual))
|
|
1583 return -EINVAL;
|
1911
|
1584
|
1914
|
1585 offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
|
|
1586
|
|
1587 OUTREG(CRTC_OFFSET, offset);
|
1911
|
1588
|
|
1589 return 0;
|
|
1590 }
|
|
1591
|
|
1592
|
1914
|
1593 static void do_install_cmap(int con, struct fb_info *info)
|
|
1594 {
|
|
1595 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1596
|
|
1597 if (con != rinfo->currcon)
|
|
1598 return;
|
|
1599
|
|
1600 if (fb_display[con].cmap.len)
|
|
1601 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
|
|
1602 else {
|
|
1603 int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
|
|
1604 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
|
|
1605 }
|
|
1606 }
|
|
1607
|
|
1608
|
|
1609 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
1610 struct fb_var_screeninfo *var,
|
|
1611 struct fb_var_screeninfo *v,
|
|
1612 int nom, int den)
|
|
1613 {
|
|
1614 static struct {
|
|
1615 int xres, yres;
|
|
1616 } modes[] = {
|
|
1617 {1600, 1280},
|
|
1618 {1280, 1024},
|
|
1619 {1024, 768},
|
|
1620 {800, 600},
|
|
1621 {640, 480},
|
|
1622 {-1, -1}
|
|
1623 };
|
|
1624 int i;
|
|
1625
|
|
1626 /* use highest possible virtual resolution */
|
|
1627 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
|
|
1628 printk("radeonfb: using max availabe virtual resolution\n");
|
|
1629 for (i=0; modes[i].xres != -1; i++) {
|
|
1630 if (modes[i].xres * nom / den * modes[i].yres <
|
|
1631 rinfo->video_ram / 2)
|
|
1632 break;
|
|
1633 }
|
|
1634 if (modes[i].xres == -1) {
|
|
1635 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
|
|
1636 return -EINVAL;
|
|
1637 }
|
|
1638 v->xres_virtual = modes[i].xres;
|
|
1639 v->yres_virtual = modes[i].yres;
|
|
1640
|
|
1641 printk("radeonfb: virtual resolution set to max of %dx%d\n",
|
|
1642 v->xres_virtual, v->yres_virtual);
|
|
1643 } else if (v->xres_virtual == -1) {
|
|
1644 v->xres_virtual = (rinfo->video_ram * den /
|
|
1645 (nom * v->yres_virtual * 2)) & ~15;
|
|
1646 } else if (v->yres_virtual == -1) {
|
|
1647 v->xres_virtual = (v->xres_virtual + 15) & ~15;
|
|
1648 v->yres_virtual = rinfo->video_ram * den /
|
|
1649 (nom * v->xres_virtual *2);
|
|
1650 } else {
|
|
1651 if (v->xres_virtual * nom / den * v->yres_virtual >
|
|
1652 rinfo->video_ram) {
|
|
1653 return -EINVAL;
|
|
1654 }
|
|
1655 }
|
|
1656
|
|
1657 if (v->xres_virtual * nom / den >= 8192) {
|
|
1658 v->xres_virtual = 8192 * den / nom - 16;
|
|
1659 }
|
|
1660
|
|
1661 if (v->xres_virtual < v->xres)
|
|
1662 return -EINVAL;
|
|
1663
|
|
1664 if (v->yres_virtual < v->yres)
|
|
1665 return -EINVAL;
|
|
1666
|
|
1667 return 0;
|
|
1668 }
|
|
1669
|
1911
|
1670
|
|
1671 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
1672 unsigned long arg, int con, struct fb_info *info)
|
|
1673 {
|
|
1674 return -EINVAL;
|
|
1675 }
|
|
1676
|
|
1677
|
|
1678
|
|
1679 static int radeonfb_switch (int con, struct fb_info *info)
|
|
1680 {
|
|
1681 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1682 struct display *disp;
|
|
1683 struct fb_cmap *cmap;
|
|
1684 int switchcon = 0;
|
1914
|
1685
|
1911
|
1686 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
1687
|
|
1688 if (rinfo->currcon >= 0) {
|
|
1689 cmap = &(rinfo->currcon_display->cmap);
|
|
1690 if (cmap->len)
|
|
1691 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
|
|
1692 }
|
|
1693
|
|
1694 if ((disp->var.xres != rinfo->xres) ||
|
|
1695 (disp->var.yres != rinfo->yres) ||
|
|
1696 (disp->var.pixclock != rinfo->pixclock) ||
|
|
1697 (disp->var.bits_per_pixel != rinfo->depth))
|
|
1698 switchcon = 1;
|
|
1699
|
|
1700 if (switchcon) {
|
|
1701 rinfo->currcon = con;
|
|
1702 rinfo->currcon_display = disp;
|
|
1703 disp->var.activate = FB_ACTIVATE_NOW;
|
|
1704
|
|
1705 radeonfb_set_var (&disp->var, con, info);
|
1914
|
1706 radeon_set_dispsw (rinfo, disp);
|
|
1707 do_install_cmap(con, info);
|
1911
|
1708 }
|
1914
|
1709
|
|
1710 /* XXX absurd hack for X to restore console */
|
|
1711 {
|
|
1712 OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
|
1713 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
|
1714 }
|
|
1715
|
1911
|
1716 return 0;
|
|
1717 }
|
|
1718
|
|
1719
|
|
1720
|
|
1721 static int radeonfb_updatevar (int con, struct fb_info *info)
|
|
1722 {
|
|
1723 int rc;
|
|
1724
|
|
1725 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
|
|
1726 con, info);
|
|
1727
|
|
1728 return rc;
|
|
1729 }
|
|
1730
|
|
1731 static void radeonfb_blank (int blank, struct fb_info *info)
|
|
1732 {
|
|
1733 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1734 u32 val = INREG(CRTC_EXT_CNTL);
|
|
1735
|
|
1736 /* reset it */
|
|
1737 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
|
|
1738 CRTC_VSYNC_DIS);
|
1911
|
1739
|
|
1740 switch (blank) {
|
1914
|
1741 case VESA_NO_BLANKING:
|
|
1742 break;
|
|
1743 case VESA_VSYNC_SUSPEND:
|
|
1744 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
|
1911
|
1745 break;
|
1914
|
1746 case VESA_HSYNC_SUSPEND:
|
|
1747 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
|
1911
|
1748 break;
|
1914
|
1749 case VESA_POWERDOWN:
|
|
1750 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
|
|
1751 CRTC_HSYNC_DIS);
|
1911
|
1752 break;
|
|
1753 }
|
1915
|
1754 if(blank == VESA_NO_BLANKING && rinfo->hasCRTC2)
|
|
1755 OUTREGP(CRTC_EXT_CNTL,CRTC_CRT_ON, val);
|
|
1756 else OUTREG(CRTC_EXT_CNTL, val);
|
1911
|
1757 }
|
|
1758
|
|
1759
|
|
1760
|
|
1761 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
|
|
1762 {
|
|
1763 int rc = 16; /* reasonable default */
|
|
1764
|
|
1765 switch (var->bits_per_pixel) {
|
|
1766 case 8:
|
|
1767 rc = 256;
|
|
1768 break;
|
|
1769 case 16:
|
|
1770 rc = 64;
|
|
1771 break;
|
|
1772 default:
|
|
1773 rc = 32;
|
|
1774 break;
|
|
1775 }
|
|
1776
|
|
1777 return rc;
|
|
1778 }
|
|
1779
|
|
1780
|
|
1781
|
|
1782 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
1783 unsigned *blue, unsigned *transp,
|
|
1784 struct fb_info *info)
|
|
1785 {
|
|
1786 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
1787
|
|
1788 if (regno > 255)
|
|
1789 return 1;
|
|
1790
|
|
1791 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
|
|
1792 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
|
|
1793 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
|
|
1794 *transp = 0;
|
|
1795
|
|
1796 return 0;
|
|
1797 }
|
|
1798
|
|
1799
|
|
1800
|
|
1801 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
1802 unsigned blue, unsigned transp, struct fb_info *info)
|
|
1803 {
|
|
1804 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
1805 u32 pindex;
|
1911
|
1806
|
|
1807 if (regno > 255)
|
|
1808 return 1;
|
|
1809
|
|
1810 red >>= 8;
|
|
1811 green >>= 8;
|
|
1812 blue >>= 8;
|
|
1813 rinfo->palette[regno].red = red;
|
|
1814 rinfo->palette[regno].green = green;
|
|
1815 rinfo->palette[regno].blue = blue;
|
|
1816
|
|
1817 /* init gamma for hicolor */
|
|
1818 if ((rinfo->depth > 8) && (regno == 0)) {
|
|
1819 int i;
|
|
1820
|
|
1821 for (i=0; i<255; i++) {
|
|
1822 OUTREG(PALETTE_INDEX, i);
|
1914
|
1823 OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
|
1911
|
1824 }
|
|
1825 }
|
|
1826
|
|
1827 /* default */
|
|
1828 pindex = regno;
|
1914
|
1829
|
|
1830 /* XXX actually bpp, fixme */
|
|
1831 if (rinfo->depth == 16)
|
|
1832 pindex = regno * 8;
|
|
1833
|
|
1834 if (rinfo->depth == 16) {
|
|
1835 OUTREG(PALETTE_INDEX, pindex/2);
|
|
1836 OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
|
|
1837 (green << 8) | (rinfo->palette[regno/2].blue));
|
|
1838 green = rinfo->palette[regno/2].green;
|
|
1839 }
|
|
1840
|
|
1841 if ((rinfo->depth == 8) || (regno < 32)) {
|
|
1842 OUTREG(PALETTE_INDEX, pindex);
|
|
1843 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
|
|
1844 }
|
|
1845
|
|
1846 #if 0
|
1911
|
1847 col = (red << 16) | (green << 8) | blue;
|
|
1848
|
|
1849 if (rinfo->depth == 16) {
|
|
1850 pindex = regno << 3;
|
|
1851
|
|
1852 if ((rinfo->depth == 16) && (regno >= 32)) {
|
|
1853 pindex -= 252;
|
|
1854
|
|
1855 col = (rinfo->palette[regno >> 1].red << 16) |
|
|
1856 (green << 8) |
|
|
1857 (rinfo->palette[regno >> 1].blue);
|
|
1858 } else {
|
|
1859 col = (red << 16) | (green << 8) | blue;
|
|
1860 }
|
|
1861 }
|
|
1862
|
|
1863 OUTREG8(PALETTE_INDEX, pindex);
|
|
1864 radeon_fifo_wait(32);
|
|
1865 OUTREG(PALETTE_DATA, col);
|
1914
|
1866 #endif
|
1911
|
1867
|
|
1868 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
1869 if (regno < 32) {
|
|
1870 switch (rinfo->depth) {
|
|
1871 #ifdef FBCON_HAS_CFB16
|
|
1872 case 16:
|
1914
|
1873 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
|
1911
|
1874 regno;
|
|
1875 break;
|
|
1876 #endif
|
1914
|
1877 #ifdef FBCON_HAS_CFB24
|
|
1878 case 24:
|
|
1879 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
|
|
1880 break;
|
|
1881 #endif
|
1911
|
1882 #ifdef FBCON_HAS_CFB32
|
|
1883 case 32: {
|
|
1884 u32 i;
|
|
1885
|
|
1886 i = (regno << 8) | regno;
|
|
1887 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
|
|
1888 break;
|
|
1889 }
|
|
1890 #endif
|
|
1891 }
|
|
1892 }
|
|
1893 #endif
|
|
1894 return 0;
|
|
1895 }
|
|
1896
|
|
1897
|
|
1898
|
|
1899 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
1900 struct radeon_regs *save)
|
|
1901 {
|
|
1902 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
|
|
1903 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
|
|
1904 save->dac_cntl = INREG(DAC_CNTL);
|
|
1905 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
|
|
1906 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
|
|
1907 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
|
|
1908 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
|
|
1909 save->crtc_pitch = INREG(CRTC_PITCH);
|
|
1910 }
|
|
1911
|
|
1912
|
|
1913
|
|
1914 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
|
|
1915 struct fb_var_screeninfo *mode)
|
|
1916 {
|
|
1917 struct radeon_regs newmode;
|
|
1918 int hTotal, vTotal, hSyncStart, hSyncEnd,
|
|
1919 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
|
|
1920 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
|
|
1921 u32 dotClock = 1000000000 / mode->pixclock,
|
|
1922 sync, h_sync_pol, v_sync_pol;
|
|
1923 int freq = dotClock / 10; /* x 100 */
|
|
1924 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
|
|
1925 int useable_precision, roff, ron;
|
|
1926 int min_bits, format = 0;
|
|
1927 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
|
|
1928
|
|
1929 rinfo->xres = mode->xres;
|
|
1930 rinfo->yres = mode->yres;
|
|
1931 rinfo->pixclock = mode->pixclock;
|
|
1932
|
|
1933 hSyncStart = mode->xres + mode->right_margin;
|
|
1934 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1935 hTotal = hSyncEnd + mode->left_margin;
|
|
1936
|
|
1937 vSyncStart = mode->yres + mode->lower_margin;
|
|
1938 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1939 vTotal = vSyncEnd + mode->upper_margin;
|
|
1940
|
|
1941 sync = mode->sync;
|
|
1942 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1943 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
|
1944
|
|
1945 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
|
|
1946 hSyncStart, hSyncEnd, hTotal);
|
|
1947 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
|
|
1948 vSyncStart, vSyncEnd, vTotal);
|
|
1949
|
|
1950 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1951 vsync_wid = vSyncEnd - vSyncStart;
|
|
1952 if (hsync_wid == 0)
|
|
1953 hsync_wid = 1;
|
|
1954 else if (hsync_wid > 0x3f) /* max */
|
|
1955 hsync_wid = 0x3f;
|
1914
|
1956 vsync_wid = mode->vsync_len;
|
1911
|
1957 if (vsync_wid == 0)
|
|
1958 vsync_wid = 1;
|
|
1959 else if (vsync_wid > 0x1f) /* max */
|
|
1960 vsync_wid = 0x1f;
|
|
1961
|
1914
|
1962 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1963 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
1911
|
1964
|
|
1965 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
|
1966
|
|
1967 switch (mode->bits_per_pixel) {
|
|
1968 case 8:
|
|
1969 format = DST_8BPP;
|
|
1970 bytpp = 1;
|
|
1971 break;
|
|
1972 case 16:
|
|
1973 format = DST_16BPP;
|
|
1974 bytpp = 2;
|
|
1975 break;
|
|
1976 case 24:
|
|
1977 format = DST_24BPP;
|
|
1978 bytpp = 3;
|
|
1979 break;
|
|
1980 case 32:
|
|
1981 format = DST_32BPP;
|
|
1982 bytpp = 4;
|
|
1983 break;
|
|
1984 }
|
|
1985
|
|
1986 hsync_fudge = hsync_adj_tab[format-1];
|
|
1987 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1988
|
|
1989 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
|
|
1990 (format << 8);
|
1915
|
1991 if(rinfo->hasCRTC2)
|
|
1992 /* HACKED: !!! Enable CRT port here !!! */
|
|
1993 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
|
|
1994 else newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
|
1911
|
1995 newmode.dac_cntl = INREG(DAC_CNTL) | DAC_MASK_ALL | DAC_VGA_ADR_EN |
|
|
1996 DAC_8BIT_EN;
|
|
1997
|
1951
|
1998 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
|
|
1999 ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
1911
|
2000
|
|
2001 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
|
1914
|
2002 (hsync_wid << 16) | (h_sync_pol << 23));
|
1911
|
2003
|
|
2004 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
|
2005 ((mode->yres - 1) << 16);
|
|
2006
|
|
2007 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
|
1914
|
2008 (vsync_wid << 16) | (v_sync_pol << 23));
|
1911
|
2009
|
|
2010 newmode.crtc_pitch = (mode->xres >> 3);
|
|
2011
|
1915
|
2012 #if defined(__BIG_ENDIAN)
|
1914
|
2013 newmode.surface_cntl = SURF_TRANSLATION_DIS;
|
|
2014 switch (mode->bits_per_pixel) {
|
|
2015 case 16:
|
|
2016 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
|
2017 break;
|
|
2018 case 24:
|
|
2019 case 32:
|
|
2020 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
|
|
2021 break;
|
|
2022 }
|
|
2023 #endif
|
|
2024
|
1911
|
2025 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
|
2026 & ~(0x3f)) / 64;
|
|
2027
|
|
2028 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
|
|
2029 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
|
|
2030 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
|
|
2031 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
|
|
2032
|
|
2033 newmode.xres = mode->xres;
|
|
2034 newmode.yres = mode->yres;
|
|
2035
|
|
2036 rinfo->bpp = mode->bits_per_pixel;
|
1914
|
2037 rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
|
|
2038 rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
|
1911
|
2039
|
|
2040 if (freq > rinfo->pll.ppll_max)
|
|
2041 freq = rinfo->pll.ppll_max;
|
|
2042 if (freq*12 < rinfo->pll.ppll_min)
|
|
2043 freq = rinfo->pll.ppll_min / 12;
|
|
2044
|
|
2045 {
|
|
2046 struct {
|
|
2047 int divider;
|
|
2048 int bitvalue;
|
|
2049 } *post_div,
|
|
2050 post_divs[] = {
|
|
2051 { 1, 0 },
|
|
2052 { 2, 1 },
|
|
2053 { 4, 2 },
|
|
2054 { 8, 3 },
|
|
2055 { 3, 4 },
|
|
2056 { 16, 5 },
|
|
2057 { 6, 6 },
|
|
2058 { 12, 7 },
|
|
2059 { 0, 0 },
|
|
2060 };
|
|
2061
|
|
2062 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
2063 rinfo->pll_output_freq = post_div->divider * freq;
|
|
2064 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
|
|
2065 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
|
|
2066 break;
|
|
2067 }
|
|
2068
|
|
2069 rinfo->post_div = post_div->divider;
|
|
2070 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
|
|
2071 rinfo->pll.ref_clk);
|
|
2072 newmode.ppll_ref_div = rinfo->pll.ref_div;
|
|
2073 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
|
|
2074 }
|
|
2075
|
|
2076 RTRACE("post div = 0x%x\n", rinfo->post_div);
|
|
2077 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
|
|
2078 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
|
|
2079
|
|
2080 /* DDA */
|
|
2081 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
|
|
2082 rinfo->pll.ref_div * rinfo->post_div);
|
|
2083 xclk_freq = rinfo->pll.xclk;
|
|
2084
|
|
2085 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
|
|
2086
|
|
2087 min_bits = min_bits_req(xclk_per_trans);
|
|
2088 useable_precision = min_bits + 1;
|
|
2089
|
|
2090 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
|
|
2091 vclk_freq * mode->bits_per_pixel);
|
|
2092
|
|
2093 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
|
|
2094 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
|
|
2095 xclk_per_trans) << (11 - useable_precision);
|
|
2096 roff = xclk_per_trans_precise * (32 - 4);
|
|
2097
|
|
2098 RTRACE("ron = %d, roff = %d\n", ron, roff);
|
|
2099 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
|
|
2100
|
|
2101 if ((ron + rinfo->ram.rloop) >= roff) {
|
|
2102 printk("radeonfb: error ron out of range\n");
|
|
2103 return;
|
|
2104 }
|
|
2105
|
|
2106 newmode.dda_config = (xclk_per_trans_precise |
|
|
2107 (useable_precision << 16) |
|
|
2108 (rinfo->ram.rloop << 20));
|
|
2109 newmode.dda_on_off = (ron << 16) | roff;
|
|
2110
|
|
2111 /* do it! */
|
|
2112 radeon_write_mode (rinfo, &newmode);
|
1915
|
2113 /* XXX absurd hack for X to restore console on VE */
|
|
2114 if(rinfo->hasCRTC2 && rinfo->crtDispType == MT_CRT &&
|
|
2115 (rinfo->dviDispType == MT_NONE || rinfo->dviDispType == MT_STV)) {
|
|
2116 OUTREG(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl);
|
|
2117 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
|
|
2118 }
|
1911
|
2119 return;
|
|
2120 }
|
|
2121
|
|
2122
|
1915
|
2123 /*****
|
|
2124 When changing mode with Dual-head card (VE/M6), care must
|
|
2125 be taken for the special order in setting registers. CRTC2 has
|
|
2126 to be set before changing CRTC_EXT register.
|
|
2127 Otherwise we may get a blank screen.
|
|
2128 *****/
|
1911
|
2129
|
|
2130 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
2131 struct radeon_regs *mode)
|
|
2132 {
|
|
2133 int i;
|
|
2134
|
|
2135 /* blank screen */
|
|
2136 OUTREG8(CRTC_EXT_CNTL + 1, 4);
|
|
2137
|
|
2138 for (i=0; i<9; i++)
|
|
2139 OUTREG(common_regs[i].reg, common_regs[i].val);
|
|
2140
|
|
2141 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
|
|
2142 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
|
|
2143 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
|
|
2144 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
|
|
2145 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
|
|
2146 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
|
|
2147 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
|
|
2148 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
|
|
2149 OUTREG(CRTC_OFFSET, 0);
|
|
2150 OUTREG(CRTC_OFFSET_CNTL, 0);
|
|
2151 OUTREG(CRTC_PITCH, mode->crtc_pitch);
|
1915
|
2152 #if defined(__BIG_ENDIAN)
|
|
2153 /* XXX this code makes degradation of mplayer quality on Radeon VE */
|
1914
|
2154 OUTREG(SURFACE_CNTL, mode->surface_cntl);
|
1915
|
2155 #endif
|
|
2156 /* Here we should restore FP registers for LCD & DFP monitors */
|
1911
|
2157
|
|
2158 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
|
|
2159 PPLL_DIV_SEL_MASK) {
|
|
2160 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
|
|
2161 }
|
|
2162
|
|
2163 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
|
|
2164
|
|
2165 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
|
|
2166 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
|
|
2167 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
|
2168 }
|
|
2169
|
|
2170 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
|
|
2171 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
|
|
2172 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
|
2173 }
|
|
2174
|
|
2175 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
|
|
2176 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
|
|
2177 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
|
2178 }
|
|
2179
|
|
2180 OUTPLL(HTOTAL_CNTL, 0);
|
|
2181
|
|
2182 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
|
|
2183
|
|
2184 OUTREG(DDA_CONFIG, mode->dda_config);
|
|
2185 OUTREG(DDA_ON_OFF, mode->dda_on_off);
|
|
2186
|
|
2187 /* unblank screen */
|
|
2188 OUTREG8(CRTC_EXT_CNTL + 1, 0);
|
|
2189
|
|
2190 return;
|
|
2191 }
|
|
2192
|
1914
|
2193 #if 0
|
1911
|
2194
|
|
2195 /*
|
|
2196 * text console acceleration
|
|
2197 */
|
|
2198
|
|
2199
|
|
2200 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
|
|
2201 int dsty, int dstx, int height, int width)
|
|
2202 {
|
|
2203 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
2204 u32 dp_cntl = DST_LAST_PEL;
|
|
2205
|
|
2206 srcx *= fontwidth(p);
|
|
2207 srcy *= fontheight(p);
|
|
2208 dstx *= fontwidth(p);
|
|
2209 dsty *= fontheight(p);
|
|
2210 width *= fontwidth(p);
|
|
2211 height *= fontheight(p);
|
|
2212
|
|
2213 if (srcy < dsty) {
|
|
2214 srcy += height - 1;
|
|
2215 dsty += height - 1;
|
|
2216 } else
|
|
2217 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
|
|
2218
|
|
2219 if (srcx < dstx) {
|
|
2220 srcx += width - 1;
|
|
2221 dstx += width - 1;
|
|
2222 } else
|
|
2223 dp_cntl |= DST_X_LEFT_TO_RIGHT;
|
|
2224
|
|
2225 radeon_fifo_wait(6);
|
|
2226 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2227 GMC_BRUSH_NONE |
|
|
2228 GMC_SRC_DATATYPE_COLOR |
|
|
2229 ROP3_S |
|
|
2230 DP_SRC_SOURCE_MEMORY));
|
|
2231 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2232 OUTREG(DP_CNTL, dp_cntl);
|
|
2233 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
|
|
2234 OUTREG(DST_Y_X, (dsty << 16) | dstx);
|
|
2235 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
|
|
2236 }
|
|
2237
|
|
2238
|
|
2239
|
|
2240 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|
2241 int srcy, int srcx, int height, int width)
|
|
2242 {
|
|
2243 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
2244 u32 clr;
|
|
2245
|
|
2246 clr = attr_bgcol_ec(p, conp);
|
|
2247 clr |= (clr << 8);
|
|
2248 clr |= (clr << 16);
|
|
2249
|
|
2250 srcx *= fontwidth(p);
|
|
2251 srcy *= fontheight(p);
|
|
2252 width *= fontwidth(p);
|
|
2253 height *= fontheight(p);
|
|
2254
|
|
2255 radeon_fifo_wait(6);
|
|
2256 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2257 GMC_BRUSH_SOLID_COLOR |
|
|
2258 GMC_SRC_DATATYPE_COLOR |
|
|
2259 ROP3_P));
|
|
2260 OUTREG(DP_BRUSH_FRGD_CLR, clr);
|
|
2261 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2262 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
|
|
2263 OUTREG(DST_Y_X, (srcy << 16) | srcx);
|
|
2264 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
|
|
2265 }
|
|
2266
|
|
2267
|
|
2268
|
|
2269
|
|
2270 #ifdef FBCON_HAS_CFB8
|
|
2271 static struct display_switch fbcon_radeon8 = {
|
|
2272 setup: fbcon_cfb8_setup,
|
|
2273 bmove: fbcon_radeon_bmove,
|
|
2274 clear: fbcon_cfb8_clear,
|
|
2275 putc: fbcon_cfb8_putc,
|
|
2276 putcs: fbcon_cfb8_putcs,
|
|
2277 revc: fbcon_cfb8_revc,
|
|
2278 clear_margins: fbcon_cfb8_clear_margins,
|
|
2279 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
|
2280 };
|
|
2281 #endif
|
1914
|
2282
|
|
2283 #endif /* 0 */
|