Mercurial > mplayer.hg
annotate vidix/drivers/radeon_vid.c @ 8134:63364178ff56
divx_vbr.c now GPL, small parts rephrased.
author | diego |
---|---|
date | Sat, 09 Nov 2002 02:22:19 +0000 |
parents | bd423c9c835a |
children | 3f5788602dfd |
rev | line source |
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3996 | 1 /* |
2 radeon_vid - VIDIX based video driver for Radeon and Rage128 chips | |
4030 | 3 Copyrights 2002 Nick Kurshev. This file is based on sources from |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
3996 | 6 */ |
7 | |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
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13 #include <inttypes.h> |
4201 | 14 #include "../../libdha/pci_ids.h" |
15 #include "../../libdha/pci_names.h" | |
3996 | 16 #include "../vidix.h" |
17 #include "../fourcc.h" | |
18 #include "../../libdha/libdha.h" | |
19 #include "radeon.h" | |
20 | |
21 #ifdef RAGE128 | |
22 #define RADEON_MSG "Rage128_vid:" | |
23 #define X_ADJUST 0 | |
24 #else | |
25 #define RADEON_MSG "Radeon_vid:" | |
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26 #define X_ADJUST (!IsR200 ? 8 : 0) |
3996 | 27 #ifndef RADEON |
28 #define RADEON | |
29 #endif | |
30 #endif | |
31 | |
4030 | 32 static int __verbose = 0; |
4015 | 33 |
3996 | 34 typedef struct bes_registers_s |
35 { | |
36 /* base address of yuv framebuffer */ | |
37 uint32_t yuv_base; | |
38 uint32_t fourcc; | |
39 uint32_t dest_bpp; | |
40 /* YUV BES registers */ | |
41 uint32_t reg_load_cntl; | |
42 uint32_t h_inc; | |
43 uint32_t step_by; | |
44 uint32_t y_x_start; | |
45 uint32_t y_x_end; | |
46 uint32_t v_inc; | |
47 uint32_t p1_blank_lines_at_top; | |
48 uint32_t p23_blank_lines_at_top; | |
49 uint32_t vid_buf_pitch0_value; | |
50 uint32_t vid_buf_pitch1_value; | |
51 uint32_t p1_x_start_end; | |
52 uint32_t p2_x_start_end; | |
53 uint32_t p3_x_start_end; | |
54 uint32_t base_addr; | |
4930 | 55 uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; |
56 uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; | |
57 uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; | |
58 uint32_t vid_nbufs; | |
3996 | 59 |
60 uint32_t p1_v_accum_init; | |
61 uint32_t p1_h_accum_init; | |
62 uint32_t p23_v_accum_init; | |
63 uint32_t p23_h_accum_init; | |
64 uint32_t scale_cntl; | |
65 uint32_t exclusive_horz; | |
66 uint32_t auto_flip_cntl; | |
67 uint32_t filter_cntl; | |
68 uint32_t key_cntl; | |
69 uint32_t test; | |
70 /* Configurable stuff */ | |
71 int double_buff; | |
72 | |
73 int brightness; | |
74 int saturation; | |
75 | |
76 int ckey_on; | |
77 uint32_t graphics_key_clr; | |
78 uint32_t graphics_key_msk; | |
4869 | 79 uint32_t ckey_cntl; |
3996 | 80 |
81 int deinterlace_on; | |
82 uint32_t deinterlace_pattern; | |
83 | |
84 } bes_registers_t; | |
85 | |
86 typedef struct video_registers_s | |
87 { | |
88 const char * sname; | |
89 uint32_t name; | |
90 uint32_t value; | |
91 }video_registers_t; | |
92 | |
93 static bes_registers_t besr; | |
94 #ifndef RAGE128 | |
95 static int IsR200=0; | |
96 #endif | |
97 #define DECLARE_VREG(name) { #name, name, 0 } | |
98 static video_registers_t vregs[] = | |
99 { | |
100 DECLARE_VREG(VIDEOMUX_CNTL), | |
101 DECLARE_VREG(VIPPAD_MASK), | |
102 DECLARE_VREG(VIPPAD1_A), | |
103 DECLARE_VREG(VIPPAD1_EN), | |
104 DECLARE_VREG(VIPPAD1_Y), | |
105 DECLARE_VREG(OV0_Y_X_START), | |
106 DECLARE_VREG(OV0_Y_X_END), | |
107 DECLARE_VREG(OV0_PIPELINE_CNTL), | |
108 DECLARE_VREG(OV0_EXCLUSIVE_HORZ), | |
109 DECLARE_VREG(OV0_EXCLUSIVE_VERT), | |
110 DECLARE_VREG(OV0_REG_LOAD_CNTL), | |
111 DECLARE_VREG(OV0_SCALE_CNTL), | |
112 DECLARE_VREG(OV0_V_INC), | |
113 DECLARE_VREG(OV0_P1_V_ACCUM_INIT), | |
114 DECLARE_VREG(OV0_P23_V_ACCUM_INIT), | |
115 DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), | |
116 DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), | |
117 #ifdef RADEON | |
118 DECLARE_VREG(OV0_BASE_ADDR), | |
119 #endif | |
120 DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), | |
121 DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), | |
122 DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), | |
123 DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), | |
124 DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), | |
125 DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), | |
126 DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), | |
127 DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), | |
128 DECLARE_VREG(OV0_AUTO_FLIP_CNTL), | |
129 DECLARE_VREG(OV0_DEINTERLACE_PATTERN), | |
130 DECLARE_VREG(OV0_SUBMIT_HISTORY), | |
131 DECLARE_VREG(OV0_H_INC), | |
132 DECLARE_VREG(OV0_STEP_BY), | |
133 DECLARE_VREG(OV0_P1_H_ACCUM_INIT), | |
134 DECLARE_VREG(OV0_P23_H_ACCUM_INIT), | |
135 DECLARE_VREG(OV0_P1_X_START_END), | |
136 DECLARE_VREG(OV0_P2_X_START_END), | |
137 DECLARE_VREG(OV0_P3_X_START_END), | |
138 DECLARE_VREG(OV0_FILTER_CNTL), | |
139 DECLARE_VREG(OV0_FOUR_TAP_COEF_0), | |
140 DECLARE_VREG(OV0_FOUR_TAP_COEF_1), | |
141 DECLARE_VREG(OV0_FOUR_TAP_COEF_2), | |
142 DECLARE_VREG(OV0_FOUR_TAP_COEF_3), | |
143 DECLARE_VREG(OV0_FOUR_TAP_COEF_4), | |
144 DECLARE_VREG(OV0_FLAG_CNTL), | |
145 #ifdef RAGE128 | |
146 DECLARE_VREG(OV0_COLOUR_CNTL), | |
147 #else | |
148 DECLARE_VREG(OV0_SLICE_CNTL), | |
149 #endif | |
150 DECLARE_VREG(OV0_VID_KEY_CLR), | |
151 DECLARE_VREG(OV0_VID_KEY_MSK), | |
152 DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), | |
153 DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), | |
154 DECLARE_VREG(OV0_KEY_CNTL), | |
155 DECLARE_VREG(OV0_TEST), | |
156 DECLARE_VREG(OV0_LIN_TRANS_A), | |
157 DECLARE_VREG(OV0_LIN_TRANS_B), | |
158 DECLARE_VREG(OV0_LIN_TRANS_C), | |
159 DECLARE_VREG(OV0_LIN_TRANS_D), | |
160 DECLARE_VREG(OV0_LIN_TRANS_E), | |
161 DECLARE_VREG(OV0_LIN_TRANS_F), | |
162 DECLARE_VREG(OV0_GAMMA_0_F), | |
163 DECLARE_VREG(OV0_GAMMA_10_1F), | |
164 DECLARE_VREG(OV0_GAMMA_20_3F), | |
165 DECLARE_VREG(OV0_GAMMA_40_7F), | |
166 DECLARE_VREG(OV0_GAMMA_380_3BF), | |
167 DECLARE_VREG(OV0_GAMMA_3C0_3FF), | |
168 DECLARE_VREG(SUBPIC_CNTL), | |
169 DECLARE_VREG(SUBPIC_DEFCOLCON), | |
170 DECLARE_VREG(SUBPIC_Y_X_START), | |
171 DECLARE_VREG(SUBPIC_Y_X_END), | |
172 DECLARE_VREG(SUBPIC_V_INC), | |
173 DECLARE_VREG(SUBPIC_H_INC), | |
174 DECLARE_VREG(SUBPIC_BUF0_OFFSET), | |
175 DECLARE_VREG(SUBPIC_BUF1_OFFSET), | |
176 DECLARE_VREG(SUBPIC_LC0_OFFSET), | |
177 DECLARE_VREG(SUBPIC_LC1_OFFSET), | |
178 DECLARE_VREG(SUBPIC_PITCH), | |
179 DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), | |
180 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), | |
181 DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), | |
182 DECLARE_VREG(SUBPIC_PALETTE_INDEX), | |
183 DECLARE_VREG(SUBPIC_PALETTE_DATA), | |
184 DECLARE_VREG(SUBPIC_H_ACCUM_INIT), | |
185 DECLARE_VREG(SUBPIC_V_ACCUM_INIT), | |
186 DECLARE_VREG(IDCT_RUNS), | |
187 DECLARE_VREG(IDCT_LEVELS), | |
188 DECLARE_VREG(IDCT_AUTH_CONTROL), | |
189 DECLARE_VREG(IDCT_AUTH), | |
190 DECLARE_VREG(IDCT_CONTROL) | |
191 }; | |
4030 | 192 |
3996 | 193 static void * radeon_mmio_base = 0; |
194 static void * radeon_mem_base = 0; | |
195 static int32_t radeon_overlay_off = 0; | |
196 static uint32_t radeon_ram_size = 0; | |
197 | |
4012 | 198 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) |
199 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
200 | |
201 #define INREG8(addr) GETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr) | |
202 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)(radeon_mmio_base),addr,val) | |
203 #define INREG(addr) GETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr) | |
204 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)(radeon_mmio_base),addr,val) | |
3996 | 205 #define OUTREGP(addr,val,mask) \ |
206 do { \ | |
207 unsigned int _tmp = INREG(addr); \ | |
208 _tmp &= (mask); \ | |
209 _tmp |= (val); \ | |
210 OUTREG(addr, _tmp); \ | |
211 } while (0) | |
212 | |
4666 | 213 static __inline__ uint32_t INPLL(uint32_t addr) |
214 { | |
215 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); | |
216 return (INREG(CLOCK_CNTL_DATA)); | |
217 } | |
218 | |
219 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ | |
220 OUTREG(CLOCK_CNTL_DATA, val) | |
221 #define OUTPLLP(addr,val,mask) \ | |
222 do { \ | |
223 unsigned int _tmp = INPLL(addr); \ | |
224 _tmp &= (mask); \ | |
225 _tmp |= (val); \ | |
226 OUTPLL(addr, _tmp); \ | |
227 } while (0) | |
228 | |
3996 | 229 static uint32_t radeon_vid_get_dbpp( void ) |
230 { | |
231 uint32_t dbpp,retval; | |
232 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; | |
233 switch(dbpp) | |
234 { | |
235 case DST_8BPP: retval = 8; break; | |
236 case DST_15BPP: retval = 15; break; | |
237 case DST_16BPP: retval = 16; break; | |
238 case DST_24BPP: retval = 24; break; | |
239 default: retval=32; break; | |
240 } | |
241 return retval; | |
242 } | |
243 | |
244 static int radeon_is_dbl_scan( void ) | |
245 { | |
246 return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; | |
247 } | |
248 | |
249 static int radeon_is_interlace( void ) | |
250 { | |
251 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; | |
252 } | |
253 | |
4666 | 254 static uint32_t radeon_get_xres( void ) |
255 { | |
256 /* FIXME: currently we extract that from CRTC!!!*/ | |
257 uint32_t xres,h_total; | |
258 h_total = INREG(CRTC_H_TOTAL_DISP); | |
259 xres = (h_total >> 16) & 0xffff; | |
260 return (xres + 1)*8; | |
261 } | |
262 | |
263 static uint32_t radeon_get_yres( void ) | |
264 { | |
265 /* FIXME: currently we extract that from CRTC!!!*/ | |
266 uint32_t yres,v_total; | |
267 v_total = INREG(CRTC_V_TOTAL_DISP); | |
268 yres = (v_total >> 16) & 0xffff; | |
269 return yres + 1; | |
270 } | |
271 | |
4689 | 272 static void radeon_wait_vsync(void) |
273 { | |
274 int i; | |
275 | |
276 OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); | |
277 for (i = 0; i < 2000000; i++) | |
278 { | |
279 if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; | |
280 } | |
281 } | |
282 | |
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283 #ifdef RAGE128 |
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284 static void _radeon_engine_idle(void); |
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285 static void _radeon_fifo_wait(unsigned); |
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286 #define radeon_engine_idle() _radeon_engine_idle() |
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287 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) |
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288 /* Flush all dirty data in the Pixel Cache to memory. */ |
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289 static __inline__ void radeon_engine_flush ( void ) |
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290 { |
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291 unsigned i; |
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292 |
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293 OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); |
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294 for (i = 0; i < 2000000; i++) { |
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295 if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; |
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296 } |
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297 } |
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298 |
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299 /* Reset graphics card to known state. */ |
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300 static void radeon_engine_reset( void ) |
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301 { |
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302 uint32_t clock_cntl_index; |
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303 uint32_t mclk_cntl; |
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304 uint32_t gen_reset_cntl; |
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305 |
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306 radeon_engine_flush(); |
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307 |
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308 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); |
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309 mclk_cntl = INPLL(MCLK_CNTL); |
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310 |
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311 OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); |
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312 |
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313 gen_reset_cntl = INREG(GEN_RESET_CNTL); |
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314 |
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315 OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); |
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316 INREG(GEN_RESET_CNTL); |
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317 OUTREG(GEN_RESET_CNTL, |
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318 gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); |
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319 INREG(GEN_RESET_CNTL); |
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320 |
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321 OUTPLL(MCLK_CNTL, mclk_cntl); |
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322 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); |
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323 OUTREG(GEN_RESET_CNTL, gen_reset_cntl); |
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324 } |
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325 #else |
4689 | 326 |
3996 | 327 static __inline__ void radeon_engine_flush ( void ) |
328 { | |
329 int i; | |
330 | |
331 /* initiate flush */ | |
332 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, | |
333 ~RB2D_DC_FLUSH_ALL); | |
334 | |
335 for (i=0; i < 2000000; i++) { | |
336 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) | |
337 break; | |
338 } | |
339 } | |
340 | |
4666 | 341 static void _radeon_engine_idle(void); |
342 static void _radeon_fifo_wait(unsigned); | |
343 #define radeon_engine_idle() _radeon_engine_idle() | |
344 #define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) | |
3996 | 345 |
4666 | 346 static void radeon_engine_reset( void ) |
3996 | 347 { |
4666 | 348 uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; |
349 | |
350 radeon_engine_flush (); | |
351 | |
352 clock_cntl_index = INREG(CLOCK_CNTL_INDEX); | |
353 mclk_cntl = INPLL(MCLK_CNTL); | |
354 | |
355 OUTPLL(MCLK_CNTL, (mclk_cntl | | |
356 FORCEON_MCLKA | | |
357 FORCEON_MCLKB | | |
358 FORCEON_YCLKA | | |
359 FORCEON_YCLKB | | |
360 FORCEON_MC | | |
361 FORCEON_AIC)); | |
362 rbbm_soft_reset = INREG(RBBM_SOFT_RESET); | |
3996 | 363 |
4666 | 364 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | |
365 SOFT_RESET_CP | | |
366 SOFT_RESET_HI | | |
367 SOFT_RESET_SE | | |
368 SOFT_RESET_RE | | |
369 SOFT_RESET_PP | | |
370 SOFT_RESET_E2 | | |
371 SOFT_RESET_RB | | |
372 SOFT_RESET_HDP); | |
373 INREG(RBBM_SOFT_RESET); | |
374 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) | |
375 ~(SOFT_RESET_CP | | |
376 SOFT_RESET_HI | | |
377 SOFT_RESET_SE | | |
378 SOFT_RESET_RE | | |
379 SOFT_RESET_PP | | |
380 SOFT_RESET_E2 | | |
381 SOFT_RESET_RB | | |
382 SOFT_RESET_HDP)); | |
383 INREG(RBBM_SOFT_RESET); | |
384 | |
385 OUTPLL(MCLK_CNTL, mclk_cntl); | |
386 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); | |
387 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); | |
388 | |
389 return; | |
3996 | 390 } |
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391 #endif |
4666 | 392 static void radeon_engine_restore( void ) |
3996 | 393 { |
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394 #ifndef RAGE128 |
4666 | 395 int pitch64; |
396 uint32_t xres,yres,bpp; | |
397 radeon_fifo_wait(1); | |
398 xres = radeon_get_xres(); | |
399 yres = radeon_get_yres(); | |
400 bpp = radeon_vid_get_dbpp(); | |
401 /* turn of all automatic flushing - we'll do it all */ | |
402 OUTREG(RB2D_DSTCACHE_MODE, 0); | |
403 | |
404 pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; | |
405 | |
406 radeon_fifo_wait(1); | |
407 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | | |
408 (pitch64 << 22)); | |
409 | |
410 radeon_fifo_wait(1); | |
411 #if defined(__BIG_ENDIAN) | |
412 OUTREGP(DP_DATATYPE, | |
413 HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); | |
414 #else | |
415 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); | |
416 #endif | |
417 | |
418 radeon_fifo_wait(1); | |
419 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX | |
420 | DEFAULT_SC_BOTTOM_MAX)); | |
421 radeon_fifo_wait(1); | |
422 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) | |
423 | GMC_BRUSH_SOLID_COLOR | |
424 | GMC_SRC_DATATYPE_COLOR)); | |
3996 | 425 |
4666 | 426 radeon_fifo_wait(7); |
427 OUTREG(DST_LINE_START, 0); | |
428 OUTREG(DST_LINE_END, 0); | |
429 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); | |
430 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); | |
431 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); | |
432 OUTREG(DP_SRC_BKGD_CLR, 0x00000000); | |
433 OUTREG(DP_WRITE_MASK, 0xffffffff); | |
434 | |
435 radeon_engine_idle(); | |
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436 #endif |
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437 } |
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438 #ifdef RAGE128 |
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439 static void _radeon_fifo_wait (unsigned entries) |
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440 { |
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441 unsigned i; |
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442 |
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443 for(;;) |
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444 { |
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445 for (i=0; i<2000000; i++) |
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446 if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) |
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447 return; |
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448 radeon_engine_reset(); |
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449 radeon_engine_restore(); |
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450 } |
4666 | 451 } |
452 | |
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453 static void _radeon_engine_idle ( void ) |
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454 { |
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455 unsigned i; |
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456 |
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457 /* ensure FIFO is empty before waiting for idle */ |
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458 radeon_fifo_wait (64); |
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459 for(;;) |
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460 { |
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461 for (i=0; i<2000000; i++) { |
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462 if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { |
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463 radeon_engine_flush (); |
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464 return; |
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465 } |
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466 } |
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467 radeon_engine_reset(); |
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468 radeon_engine_restore(); |
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469 } |
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470 } |
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471 #else |
4666 | 472 static void _radeon_fifo_wait (unsigned entries) |
473 { | |
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474 unsigned i; |
3996 | 475 |
4666 | 476 for(;;) |
477 { | |
478 for (i=0; i<2000000; i++) | |
479 if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) | |
480 return; | |
481 radeon_engine_reset(); | |
482 radeon_engine_restore(); | |
483 } | |
484 } | |
485 static void _radeon_engine_idle ( void ) | |
486 { | |
487 int i; | |
488 | |
489 /* ensure FIFO is empty before waiting for idle */ | |
490 radeon_fifo_wait (64); | |
491 for(;;) | |
492 { | |
3996 | 493 for (i=0; i<2000000; i++) { |
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494 if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { |
3996 | 495 radeon_engine_flush (); |
496 return; | |
497 } | |
498 } | |
4666 | 499 radeon_engine_reset(); |
500 radeon_engine_restore(); | |
501 } | |
3996 | 502 } |
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503 #endif |
3996 | 504 |
505 #ifndef RAGE128 | |
506 /* Reference color space transform data */ | |
507 typedef struct tagREF_TRANSFORM | |
508 { | |
509 float RefLuma; | |
510 float RefRCb; | |
511 float RefRCr; | |
512 float RefGCb; | |
513 float RefGCr; | |
514 float RefBCb; | |
515 float RefBCr; | |
516 } REF_TRANSFORM; | |
517 | |
518 /* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ | |
519 REF_TRANSFORM trans[2] = | |
520 { | |
521 {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ | |
522 {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ | |
523 }; | |
524 /**************************************************************************** | |
525 * SetTransform * | |
526 * Function: Calculates and sets color space transform from supplied * | |
527 * reference transform, gamma, brightness, contrast, hue and * | |
528 * saturation. * | |
529 * Inputs: bright - brightness * | |
530 * cont - contrast * | |
531 * sat - saturation * | |
532 * hue - hue * | |
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533 * red_intensity - intense of red component * |
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534 * green_intensity - intense of green component * |
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535 * blue_intensity - intense of blue component * |
3996 | 536 * ref - index to the table of refernce transforms * |
537 * Outputs: NONE * | |
538 ****************************************************************************/ | |
539 | |
540 static void radeon_set_transform(float bright, float cont, float sat, | |
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541 float hue, float red_intensity, |
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542 float green_intensity,float blue_intensity, |
4284 | 543 unsigned ref) |
3996 | 544 { |
545 float OvHueSin, OvHueCos; | |
546 float CAdjLuma, CAdjOff; | |
4284 | 547 float RedAdj,GreenAdj,BlueAdj; |
3996 | 548 float CAdjRCb, CAdjRCr; |
549 float CAdjGCb, CAdjGCr; | |
550 float CAdjBCb, CAdjBCr; | |
551 float OvLuma, OvROff, OvGOff, OvBOff; | |
552 float OvRCb, OvRCr; | |
553 float OvGCb, OvGCr; | |
554 float OvBCb, OvBCr; | |
555 float Loff = 64.0; | |
556 float Coff = 512.0f; | |
557 | |
558 uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; | |
559 uint32_t dwOvRCb, dwOvRCr; | |
560 uint32_t dwOvGCb, dwOvGCr; | |
561 uint32_t dwOvBCb, dwOvBCr; | |
562 | |
563 if (ref >= 2) return; | |
564 | |
565 OvHueSin = sin((double)hue); | |
566 OvHueCos = cos((double)hue); | |
567 | |
568 CAdjLuma = cont * trans[ref].RefLuma; | |
569 CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; | |
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570 RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; |
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571 GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; |
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572 BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; |
3996 | 573 |
574 CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; | |
575 CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; | |
576 CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); | |
577 CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); | |
578 CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; | |
579 CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; | |
580 | |
581 #if 0 /* default constants */ | |
582 CAdjLuma = 1.16455078125; | |
583 | |
584 CAdjRCb = 0.0; | |
585 CAdjRCr = 1.59619140625; | |
586 CAdjGCb = -0.39111328125; | |
587 CAdjGCr = -0.8125; | |
588 CAdjBCb = 2.01708984375; | |
589 CAdjBCr = 0; | |
590 #endif | |
591 OvLuma = CAdjLuma; | |
592 OvRCb = CAdjRCb; | |
593 OvRCr = CAdjRCr; | |
594 OvGCb = CAdjGCb; | |
595 OvGCr = CAdjGCr; | |
596 OvBCb = CAdjBCb; | |
597 OvBCr = CAdjBCr; | |
4284 | 598 OvROff = RedAdj + CAdjOff - |
3996 | 599 OvLuma * Loff - (OvRCb + OvRCr) * Coff; |
4284 | 600 OvGOff = GreenAdj + CAdjOff - |
3996 | 601 OvLuma * Loff - (OvGCb + OvGCr) * Coff; |
4284 | 602 OvBOff = BlueAdj + CAdjOff - |
3996 | 603 OvLuma * Loff - (OvBCb + OvBCr) * Coff; |
604 #if 0 /* default constants */ | |
605 OvROff = -888.5; | |
606 OvGOff = 545; | |
607 OvBOff = -1104; | |
608 #endif | |
609 | |
610 dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; | |
611 dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; | |
612 dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; | |
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613 /* Whatever docs say about R200 having 3.8 format instead of 3.11 |
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614 as in Radeon is a lie */ |
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615 #if 0 |
3996 | 616 if(!IsR200) |
617 { | |
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618 #endif |
3996 | 619 dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; |
620 dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; | |
621 dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; | |
622 dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; | |
623 dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; | |
624 dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; | |
625 dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; | |
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626 #if 0 |
3996 | 627 } |
628 else | |
629 { | |
630 dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; | |
631 dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; | |
632 dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; | |
633 dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; | |
634 dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; | |
635 dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; | |
636 dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; | |
637 } | |
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638 #endif |
3996 | 639 OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); |
640 OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); | |
641 OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); | |
642 OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); | |
643 OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); | |
644 OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); | |
645 } | |
646 | |
647 /* Gamma curve definition */ | |
648 typedef struct | |
649 { | |
650 unsigned int gammaReg; | |
651 unsigned int gammaSlope; | |
652 unsigned int gammaOffset; | |
653 }GAMMA_SETTINGS; | |
654 | |
655 /* Recommended gamma curve parameters */ | |
656 GAMMA_SETTINGS r200_def_gamma[18] = | |
657 { | |
658 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
659 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
660 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
661 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
662 {OV0_GAMMA_80_BF, 0x100, 0x0100}, | |
663 {OV0_GAMMA_C0_FF, 0x100, 0x0100}, | |
664 {OV0_GAMMA_100_13F, 0x100, 0x0200}, | |
665 {OV0_GAMMA_140_17F, 0x100, 0x0200}, | |
666 {OV0_GAMMA_180_1BF, 0x100, 0x0300}, | |
667 {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, | |
668 {OV0_GAMMA_200_23F, 0x100, 0x0400}, | |
669 {OV0_GAMMA_240_27F, 0x100, 0x0400}, | |
670 {OV0_GAMMA_280_2BF, 0x100, 0x0500}, | |
671 {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, | |
672 {OV0_GAMMA_300_33F, 0x100, 0x0600}, | |
673 {OV0_GAMMA_340_37F, 0x100, 0x0600}, | |
674 {OV0_GAMMA_380_3BF, 0x100, 0x0700}, | |
675 {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} | |
676 }; | |
677 | |
678 GAMMA_SETTINGS r100_def_gamma[6] = | |
679 { | |
680 {OV0_GAMMA_0_F, 0x100, 0x0000}, | |
681 {OV0_GAMMA_10_1F, 0x100, 0x0020}, | |
682 {OV0_GAMMA_20_3F, 0x100, 0x0040}, | |
683 {OV0_GAMMA_40_7F, 0x100, 0x0080}, | |
684 {OV0_GAMMA_380_3BF, 0x100, 0x0100}, | |
685 {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} | |
686 }; | |
687 | |
688 static void make_default_gamma_correction( void ) | |
689 { | |
690 size_t i; | |
691 if(!IsR200){ | |
692 OUTREG(OV0_LIN_TRANS_A, 0x12A00000); | |
693 OUTREG(OV0_LIN_TRANS_B, 0x199018FE); | |
694 OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); | |
695 OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); | |
696 OUTREG(OV0_LIN_TRANS_E, 0x12A02050); | |
697 OUTREG(OV0_LIN_TRANS_F, 0x0000174E); | |
698 for(i=0; i<6; i++){ | |
699 OUTREG(r100_def_gamma[i].gammaReg, | |
700 (r100_def_gamma[i].gammaSlope<<16) | | |
701 r100_def_gamma[i].gammaOffset); | |
702 } | |
703 } | |
704 else{ | |
705 OUTREG(OV0_LIN_TRANS_A, 0x12a00000); | |
706 OUTREG(OV0_LIN_TRANS_B, 0x1990190e); | |
707 OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); | |
708 OUTREG(OV0_LIN_TRANS_D, 0xf3000442); | |
709 OUTREG(OV0_LIN_TRANS_E, 0x12a02040); | |
710 OUTREG(OV0_LIN_TRANS_F, 0x175f); | |
711 | |
712 /* Default Gamma, | |
713 Of 18 segments for gamma cure, all segments in R200 are programmable, | |
714 while only lower 4 and upper 2 segments are programmable in Radeon*/ | |
715 for(i=0; i<18; i++){ | |
716 OUTREG(r200_def_gamma[i].gammaReg, | |
717 (r200_def_gamma[i].gammaSlope<<16) | | |
718 r200_def_gamma[i].gammaOffset); | |
719 } | |
720 } | |
721 } | |
722 #endif | |
723 | |
724 static void radeon_vid_make_default(void) | |
725 { | |
726 #ifdef RAGE128 | |
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727 OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ |
3996 | 728 #else |
729 make_default_gamma_correction(); | |
730 #endif | |
731 besr.deinterlace_pattern = 0x900AAAAA; | |
732 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
733 besr.deinterlace_on=1; | |
734 besr.double_buff=1; | |
4869 | 735 besr.ckey_on=0; |
736 besr.graphics_key_msk=0; | |
737 besr.graphics_key_clr=0; | |
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738 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
3996 | 739 } |
740 | |
741 | |
742 unsigned vixGetVersion( void ) { return VIDIX_VERSION; } | |
743 | |
4107 | 744 static unsigned short ati_card_ids[] = |
3996 | 745 { |
746 #ifdef RAGE128 | |
747 /* | |
748 This driver should be compatible with Rage128 (pro) chips. | |
749 (include adaptive deinterlacing!!!). | |
750 Moreover: the same logic can be used with Mach64 chips. | |
751 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
752 but they are incompatible by i/o ports. So if enthusiasts will want | |
753 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
754 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
755 fourccs (422 and 420 formats only). | |
756 */ | |
757 /* Rage128 Pro GL */ | |
4107 | 758 DEVICE_ATI_RAGE_128_PA_PRO, |
759 DEVICE_ATI_RAGE_128_PB_PRO, | |
760 DEVICE_ATI_RAGE_128_PC_PRO, | |
761 DEVICE_ATI_RAGE_128_PD_PRO, | |
762 DEVICE_ATI_RAGE_128_PE_PRO, | |
763 DEVICE_ATI_RAGE_128_PF_PRO, | |
3996 | 764 /* Rage128 Pro VR */ |
4107 | 765 DEVICE_ATI_RAGE_128_PG_PRO, |
766 DEVICE_ATI_RAGE_128_PH_PRO, | |
767 DEVICE_ATI_RAGE_128_PI_PRO, | |
768 DEVICE_ATI_RAGE_128_PJ_PRO, | |
769 DEVICE_ATI_RAGE_128_PK_PRO, | |
770 DEVICE_ATI_RAGE_128_PL_PRO, | |
771 DEVICE_ATI_RAGE_128_PM_PRO, | |
772 DEVICE_ATI_RAGE_128_PN_PRO, | |
773 DEVICE_ATI_RAGE_128_PO_PRO, | |
774 DEVICE_ATI_RAGE_128_PP_PRO, | |
775 DEVICE_ATI_RAGE_128_PQ_PRO, | |
776 DEVICE_ATI_RAGE_128_PR_PRO, | |
777 DEVICE_ATI_RAGE_128_PS_PRO, | |
778 DEVICE_ATI_RAGE_128_PT_PRO, | |
779 DEVICE_ATI_RAGE_128_PU_PRO, | |
780 DEVICE_ATI_RAGE_128_PV_PRO, | |
781 DEVICE_ATI_RAGE_128_PW_PRO, | |
782 DEVICE_ATI_RAGE_128_PX_PRO, | |
3996 | 783 /* Rage128 GL */ |
4107 | 784 DEVICE_ATI_RAGE_128_RE_SG, |
785 DEVICE_ATI_RAGE_128_RF_SG, | |
786 DEVICE_ATI_RAGE_128_RG, | |
787 DEVICE_ATI_RAGE_128_RK_VR, | |
788 DEVICE_ATI_RAGE_128_RL_VR, | |
789 DEVICE_ATI_RAGE_128_SE_4X, | |
790 DEVICE_ATI_RAGE_128_SF_4X, | |
791 DEVICE_ATI_RAGE_128_SG_4X, | |
792 DEVICE_ATI_RAGE_128_4X, | |
793 DEVICE_ATI_RAGE_128_SK_4X, | |
794 DEVICE_ATI_RAGE_128_SL_4X, | |
795 DEVICE_ATI_RAGE_128_SM_4X, | |
796 DEVICE_ATI_RAGE_128_4X2, | |
797 DEVICE_ATI_RAGE_128_PRO, | |
798 DEVICE_ATI_RAGE_128_PRO2, | |
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799 DEVICE_ATI_RAGE_128_PRO3, |
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800 /* these seem to be based on rage 128 instead of mach64 */ |
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801 DEVICE_ATI_RAGE_MOBILITY_M3, |
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802 DEVICE_ATI_RAGE_MOBILITY_M32 |
3996 | 803 #else |
804 /* Radeons (indeed: Rage 256 Pro ;) */ | |
4107 | 805 DEVICE_ATI_RADEON_8500_DV, |
806 DEVICE_ATI_RADEON_MOBILITY_M6, | |
807 DEVICE_ATI_RADEON_MOBILITY_M62, | |
808 DEVICE_ATI_RADEON_MOBILITY_M63, | |
809 DEVICE_ATI_RADEON_QD, | |
810 DEVICE_ATI_RADEON_QE, | |
811 DEVICE_ATI_RADEON_QF, | |
812 DEVICE_ATI_RADEON_QG, | |
813 DEVICE_ATI_RADEON_QL, | |
814 DEVICE_ATI_RADEON_QW, | |
815 DEVICE_ATI_RADEON_VE_QY, | |
816 DEVICE_ATI_RADEON_VE_QZ | |
3996 | 817 #endif |
818 }; | |
819 | |
820 static int find_chip(unsigned chip_id) | |
821 { | |
822 unsigned i; | |
4107 | 823 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) |
3996 | 824 { |
4107 | 825 if(chip_id == ati_card_ids[i]) return i; |
3996 | 826 } |
827 return -1; | |
828 } | |
829 | |
830 pciinfo_t pci_info; | |
831 static int probed=0; | |
832 | |
833 vidix_capability_t def_cap = | |
834 { | |
835 #ifdef RAGE128 | |
836 "BES driver for rage128 cards", | |
837 #else | |
838 "BES driver for radeon cards", | |
839 #endif | |
4327 | 840 "Nick Kurshev", |
3996 | 841 TYPE_OUTPUT | TYPE_FX, |
4191 | 842 { 0, 0, 0, 0 }, |
4282 | 843 2048, |
844 2048, | |
3996 | 845 4, |
846 4, | |
847 -1, | |
4264 | 848 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, |
4134 | 849 VENDOR_ATI, |
3996 | 850 0, |
851 { 0, 0, 0, 0} | |
852 }; | |
853 | |
854 | |
4191 | 855 int vixProbe( int verbose,int force ) |
3996 | 856 { |
857 pciinfo_t lst[MAX_PCI_DEVICES]; | |
858 unsigned i,num_pci; | |
859 int err; | |
4030 | 860 __verbose = verbose; |
3996 | 861 err = pci_scan(lst,&num_pci); |
862 if(err) | |
863 { | |
864 printf(RADEON_MSG" Error occured during pci scan: %s\n",strerror(err)); | |
865 return err; | |
866 } | |
867 else | |
868 { | |
869 err = ENXIO; | |
870 for(i=0;i<num_pci;i++) | |
871 { | |
4107 | 872 if(lst[i].vendor == VENDOR_ATI) |
3996 | 873 { |
874 int idx; | |
4191 | 875 const char *dname; |
3996 | 876 idx = find_chip(lst[i].device); |
4191 | 877 if(idx == -1 && force == PROBE_NORMAL) continue; |
878 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
879 dname = dname ? dname : "Unknown chip"; | |
880 printf(RADEON_MSG" Found chip: %s\n",dname); | |
3996 | 881 #ifndef RAGE128 |
4191 | 882 if(idx != -1) |
883 if(ati_card_ids[idx] == DEVICE_ATI_RADEON_QL || | |
884 ati_card_ids[idx] == DEVICE_ATI_RADEON_8500_DV || | |
885 ati_card_ids[idx] == DEVICE_ATI_RADEON_QW) IsR200 = 1; | |
3996 | 886 #endif |
4193 | 887 if(force > PROBE_NORMAL) |
888 { | |
889 printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
890 if(idx == -1) | |
891 #ifdef RAGE128 | |
4373 | 892 printf(RADEON_MSG" Assuming it as Rage128\n"); |
4193 | 893 #else |
4373 | 894 printf(RADEON_MSG" Assuming it as Radeon1\n"); |
4193 | 895 #endif |
896 } | |
4191 | 897 def_cap.device_id = lst[i].device; |
3996 | 898 err = 0; |
899 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
900 probed=1; | |
901 break; | |
902 } | |
903 } | |
904 } | |
905 if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); | |
906 return err; | |
907 } | |
908 | |
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909 static void radeon_vid_dump_regs( void ); /* forward declaration */ |
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910 |
3996 | 911 int vixInit( void ) |
912 { | |
4477 | 913 int err; |
4012 | 914 if(!probed) |
915 { | |
916 printf(RADEON_MSG" Driver was not probed but is being initializing\n"); | |
917 return EINTR; | |
918 } | |
919 if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; | |
3996 | 920 radeon_ram_size = INREG(CONFIG_MEMSIZE); |
921 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ | |
922 radeon_ram_size &= CONFIG_MEMSIZE_MASK; | |
923 if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; | |
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924 memset(&besr,0,sizeof(bes_registers_t)); |
3996 | 925 radeon_vid_make_default(); |
926 printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); | |
4477 | 927 err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); |
928 if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); | |
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929 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 930 return 0; |
931 } | |
932 | |
933 void vixDestroy( void ) | |
934 { | |
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935 /* remove colorkeying */ |
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936 radeon_fifo_wait(3); |
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937 OUTREG(OV0_GRAPHICS_KEY_CLR, 0); |
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938 OUTREG(OV0_GRAPHICS_KEY_MSK, 0); |
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939 OUTREG(OV0_VID_KEY_CLR, 0); |
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940 OUTREG(OV0_VID_KEY_MSK, 0); |
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941 OUTREG(OV0_KEY_CNTL, 0); |
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942 |
3996 | 943 unmap_phys_mem(radeon_mem_base,radeon_ram_size); |
4855 | 944 unmap_phys_mem(radeon_mmio_base,0xFFFF); |
3996 | 945 } |
946 | |
947 int vixGetCapability(vidix_capability_t *to) | |
948 { | |
949 memcpy(to,&def_cap,sizeof(vidix_capability_t)); | |
950 return 0; | |
951 } | |
952 | |
6483 | 953 /* |
954 Full list of fourcc which are supported by Win2K redeon driver: | |
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955 YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, |
6483 | 956 IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 |
957 */ | |
3996 | 958 uint32_t supported_fourcc[] = |
959 { | |
6483 | 960 IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, |
3996 | 961 IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, |
4455 | 962 IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, |
4429 | 963 IMGFMT_RGB15, IMGFMT_BGR15, |
4416 | 964 IMGFMT_RGB16, IMGFMT_BGR16, |
965 IMGFMT_RGB32, IMGFMT_BGR32 | |
3996 | 966 }; |
967 | |
6483 | 968 inline static int is_supported_fourcc(uint32_t fourcc) |
3996 | 969 { |
6483 | 970 unsigned int i; |
3996 | 971 for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) |
972 { | |
973 if(fourcc==supported_fourcc[i]) return 1; | |
974 } | |
975 return 0; | |
976 } | |
977 | |
978 int vixQueryFourcc(vidix_fourcc_t *to) | |
979 { | |
980 if(is_supported_fourcc(to->fourcc)) | |
981 { | |
982 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
983 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
984 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
985 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
986 VID_DEPTH_32BPP; | |
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987 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
3996 | 988 return 0; |
989 } | |
4015 | 990 else to->depth = to->flags = 0; |
3996 | 991 return ENOSYS; |
992 } | |
993 | |
994 static void radeon_vid_dump_regs( void ) | |
995 { | |
996 size_t i; | |
4015 | 997 printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); |
998 printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); | |
999 printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); | |
1000 printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); | |
1001 printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); | |
4666 | 1002 printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); |
4015 | 1003 printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); |
3996 | 1004 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) |
4015 | 1005 printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); |
1006 printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); | |
3996 | 1007 } |
1008 | |
1009 static void radeon_vid_stop_video( void ) | |
1010 { | |
1011 radeon_engine_idle(); | |
1012 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
1013 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
1014 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
1015 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); | |
1016 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
1017 OUTREG(OV0_TEST, 0); | |
1018 } | |
1019 | |
1020 static void radeon_vid_display_video( void ) | |
1021 { | |
1022 int bes_flags; | |
1023 radeon_fifo_wait(2); | |
1024 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1025 radeon_engine_idle(); | |
1026 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1027 radeon_fifo_wait(15); | |
4666 | 1028 |
1029 /* Shutdown capturing */ | |
1030 OUTREG(FCP_CNTL, FCP_CNTL__GND); | |
1031 OUTREG(CAP0_TRIG_CNTL, 0); | |
1032 | |
4689 | 1033 OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); |
1034 OUTREG(DISP_TEST_DEBUG_CNTL, 0); | |
4666 | 1035 |
3996 | 1036 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
1037 | |
4611 | 1038 if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); |
3996 | 1039 #ifdef RAGE128 |
7493 | 1040 OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | |
1041 (((besr.saturation*31+31000)/2000) << 8) | | |
1042 (((besr.saturation*31+31000)/2000) << 16)); | |
3996 | 1043 #endif |
1044 radeon_fifo_wait(2); | |
4869 | 1045 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1046 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1047 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
3996 | 1048 |
1049 OUTREG(OV0_H_INC, besr.h_inc); | |
1050 OUTREG(OV0_STEP_BY, besr.step_by); | |
1051 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
1052 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
1053 OUTREG(OV0_V_INC, besr.v_inc); | |
1054 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
1055 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); | |
1056 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); | |
1057 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); | |
1058 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); | |
1059 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
1060 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
1061 #ifdef RADEON | |
1062 OUTREG(OV0_BASE_ADDR, besr.base_addr); | |
1063 #endif | |
4930 | 1064 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1065 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1066 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1067 radeon_fifo_wait(9); |
4930 | 1068 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); |
5041 | 1069 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); |
1070 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); | |
3996 | 1071 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); |
1072 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
1073 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
1074 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); | |
1075 | |
6678 | 1076 #ifdef RADEON |
1077 bes_flags = SCALER_ENABLE | | |
1078 SCALER_SMART_SWITCH; | |
1079 // SCALER_HORZ_PICK_NEAREST | | |
1080 // SCALER_VERT_PICK_NEAREST | | |
1081 #endif | |
3996 | 1082 bes_flags = SCALER_ENABLE | |
1083 SCALER_SMART_SWITCH | | |
1084 SCALER_Y2R_TEMP | | |
1085 SCALER_PIX_EXPAND; | |
1086 if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; | |
1087 if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; | |
1088 #ifdef RAGE128 | |
1089 bes_flags |= SCALER_BURST_PER_PLANE; | |
1090 #endif | |
1091 switch(besr.fourcc) | |
1092 { | |
1093 case IMGFMT_RGB15: | |
1094 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
4429 | 1095 case IMGFMT_RGB16: |
3996 | 1096 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; |
4416 | 1097 /* |
3996 | 1098 case IMGFMT_RGB24: |
1099 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
4416 | 1100 */ |
3996 | 1101 case IMGFMT_RGB32: |
1102 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
6483 | 1103 /* 4:1:0 */ |
3996 | 1104 case IMGFMT_IF09: |
1105 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; | |
6483 | 1106 /* 4:0:0 */ |
1107 case IMGFMT_Y800: | |
1108 case IMGFMT_Y8: | |
3996 | 1109 /* 4:2:0 */ |
1110 case IMGFMT_IYUV: | |
1111 case IMGFMT_I420: | |
6483 | 1112 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
3996 | 1113 /* 4:2:2 */ |
4455 | 1114 case IMGFMT_YVYU: |
3996 | 1115 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; |
1116 case IMGFMT_YUY2: | |
1117 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
1118 } | |
1119 OUTREG(OV0_SCALE_CNTL, bes_flags); | |
1120 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
4666 | 1121 if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); |
4030 | 1122 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1123 } |
1124 | |
4456 | 1125 static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
4009 | 1126 { |
4456 | 1127 unsigned pitch,spy,spv,spu; |
1128 spy = spv = spu = 0; | |
1129 switch(spitch->y) | |
1130 { | |
1131 case 16: | |
1132 case 32: | |
1133 case 64: | |
1134 case 128: | |
1135 case 256: spy = spitch->y; break; | |
1136 default: break; | |
1137 } | |
1138 switch(spitch->u) | |
1139 { | |
1140 case 16: | |
1141 case 32: | |
1142 case 64: | |
1143 case 128: | |
1144 case 256: spu = spitch->u; break; | |
1145 default: break; | |
1146 } | |
1147 switch(spitch->v) | |
1148 { | |
1149 case 16: | |
1150 case 32: | |
1151 case 64: | |
1152 case 128: | |
1153 case 256: spv = spitch->v; break; | |
1154 default: break; | |
1155 } | |
4009 | 1156 switch(fourcc) |
1157 { | |
1158 /* 4:2:0 */ | |
1159 case IMGFMT_IYUV: | |
1160 case IMGFMT_YV12: | |
4456 | 1161 case IMGFMT_I420: |
1162 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
1163 else pitch = 32; | |
1164 break; | |
6483 | 1165 /* 4:1:0 */ |
1166 case IMGFMT_IF09: | |
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1167 case IMGFMT_YVU9: |
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1168 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; |
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1169 else pitch = 64; |
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1170 break; |
4456 | 1171 default: |
1172 if(spy >= 16) pitch = spy; | |
1173 else pitch = 16; | |
1174 break; | |
4009 | 1175 } |
1176 return pitch; | |
1177 } | |
1178 | |
3996 | 1179 static int radeon_vid_init_video( vidix_playback_t *config ) |
1180 { | |
4930 | 1181 uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; |
6483 | 1182 int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; |
3996 | 1183 radeon_vid_stop_video(); |
1184 left = config->src.x << 16; | |
1185 top = config->src.y << 16; | |
1186 src_h = config->src.h; | |
1187 src_w = config->src.w; | |
6483 | 1188 is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; |
3996 | 1189 if(config->fourcc == IMGFMT_YV12 || |
1190 config->fourcc == IMGFMT_I420 || | |
1191 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
6483 | 1192 if(config->fourcc == IMGFMT_YVU9 || |
1193 config->fourcc == IMGFMT_IF09) is_410 = 1; | |
1194 if(config->fourcc == IMGFMT_Y800 || | |
1195 config->fourcc == IMGFMT_Y8) is_400 = 1; | |
4416 | 1196 if(config->fourcc == IMGFMT_RGB32 || |
1197 config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; | |
4571 | 1198 if(config->fourcc == IMGFMT_RGB32 || |
1199 config->fourcc == IMGFMT_BGR32 || | |
1200 config->fourcc == IMGFMT_RGB24 || | |
1201 config->fourcc == IMGFMT_BGR24 || | |
1202 config->fourcc == IMGFMT_RGB16 || | |
1203 config->fourcc == IMGFMT_BGR16 || | |
1204 config->fourcc == IMGFMT_RGB15 || | |
1205 config->fourcc == IMGFMT_BGR15) is_rgb = 1; | |
4456 | 1206 best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); |
4415 | 1207 mpitch = best_pitch-1; |
3996 | 1208 switch(config->fourcc) |
1209 { | |
6483 | 1210 /* 4:0:0 */ |
1211 case IMGFMT_Y800: | |
1212 case IMGFMT_Y8: | |
1213 /* 4:1:0 */ | |
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1214 case IMGFMT_YVU9: |
6483 | 1215 case IMGFMT_IF09: |
3996 | 1216 /* 4:2:0 */ |
1217 case IMGFMT_IYUV: | |
1218 case IMGFMT_YV12: | |
4415 | 1219 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; |
4015 | 1220 config->dest.pitch.y = |
1221 config->dest.pitch.u = | |
4415 | 1222 config->dest.pitch.v = best_pitch; |
3996 | 1223 break; |
4416 | 1224 /* RGB 4:4:4:4 */ |
1225 case IMGFMT_RGB32: | |
1226 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
1227 config->dest.pitch.y = | |
1228 config->dest.pitch.u = | |
1229 config->dest.pitch.v = best_pitch; | |
1230 break; | |
3996 | 1231 /* 4:2:2 */ |
4455 | 1232 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ |
4415 | 1233 pitch = ((src_w*2) + mpitch) & ~mpitch; |
3996 | 1234 config->dest.pitch.y = |
1235 config->dest.pitch.u = | |
4415 | 1236 config->dest.pitch.v = best_pitch; |
3996 | 1237 break; |
1238 } | |
1239 dest_w = config->dest.w; | |
1240 dest_h = config->dest.h; | |
1241 if(radeon_is_dbl_scan()) dest_h *= 2; | |
1242 besr.dest_bpp = radeon_vid_get_dbpp(); | |
1243 besr.fourcc = config->fourcc; | |
1244 besr.v_inc = (src_h << 20) / dest_h; | |
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1245 if(radeon_is_interlace()) besr.v_inc *= 2; |
3996 | 1246 h_inc = (src_w << 12) / dest_w; |
1247 step_by = 1; | |
1248 while(h_inc >= (2 << 12)) { | |
1249 step_by++; | |
1250 h_inc >>= 1; | |
1251 } | |
1252 | |
1253 /* keep everything in 16.16 */ | |
4015 | 1254 besr.base_addr = INREG(DISPLAY_BASE_ADDR); |
4666 | 1255 config->offsets[0] = 0; |
4930 | 1256 for(i=1;i<besr.vid_nbufs;i++) |
1257 config->offsets[i] = config->offsets[i-1]+config->frame_size; | |
6483 | 1258 if(is_420 || is_410 || is_400) |
3996 | 1259 { |
1260 uint32_t d1line,d2line,d3line; | |
1261 d1line = top*pitch; | |
6483 | 1262 if(is_420) |
1263 { | |
1264 d2line = src_h*pitch+(d1line>>2); | |
1265 d3line = d2line+((src_h*pitch)>>2); | |
1266 } | |
1267 else | |
1268 if(is_410) | |
1269 { | |
1270 d2line = src_h*pitch+(d1line>>4); | |
1271 d3line = d2line+((src_h*pitch)>>4); | |
1272 } | |
1273 else | |
1274 { | |
1275 d2line = 0; | |
1276 d3line = 0; | |
1277 } | |
3996 | 1278 d1line += (left >> 16) & ~15; |
6483 | 1279 if(is_420) |
1280 { | |
1281 d2line += (left >> 17) & ~15; | |
1282 d3line += (left >> 17) & ~15; | |
1283 } | |
1284 else | |
1285 if(is_410) | |
1286 { | |
1287 d2line += (left >> 18) & ~15; | |
1288 d3line += (left >> 18) & ~15; | |
1289 } | |
3996 | 1290 config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; |
6483 | 1291 if(is_400) |
1292 { | |
1293 config->offset.v = 0; | |
1294 config->offset.u = 0; | |
1295 } | |
1296 else | |
1297 { | |
1298 config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; | |
1299 config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; | |
1300 } | |
4930 | 1301 for(i=0;i<besr.vid_nbufs;i++) |
1302 { | |
1303 besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); | |
6483 | 1304 if(is_400) |
1305 { | |
1306 besr.vid_buf_base_adrs_v[i]=0; | |
1307 besr.vid_buf_base_adrs_u[i]=0; | |
1308 } | |
1309 else | |
1310 { | |
1311 besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
1312 besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
1313 } | |
4930 | 1314 } |
1315 config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; | |
6483 | 1316 if(is_400) |
1317 { | |
1318 config->offset.v = 0; | |
1319 config->offset.u = 0; | |
1320 } | |
1321 else | |
1322 { | |
1323 config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; | |
1324 config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; | |
1325 } | |
3996 | 1326 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
1327 { | |
1328 uint32_t tmp; | |
1329 tmp = config->offset.u; | |
1330 config->offset.u = config->offset.v; | |
1331 config->offset.v = tmp; | |
1332 } | |
1333 } | |
1334 else | |
1335 { | |
1336 config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; | |
4930 | 1337 for(i=0;i<besr.vid_nbufs;i++) |
1338 { | |
1339 besr.vid_buf_base_adrs_y[i] = | |
1340 besr.vid_buf_base_adrs_u[i] = | |
4932 | 1341 besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; |
4930 | 1342 } |
3996 | 1343 } |
1344 | |
1345 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); | |
1346 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1347 ((tmp << 12) & 0xf0000000); | |
1348 | |
1349 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); | |
1350 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | | |
1351 ((tmp << 12) & 0x70000000); | |
1352 tmp = (top & 0x0000ffff) + 0x00018000; | |
1353 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) | |
1354 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
1355 | |
1356 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
6483 | 1357 besr.p23_v_accum_init = (is_420||is_410) ? |
1358 ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) | |
3996 | 1359 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; |
1360 | |
6483 | 1361 leftUV = (left >> (is_410?18:17)) & 15; |
3996 | 1362 left = (left >> 16) & 15; |
4571 | 1363 if(is_rgb && !is_rgb32) h_inc<<=1; |
4416 | 1364 if(is_rgb32) |
4571 | 1365 besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); |
4416 | 1366 else |
6483 | 1367 if(is_410) |
1368 besr.h_inc = h_inc | ((h_inc >> 2) << 16); | |
1369 else | |
4416 | 1370 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
3996 | 1371 besr.step_by = step_by | (step_by << 8); |
1372 besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); | |
1373 besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); | |
1374 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
6483 | 1375 if(is_420 || is_410) |
3996 | 1376 { |
6483 | 1377 src_h = (src_h + 1) >> (is_410?2:1); |
3996 | 1378 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
1379 } | |
1380 else besr.p23_blank_lines_at_top = 0; | |
1381 besr.vid_buf_pitch0_value = pitch; | |
6483 | 1382 besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; |
3996 | 1383 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
6483 | 1384 if (is_410||is_420) src_w>>=is_410?2:1; |
1385 if(is_400) | |
1386 { | |
1387 besr.p2_x_start_end = 0; | |
1388 besr.p3_x_start_end = 0; | |
1389 } | |
1390 else | |
1391 { | |
1392 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
1393 besr.p3_x_start_end = besr.p2_x_start_end; | |
1394 } | |
4869 | 1395 |
3996 | 1396 return 0; |
1397 } | |
1398 | |
4009 | 1399 static void radeon_compute_framesize(vidix_playback_t *info) |
1400 { | |
4666 | 1401 unsigned pitch,awidth,dbpp; |
4456 | 1402 pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); |
4666 | 1403 dbpp = radeon_vid_get_dbpp(); |
4033 | 1404 switch(info->fourcc) |
1405 { | |
1406 case IMGFMT_I420: | |
1407 case IMGFMT_YV12: | |
1408 case IMGFMT_IYUV: | |
4666 | 1409 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); |
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1410 info->frame_size = awidth*(info->src.h+info->src.h/2); |
4033 | 1411 break; |
6483 | 1412 case IMGFMT_Y800: |
1413 case IMGFMT_Y8: | |
1414 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1415 info->frame_size = awidth*info->src.h; | |
1416 break; | |
1417 case IMGFMT_IF09: | |
1418 case IMGFMT_YVU9: | |
1419 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
1420 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
1421 break; | |
4429 | 1422 case IMGFMT_RGB32: |
1423 case IMGFMT_BGR32: | |
4666 | 1424 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); |
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1425 info->frame_size = awidth*info->src.h; |
4429 | 1426 break; |
1427 /* YUY2 YVYU, RGB15, RGB16 */ | |
4666 | 1428 default: |
1429 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
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1430 info->frame_size = awidth*info->src.h; |
4033 | 1431 break; |
1432 } | |
4009 | 1433 } |
1434 | |
3996 | 1435 int vixConfigPlayback(vidix_playback_t *info) |
1436 { | |
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1437 unsigned rgb_size,nfr; |
3996 | 1438 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
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1439 if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; |
4666 | 1440 if(info->num_frames==1) besr.double_buff=0; |
1441 else besr.double_buff=1; | |
4009 | 1442 radeon_compute_framesize(info); |
4930 | 1443 |
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1444 rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); |
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1445 nfr = info->num_frames; |
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1446 for(;nfr>0; nfr--) |
4930 | 1447 { |
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1448 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1449 radeon_overlay_off &= 0xffff0000; |
1450 if(radeon_overlay_off >= (int)rgb_size ) break; | |
1451 } | |
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1452 if(nfr <= 3) |
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1453 { |
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1454 nfr = info->num_frames; |
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1455 for(;nfr>0; nfr--) |
4930 | 1456 { |
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1457 radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; |
4930 | 1458 radeon_overlay_off &= 0xffff0000; |
1459 if(radeon_overlay_off > 0) break; | |
1460 } | |
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1461 } |
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1462 if(nfr <= 0) return EINVAL; |
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1463 info->num_frames = nfr; |
4930 | 1464 besr.vid_nbufs = info->num_frames; |
1465 info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; | |
3996 | 1466 radeon_vid_init_video(info); |
1467 return 0; | |
1468 } | |
1469 | |
1470 int vixPlaybackOn( void ) | |
1471 { | |
1472 radeon_vid_display_video(); | |
1473 return 0; | |
1474 } | |
1475 | |
1476 int vixPlaybackOff( void ) | |
1477 { | |
1478 radeon_vid_stop_video(); | |
1479 return 0; | |
1480 } | |
1481 | |
4033 | 1482 int vixPlaybackFrameSelect(unsigned frame) |
3996 | 1483 { |
4412 | 1484 uint32_t off[6]; |
4930 | 1485 int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; |
4412 | 1486 /* |
1487 buf3-5 always should point onto second buffer for better | |
1488 deinterlacing and TV-in | |
1489 */ | |
4666 | 1490 if(!besr.double_buff) return 0; |
4930 | 1491 if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; |
1492 if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; | |
1493 off[0] = besr.vid_buf_base_adrs_y[frame]; | |
1494 off[1] = besr.vid_buf_base_adrs_v[frame]; | |
1495 off[2] = besr.vid_buf_base_adrs_u[frame]; | |
1496 off[3] = besr.vid_buf_base_adrs_y[prev_frame]; | |
1497 off[4] = besr.vid_buf_base_adrs_v[prev_frame]; | |
1498 off[5] = besr.vid_buf_base_adrs_u[prev_frame]; | |
4855 | 1499 radeon_fifo_wait(8); |
3996 | 1500 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
4666 | 1501 radeon_engine_idle(); |
3996 | 1502 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); |
4412 | 1503 OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); |
1504 OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); | |
1505 OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); | |
4413 | 1506 OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); |
1507 OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); | |
1508 OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); | |
3996 | 1509 OUTREG(OV0_REG_LOAD_CNTL, 0); |
4930 | 1510 if(besr.vid_nbufs == 2) radeon_wait_vsync(); |
4030 | 1511 if(__verbose > 1) radeon_vid_dump_regs(); |
3996 | 1512 return 0; |
1513 } | |
1514 | |
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1515 vidix_video_eq_t equal = |
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1516 { |
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1517 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION |
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1518 #ifndef RAGE128 |
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1519 | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY |
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1520 #endif |
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1521 , |
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1522 0, 0, 0, 0, 0, 0, 0, 0 }; |
3996 | 1523 |
1524 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
1525 { | |
1526 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
1527 return 0; | |
1528 } | |
1529 | |
4229 | 1530 #ifndef RAGE128 |
1531 #define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) | |
1532 #define RTFBrightness(a) (((a)*1.0)/2000.0) | |
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1533 #define RTFIntensity(a) (((a)*1.0)/2000.0) |
4229 | 1534 #define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) |
1535 #define RTFHue(a) (((a)*3.1416)/1000.0) | |
1536 #define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} | |
1537 #endif | |
1538 | |
3996 | 1539 int vixPlaybackSetEq( const vidix_video_eq_t * eq) |
1540 { | |
1541 #ifdef RAGE128 | |
1542 int br,sat; | |
4229 | 1543 #else |
1544 int itu_space; | |
3996 | 1545 #endif |
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1546 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; |
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1547 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; |
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1548 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; |
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1549 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; |
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1550 if(eq->cap & VEQ_CAP_RGB_INTENSITY) |
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1551 { |
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1552 equal.red_intensity = eq->red_intensity; |
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1553 equal.green_intensity = eq->green_intensity; |
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1554 equal.blue_intensity = eq->blue_intensity; |
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1555 } |
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1556 equal.flags = eq->flags; |
3996 | 1557 #ifdef RAGE128 |
1558 br = equal.brightness * 64 / 1000; | |
4229 | 1559 if(br < -64) br = -64; if(br > 63) br = 63; |
4230 | 1560 sat = (equal.saturation + 1000) * 16 / 1000; |
4229 | 1561 if(sat < 0) sat = 0; if(sat > 31) sat = 31; |
3996 | 1562 OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); |
1563 #else | |
4229 | 1564 itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; |
1565 RTFCheckParam(equal.brightness); | |
1566 RTFCheckParam(equal.saturation); | |
1567 RTFCheckParam(equal.contrast); | |
1568 RTFCheckParam(equal.hue); | |
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1569 RTFCheckParam(equal.red_intensity); |
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1570 RTFCheckParam(equal.green_intensity); |
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1571 RTFCheckParam(equal.blue_intensity); |
4229 | 1572 radeon_set_transform(RTFBrightness(equal.brightness), |
1573 RTFContrast(equal.contrast), | |
1574 RTFSaturation(equal.saturation), | |
1575 RTFHue(equal.hue), | |
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1576 RTFIntensity(equal.red_intensity), |
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1577 RTFIntensity(equal.green_intensity), |
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1578 RTFIntensity(equal.blue_intensity), |
4229 | 1579 itu_space); |
3996 | 1580 #endif |
1581 return 0; | |
1582 } | |
1583 | |
4611 | 1584 int vixPlaybackSetDeint( const vidix_deinterlace_t * info) |
1585 { | |
1586 unsigned sflg; | |
1587 switch(info->flags) | |
1588 { | |
1589 default: | |
1590 case CFG_NON_INTERLACED: | |
1591 besr.deinterlace_on = 0; | |
1592 break; | |
1593 case CFG_EVEN_ODD_INTERLACING: | |
1594 case CFG_INTERLACED: | |
1595 besr.deinterlace_on = 1; | |
1596 besr.deinterlace_pattern = 0x900AAAAA; | |
1597 break; | |
1598 case CFG_ODD_EVEN_INTERLACING: | |
1599 besr.deinterlace_on = 1; | |
1600 besr.deinterlace_pattern = 0x00055555; | |
1601 break; | |
1602 case CFG_UNIQUE_INTERLACING: | |
1603 besr.deinterlace_on = 1; | |
1604 besr.deinterlace_pattern = info->deinterlace_pattern; | |
1605 break; | |
1606 } | |
1607 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); | |
1608 radeon_engine_idle(); | |
1609 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
1610 radeon_fifo_wait(15); | |
1611 sflg = INREG(OV0_SCALE_CNTL); | |
1612 if(besr.deinterlace_on) | |
1613 { | |
1614 OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); | |
1615 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); | |
1616 } | |
1617 else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); | |
1618 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
1619 return 0; | |
1620 } | |
1621 | |
1622 int vixPlaybackGetDeint( vidix_deinterlace_t * info) | |
1623 { | |
1624 if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; | |
1625 else | |
1626 { | |
1627 info->flags = CFG_UNIQUE_INTERLACING; | |
1628 info->deinterlace_pattern = besr.deinterlace_pattern; | |
1629 } | |
1630 return 0; | |
1631 } | |
4869 | 1632 |
1633 | |
1634 /* Graphic keys */ | |
1635 static vidix_grkey_t radeon_grkey; | |
1636 | |
1637 static void set_gr_key( void ) | |
1638 { | |
1639 if(radeon_grkey.ckey.op == CKEY_TRUE) | |
1640 { | |
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1641 int dbpp=radeon_vid_get_dbpp(); |
4869 | 1642 besr.ckey_on=1; |
1643 | |
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1644 switch(dbpp) |
4869 | 1645 { |
1646 case 15: | |
1647 besr.graphics_key_clr= | |
1648 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1649 | ((radeon_grkey.ckey.green&0xF8)<<2) | |
1650 | ((radeon_grkey.ckey.red &0xF8)<<7); | |
1651 break; | |
1652 case 16: | |
1653 besr.graphics_key_clr= | |
1654 ((radeon_grkey.ckey.blue &0xF8)>>3) | |
1655 | ((radeon_grkey.ckey.green&0xFC)<<3) | |
1656 | ((radeon_grkey.ckey.red &0xF8)<<8); | |
1657 break; | |
1658 case 24: | |
1659 besr.graphics_key_clr= | |
1660 ((radeon_grkey.ckey.blue &0xFF)) | |
1661 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1662 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1663 break; | |
1664 case 32: | |
1665 besr.graphics_key_clr= | |
1666 ((radeon_grkey.ckey.blue &0xFF)) | |
1667 | ((radeon_grkey.ckey.green&0xFF)<<8) | |
1668 | ((radeon_grkey.ckey.red &0xFF)<<16); | |
1669 break; | |
1670 default: | |
1671 besr.ckey_on=0; | |
1672 besr.graphics_key_msk=0; | |
1673 besr.graphics_key_clr=0; | |
1674 } | |
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1675 #ifdef RAGE128 |
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1676 besr.graphics_key_msk=(1<<dbpp)-1; |
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1677 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; |
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1678 #else |
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1679 besr.graphics_key_msk=besr.graphics_key_clr; |
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1680 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND; |
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1681 #endif |
4869 | 1682 } |
1683 else | |
1684 { | |
1685 besr.ckey_on=0; | |
1686 besr.graphics_key_msk=0; | |
1687 besr.graphics_key_clr=0; | |
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1688 besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; |
4869 | 1689 } |
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1690 radeon_fifo_wait(3); |
4869 | 1691 OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); |
1692 OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1693 OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); | |
1694 } | |
1695 | |
1696 int vixGetGrKeys(vidix_grkey_t *grkey) | |
1697 { | |
1698 memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); | |
1699 return(0); | |
1700 } | |
1701 | |
1702 int vixSetGrKeys(const vidix_grkey_t *grkey) | |
1703 { | |
1704 memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); | |
1705 set_gr_key(); | |
1706 return(0); | |
1707 } |