Mercurial > mplayer.hg
annotate cpudetect.c @ 8477:b5dce4fa1c48
support for exotic norms
author | henry |
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date | Mon, 16 Dec 2002 17:05:49 +0000 |
parents | 1b2fc92980d9 |
children | 9b73b801af55 |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
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17 #ifdef __NetBSD__ |
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18 #include <sys/param.h> |
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19 #include <setjmp.h> |
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20 #endif |
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21 |
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22 #ifdef __FreeBSD__ |
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23 #include <sys/types.h> |
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24 #include <sys/sysctl.h> |
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25 #endif |
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26 |
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27 #ifdef __linux__ |
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28 #include <signal.h> |
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29 #endif |
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30 |
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32 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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33 * help understanding how to use it. Thanks to the Mesa |
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34 * team for SSE support detection and more cpu detect code. |
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35 */ |
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36 |
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37 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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38 |
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39 static void check_os_katmai_support( void ); |
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40 |
2272 | 41 #if 1 |
42 // return TRUE if cpuid supported | |
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43 static int has_cpuid() |
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44 { |
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45 int a, c; |
2272 | 46 |
47 // code from libavcodec: | |
48 __asm__ __volatile__ ( | |
49 /* See if CPUID instruction is supported ... */ | |
50 /* ... Get copies of EFLAGS into eax and ecx */ | |
51 "pushf\n\t" | |
52 "popl %0\n\t" | |
53 "movl %0, %1\n\t" | |
54 | |
55 /* ... Toggle the ID bit in one copy and store */ | |
56 /* to the EFLAGS reg */ | |
57 "xorl $0x200000, %0\n\t" | |
58 "push %0\n\t" | |
59 "popf\n\t" | |
60 | |
61 /* ... Get the (hopefully modified) EFLAGS */ | |
62 "pushf\n\t" | |
63 "popl %0\n\t" | |
64 : "=a" (a), "=c" (c) | |
65 : | |
66 : "cc" | |
67 ); | |
68 | |
69 return (a!=c); | |
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70 } |
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71 #endif |
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72 |
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73 static void |
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74 do_cpuid(unsigned int ax, unsigned int *p) |
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75 { |
2272 | 76 #if 0 |
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77 __asm __volatile( |
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78 "cpuid;" |
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79 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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80 : "0" (ax) |
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81 ); |
2272 | 82 #else |
83 // code from libavcodec: | |
84 __asm __volatile | |
85 ("movl %%ebx, %%esi\n\t" | |
86 "cpuid\n\t" | |
87 "xchgl %%ebx, %%esi" | |
3403 | 88 : "=a" (p[0]), "=S" (p[1]), |
2272 | 89 "=c" (p[2]), "=d" (p[3]) |
90 : "0" (ax)); | |
91 #endif | |
92 | |
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93 } |
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94 |
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95 void GetCpuCaps( CpuCaps *caps) |
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96 { |
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97 unsigned int regs[4]; |
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98 unsigned int regs2[4]; |
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99 |
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100 caps->isX86=1; |
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101 |
3700 | 102 memset(caps, 0, sizeof(*caps)); |
2288 | 103 if (!has_cpuid()) { |
6134 | 104 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 105 return; |
106 } | |
107 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 108 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 109 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 110 if (regs[0]>=0x00000001) |
2280 | 111 { |
2303 | 112 char *tmpstr; |
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113 |
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114 do_cpuid(0x00000001, regs2); |
2301 | 115 |
2303 | 116 tmpstr=GetCpuFriendlyName(regs, regs2); |
5937 | 117 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
2303 | 118 free(tmpstr); |
2301 | 119 |
2288 | 120 caps->cpuType=(regs2[0] >> 8)&0xf; |
121 if(caps->cpuType==0xf){ | |
122 // use extended family (P4, IA64) | |
123 caps->cpuType=8+((regs2[0]>>20)&255); | |
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124 } |
3403 | 125 caps->cpuStepping=regs2[0] & 0xf; |
6135 | 126 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
3403 | 127 caps->cpuType, caps->cpuStepping); |
2288 | 128 |
129 // general feature flags: | |
2272 | 130 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
131 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
132 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 133 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
134 } | |
135 do_cpuid(0x80000000, regs); | |
136 if (regs[0]>=0x80000001) { | |
6134 | 137 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 138 do_cpuid(0x80000001, regs2); |
3840 | 139 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
140 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 141 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
142 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
143 } | |
144 #if 0 | |
5937 | 145 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 146 gCpuCaps.hasMMX, |
147 gCpuCaps.hasMMX2, | |
148 gCpuCaps.hasSSE, | |
149 gCpuCaps.hasSSE2, | |
150 gCpuCaps.has3DNow, | |
151 gCpuCaps.has3DNowExt ); | |
152 #endif | |
153 | |
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154 /* FIXME: Does SSE2 need more OS support, too? */ |
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155 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) |
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156 if (caps->hasSSE) |
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157 check_os_katmai_support(); |
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158 if (!caps->hasSSE) |
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159 caps->hasSSE2 = 0; |
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160 #else |
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161 caps->hasSSE=0; |
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162 caps->hasSSE2 = 0; |
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163 #endif |
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164 // caps->has3DNow=1; |
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165 // caps->hasMMX2 = 0; |
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166 // caps->hasMMX = 0; |
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167 |
4829 | 168 #ifndef HAVE_MMX |
6134 | 169 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 170 caps->hasMMX=0; |
171 #endif | |
172 #ifndef HAVE_MMX2 | |
6134 | 173 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 174 caps->hasMMX2=0; |
175 #endif | |
176 #ifndef HAVE_SSE | |
6134 | 177 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 178 caps->hasSSE=0; |
179 #endif | |
180 #ifndef HAVE_SSE2 | |
6134 | 181 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 182 caps->hasSSE2=0; |
183 #endif | |
184 #ifndef HAVE_3DNOW | |
6134 | 185 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 186 caps->has3DNow=0; |
187 #endif | |
188 #ifndef HAVE_3DNOWEX | |
6134 | 189 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 190 caps->has3DNowExt=0; |
191 #endif | |
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192 } |
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193 |
2301 | 194 |
195 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
196 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
197 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
198 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
199 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
200 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
201 | |
202 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
203 #include "cputable.h" /* get cpuname and cpuvendors */ | |
204 char vendor[17]; | |
2303 | 205 char *retname; |
2301 | 206 int i; |
207 | |
2417 | 208 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 209 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 210 exit(1); |
211 } | |
212 | |
3837 | 213 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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214 |
2301 | 215 for(i=0; i<MAX_VENDORS; i++){ |
216 if(!strcmp(cpuvendors[i].string,vendor)){ | |
217 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
2303 | 218 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 219 } else { |
2303 | 220 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 221 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
222 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
223 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
224 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
225 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
226 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
227 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 228 "to the MPlayer-Developers, so we can add it to the list!\n"); |
229 } | |
230 } | |
231 } | |
232 | |
233 //printf("Detected CPU: %s\n", retname); | |
234 return retname; | |
235 } | |
236 | |
237 #undef CPUID_EXTFAMILY | |
238 #undef CPUID_EXTMODEL | |
239 #undef CPUID_TYPE | |
240 #undef CPUID_FAMILY | |
241 #undef CPUID_MODEL | |
242 #undef CPUID_STEPPING | |
243 | |
244 | |
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245 #ifdef __NetBSD__ |
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246 jmp_buf sseCheckEnv; |
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247 |
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248 void sseCheckHandler(int i) |
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249 { |
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250 longjmp(sseCheckEnv, 1); |
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251 } |
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252 #endif |
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253 |
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254 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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255 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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256 { |
6134 | 257 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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258 |
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259 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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260 * instructions are 3 bytes long. We must increment the instruction |
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261 * pointer manually to avoid repeated execution of the offending |
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262 * instruction. |
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263 * |
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264 * If the SIGILL is caused by a divide-by-zero when unmasked |
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265 * exceptions aren't supported, the SIMD FPU status and control |
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266 * word will be restored at the end of the test, so we don't need |
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267 * to worry about doing it here. Besides, we may not be able to... |
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268 */ |
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269 sc.eip += 3; |
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270 |
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271 gCpuCaps.hasSSE=0; |
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272 } |
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273 |
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274 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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275 { |
6134 | 276 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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277 |
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278 if ( sc.fpstate->magic != 0xffff ) { |
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279 /* Our signal context has the extended FPU state, so reset the |
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280 * divide-by-zero exception mask and clear the divide-by-zero |
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281 * exception bit. |
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282 */ |
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283 sc.fpstate->mxcsr |= 0x00000200; |
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284 sc.fpstate->mxcsr &= 0xfffffffb; |
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285 } else { |
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286 /* If we ever get here, we're completely hosed. |
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287 */ |
6134 | 288 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
289 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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290 } |
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291 } |
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292 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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293 |
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294 /* If we're running on a processor that can do SSE, let's see if we |
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295 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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296 * haven't been configured for a Pentium III but are running on one, |
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297 * and RedHat patched 2.2 kernels that have broken exception handling |
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298 * support for user space apps that do SSE. |
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299 */ |
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300 static void check_os_katmai_support( void ) |
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301 { |
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302 #if defined(__FreeBSD__) |
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303 int has_sse=0, ret; |
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304 size_t len=sizeof(has_sse); |
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305 |
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306 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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307 if (ret || !has_sse) |
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308 gCpuCaps.hasSSE=0; |
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309 |
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310 #elif defined(__NetBSD__) |
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311 #if __NetBSD_Version__ >= 105260000 |
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312 if ( gCpuCaps.hasSSE ) { |
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313 void (*oldHandler)(int); |
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314 |
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315 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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316 |
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317 oldHandler = signal(SIGILL, sseCheckHandler); |
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318 if (setjmp(sseCheckEnv)) { |
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319 gCpuCaps.hasSSE = 0; |
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320 } else { |
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321 __asm__ __volatile__ ( |
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322 "subl $0x10, %esp \n" |
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323 "movups %xmm0, (%esp) \n" |
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324 "emms \n" |
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325 "addl $0x10, %esp \n" |
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326 ); |
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327 } |
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328 signal(SIGILL, oldHandler); |
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329 |
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330 if ( gCpuCaps.hasSSE ) { |
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331 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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332 } else { |
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333 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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334 } |
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335 } |
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336 #else |
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337 gCpuCaps.hasSSE = 0 |
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338 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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339 #endif |
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340 #elif defined(__linux__) |
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341 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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342 struct sigaction saved_sigill; |
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343 struct sigaction saved_sigfpe; |
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344 |
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345 /* Save the original signal handlers. |
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346 */ |
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347 sigaction( SIGILL, NULL, &saved_sigill ); |
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348 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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349 |
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350 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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351 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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352 |
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353 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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354 * supports the extended FPU save and restore required for SSE. If |
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355 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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356 * doesn't support Streaming SIMD Exceptions, even if the processor |
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357 * does. |
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358 */ |
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359 if ( gCpuCaps.hasSSE ) { |
6134 | 360 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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361 |
2272 | 362 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
363 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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364 |
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365 if ( gCpuCaps.hasSSE ) { |
6134 | 366 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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367 } else { |
6134 | 368 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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369 } |
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370 } |
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371 |
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372 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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373 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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374 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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375 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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376 * as expected, we're okay but we need to clean up after it. |
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377 * |
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378 * Are we being too stringent in our requirement that the OS support |
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379 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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380 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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381 * doesn't even support them. We at least know the user-space SSE |
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382 * support is good in kernels that do support unmasked exceptions, |
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383 * and therefore to be safe I'm going to leave this test in here. |
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384 */ |
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385 if ( gCpuCaps.hasSSE ) { |
6134 | 386 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
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387 |
2272 | 388 // test_os_katmai_exception_support(); |
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389 |
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390 if ( gCpuCaps.hasSSE ) { |
6134 | 391 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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392 } else { |
6134 | 393 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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394 } |
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395 } |
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396 |
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397 /* Restore the original signal handlers. |
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398 */ |
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399 sigaction( SIGILL, &saved_sigill, NULL ); |
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400 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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401 |
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402 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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403 * safe to go ahead and hook out the SSE code throughout Mesa. |
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404 */ |
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405 if ( gCpuCaps.hasSSE ) { |
6134 | 406 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
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407 } else { |
6134 | 408 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
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409 } |
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410 #else |
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411 /* We can't use POSIX signal handling to test the availability of |
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412 * SSE, so we disable it by default. |
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413 */ |
5937 | 414 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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415 gCpuCaps.hasSSE=0; |
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416 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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417 #else |
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418 /* Do nothing on other platforms for now. |
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419 */ |
6134 | 420 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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421 gCpuCaps.hasSSE=0; |
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422 #endif /* __linux__ */ |
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423 } |
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424 #else /* ARCH_X86 */ |
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425 |
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426 void GetCpuCaps( CpuCaps *caps) |
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427 { |
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428 caps->cpuType=0; |
3403 | 429 caps->cpuStepping=0; |
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430 caps->hasMMX=0; |
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431 caps->hasMMX2=0; |
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432 caps->has3DNow=0; |
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433 caps->has3DNowExt=0; |
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434 caps->hasSSE=0; |
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435 caps->hasSSE2=0; |
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436 caps->isX86=0; |
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437 } |
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438 #endif /* !ARCH_X86 */ |