Mercurial > mplayer.hg
annotate vidix/drivers/mach64_vid.c @ 5574:bdfd4b72244a
fixing vertical scaling on non mobility cards, this might have overflowed into the horizontal stuff, so perhaps it fixes the horizontal stuff too
author | michael |
---|---|
date | Fri, 12 Apr 2002 12:29:12 +0000 |
parents | 51fcb1e5c96e |
children | 865c1fd6e0b0 |
rev | line source |
---|---|
4691 | 1 /* |
2 mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips | |
3 Copyrights 2002 Nick Kurshev. This file is based on sources from | |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
4866 | 6 WARNING: THIS DRIVER IS IN BETTA STAGE |
4691 | 7 */ |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
13 #include <inttypes.h> | |
14 #include <fcntl.h> | |
15 | |
16 #include "../vidix.h" | |
17 #include "../fourcc.h" | |
18 #include "../../libdha/libdha.h" | |
19 #include "../../libdha/pci_ids.h" | |
20 #include "../../libdha/pci_names.h" | |
21 | |
22 #include "mach64.h" | |
23 | |
24 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ | |
25 | |
26 static void *mach64_mmio_base = 0; | |
27 static void *mach64_mem_base = 0; | |
4721 | 28 static int32_t mach64_overlay_offset = 0; |
4691 | 29 static uint32_t mach64_ram_size = 0; |
4866 | 30 static uint32_t mach64_buffer_base[10][3]; |
31 static int num_mach64_buffers=-1; | |
4876 | 32 static int supports_planar=0; |
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33 static int supports_lcd_v_stretch=0; |
4691 | 34 |
35 pciinfo_t pci_info; | |
36 static int probed = 0; | |
37 static int __verbose = 0; | |
4721 | 38 |
4758 | 39 #define VERBOSE_LEVEL 1 |
40 | |
4721 | 41 typedef struct bes_registers_s |
42 { | |
43 /* base address of yuv framebuffer */ | |
44 uint32_t yuv_base; | |
45 uint32_t fourcc; | |
46 /* YUV BES registers */ | |
47 uint32_t reg_load_cntl; | |
48 uint32_t scale_inc; | |
49 uint32_t y_x_start; | |
50 uint32_t y_x_end; | |
51 uint32_t vid_buf_pitch; | |
52 uint32_t height_width; | |
53 | |
54 uint32_t scale_cntl; | |
55 uint32_t exclusive_horz; | |
56 uint32_t auto_flip_cntl; | |
57 uint32_t filter_cntl; | |
58 uint32_t key_cntl; | |
59 uint32_t test; | |
60 /* Configurable stuff */ | |
61 | |
62 int brightness; | |
63 int saturation; | |
64 | |
65 int ckey_on; | |
66 uint32_t graphics_key_clr; | |
67 uint32_t graphics_key_msk; | |
68 | |
69 int deinterlace_on; | |
70 uint32_t deinterlace_pattern; | |
71 | |
72 } bes_registers_t; | |
73 | |
74 static bes_registers_t besr; | |
75 | |
76 typedef struct video_registers_s | |
77 { | |
78 const char * sname; | |
79 uint32_t name; | |
80 uint32_t value; | |
81 }video_registers_t; | |
82 | |
83 static bes_registers_t besr; | |
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84 |
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85 /* Graphic keys */ |
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86 static vidix_grkey_t mach64_grkey; |
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87 |
4721 | 88 #define DECLARE_VREG(name) { #name, name, 0 } |
89 static video_registers_t vregs[] = | |
90 { | |
91 DECLARE_VREG(OVERLAY_SCALE_INC), | |
92 DECLARE_VREG(OVERLAY_Y_X_START), | |
93 DECLARE_VREG(OVERLAY_Y_X_END), | |
94 DECLARE_VREG(OVERLAY_SCALE_CNTL), | |
95 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), | |
96 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), | |
97 DECLARE_VREG(OVERLAY_TEST), | |
98 DECLARE_VREG(SCALER_BUF_PITCH), | |
99 DECLARE_VREG(SCALER_HEIGHT_WIDTH), | |
100 DECLARE_VREG(SCALER_BUF0_OFFSET), | |
101 DECLARE_VREG(SCALER_BUF0_OFFSET_U), | |
102 DECLARE_VREG(SCALER_BUF0_OFFSET_V), | |
103 DECLARE_VREG(SCALER_BUF1_OFFSET), | |
104 DECLARE_VREG(SCALER_BUF1_OFFSET_U), | |
105 DECLARE_VREG(SCALER_BUF1_OFFSET_V), | |
106 DECLARE_VREG(SCALER_H_COEFF0), | |
107 DECLARE_VREG(SCALER_H_COEFF1), | |
108 DECLARE_VREG(SCALER_H_COEFF2), | |
109 DECLARE_VREG(SCALER_H_COEFF3), | |
110 DECLARE_VREG(SCALER_H_COEFF4), | |
111 DECLARE_VREG(SCALER_COLOUR_CNTL), | |
112 DECLARE_VREG(SCALER_THRESHOLD), | |
113 DECLARE_VREG(VIDEO_FORMAT), | |
114 DECLARE_VREG(VIDEO_CONFIG), | |
115 DECLARE_VREG(VIDEO_SYNC_TEST), | |
116 DECLARE_VREG(VIDEO_SYNC_TEST_B) | |
117 }; | |
118 | |
4691 | 119 /* VIDIX exports */ |
120 | |
121 /* MMIO space*/ | |
122 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
123 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
124 | |
4721 | 125 #define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) |
126 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) | |
127 #define INREG(addr) GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) | |
128 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) | |
4691 | 129 |
130 #define OUTREGP(addr,val,mask) \ | |
131 do { \ | |
132 unsigned int _tmp = INREG(addr); \ | |
133 _tmp &= (mask); \ | |
134 _tmp |= (val); \ | |
135 OUTREG(addr, _tmp); \ | |
136 } while (0) | |
137 | |
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138 static __inline__ int ATIGetMach64LCDReg(int _Index) |
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139 { |
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140 OUTREG8(LCD_INDEX, _Index); |
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141 return INREG(LCD_DATA); |
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142 } |
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143 |
4691 | 144 static __inline__ uint32_t INPLL(uint32_t addr) |
145 { | |
4721 | 146 uint32_t res; |
147 | |
148 /* write addr byte */ | |
149 OUTREG8(CLOCK_CNTL + 1, (addr << 2)); | |
150 /* read the register value */ | |
151 res = INREG(CLOCK_CNTL + 2); | |
152 return res; | |
4691 | 153 } |
154 | |
4721 | 155 static __inline__ void OUTPLL(uint32_t addr,uint32_t val) |
156 { | |
157 /* write addr byte */ | |
158 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); | |
159 /* write the register value */ | |
160 OUTREG(CLOCK_CNTL + 2, val); | |
161 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); | |
162 } | |
163 | |
4691 | 164 #define OUTPLLP(addr,val,mask) \ |
165 do { \ | |
166 unsigned int _tmp = INPLL(addr); \ | |
167 _tmp &= (mask); \ | |
168 _tmp |= (val); \ | |
169 OUTPLL(addr, _tmp); \ | |
170 } while (0) | |
171 | |
4721 | 172 static void mach64_fifo_wait(unsigned n) |
173 { | |
174 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); | |
175 } | |
176 | |
177 static void mach64_wait_for_idle( void ) | |
178 { | |
179 mach64_fifo_wait(16); | |
180 while ((INREG(GUI_STAT) & 1)!= 0); | |
181 } | |
182 | |
4876 | 183 static void mach64_wait_vsync( void ) |
184 { | |
185 int i; | |
186 | |
187 for(i=0; i<2000000; i++) | |
188 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; | |
189 for(i=0; i<2000000; i++) | |
190 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; | |
191 | |
192 } | |
193 | |
4691 | 194 static vidix_capability_t mach64_cap = |
195 { | |
196 "BES driver for Mach64/3DRage cards", | |
4872 | 197 "Nick Kurshev and Michael Niedermayer", |
4691 | 198 TYPE_OUTPUT, |
199 { 0, 0, 0, 0 }, | |
200 2048, | |
201 2048, | |
202 4, | |
203 4, | |
204 -1, | |
205 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
206 VENDOR_ATI, | |
207 -1, | |
208 { 0, 0, 0, 0 } | |
209 }; | |
210 | |
4721 | 211 static uint32_t mach64_vid_get_dbpp( void ) |
212 { | |
213 uint32_t dbpp,retval; | |
214 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; | |
215 switch(dbpp) | |
216 { | |
217 case 1: retval = 4; break; | |
218 case 2: retval = 8; break; | |
219 case 3: retval = 15; break; | |
220 case 4: retval = 16; break; | |
221 case 5: retval = 24; break; | |
222 default: retval=32; break; | |
223 } | |
224 return retval; | |
225 } | |
226 | |
227 static int mach64_is_dbl_scan( void ) | |
228 { | |
229 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; | |
230 } | |
231 | |
232 static int mach64_is_interlace( void ) | |
233 { | |
234 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; | |
235 } | |
236 | |
237 static uint32_t mach64_get_xres( void ) | |
238 { | |
239 /* FIXME: currently we extract that from CRTC!!!*/ | |
240 uint32_t xres,h_total; | |
241 h_total = INREG(CRTC_H_TOTAL_DISP); | |
242 xres = (h_total >> 16) & 0xffff; | |
243 return (xres + 1)*8; | |
244 } | |
245 | |
246 static uint32_t mach64_get_yres( void ) | |
247 { | |
248 /* FIXME: currently we extract that from CRTC!!!*/ | |
249 uint32_t yres,v_total; | |
250 v_total = INREG(CRTC_V_TOTAL_DISP); | |
251 yres = (v_total >> 16) & 0xffff; | |
252 return yres + 1; | |
253 } | |
254 | |
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255 // returns the verical stretch factor in 16.16 |
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256 static int mach64_get_vert_stretch(void) |
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257 { |
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258 int lcd_index; |
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259 int lcd_gen_ctrl; |
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260 int vert_stretching; |
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261 int ext_vert_stretch; |
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262 int ret; |
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263 int yres= mach64_get_yres(); |
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264 |
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265 if(!supports_lcd_etch) return 1<<16; |
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266 |
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267 lcd_index= INREG(LCD_INDEX); |
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268 |
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269 vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); |
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270 if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; |
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271 else |
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272 { |
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273 int panel_size; |
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274 |
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275 ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); |
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276 panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; |
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277 panel_size++; |
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278 |
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279 ret= ((yres<<16) + (panel_size>>1))/panel_size; |
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280 } |
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281 |
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282 // lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); |
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283 |
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284 OUTREG(LCD_INDEX, lcd_index); |
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285 |
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286 if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); |
4872 | 287 |
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288 return ret; |
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289 } |
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290 |
4721 | 291 static void mach64_vid_make_default() |
292 { | |
4872 | 293 mach64_fifo_wait(5); |
4761 | 294 OUTREG(SCALER_COLOUR_CNTL,0x00101000); |
4872 | 295 |
296 besr.ckey_on=0; | |
297 besr.graphics_key_msk=0; | |
298 besr.graphics_key_clr=0; | |
299 | |
300 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
301 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
302 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
303 | |
4721 | 304 } |
305 | |
306 static void mach64_vid_dump_regs( void ) | |
307 { | |
308 size_t i; | |
309 printf("[mach64] *** Begin of DRIVER variables dump ***\n"); | |
310 printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); | |
311 printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); | |
312 printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); | |
313 printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); | |
314 printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); | |
315 printf("[mach64] *** Begin of OV0 registers dump ***\n"); | |
316 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
317 { | |
318 mach64_wait_for_idle(); | |
319 printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
320 } | |
321 printf("[mach64] *** End of OV0 registers dump ***\n"); | |
322 } | |
323 | |
324 | |
4691 | 325 unsigned int vixGetVersion(void) |
326 { | |
327 return(VIDIX_VERSION); | |
328 } | |
329 | |
330 static unsigned short ati_card_ids[] = | |
331 { | |
332 DEVICE_ATI_215CT_MACH64_CT, | |
333 DEVICE_ATI_210888CX_MACH64_CX, | |
334 DEVICE_ATI_210888ET_MACH64_ET, | |
335 DEVICE_ATI_MACH64_VT, | |
336 DEVICE_ATI_210888GX_MACH64_GX, | |
337 DEVICE_ATI_264LT_MACH64_LT, | |
338 DEVICE_ATI_264VT_MACH64_VT, | |
339 DEVICE_ATI_264VT3_MACH64_VT3, | |
340 DEVICE_ATI_264VT4_MACH64_VT4, | |
341 /**/ | |
342 DEVICE_ATI_3D_RAGE_PRO, | |
343 DEVICE_ATI_3D_RAGE_PRO2, | |
344 DEVICE_ATI_3D_RAGE_PRO3, | |
345 DEVICE_ATI_3D_RAGE_PRO4, | |
346 DEVICE_ATI_RAGE_XC, | |
347 DEVICE_ATI_RAGE_XL_AGP, | |
348 DEVICE_ATI_RAGE_XC_AGP, | |
349 DEVICE_ATI_RAGE_XL, | |
350 DEVICE_ATI_3D_RAGE_PRO5, | |
351 DEVICE_ATI_3D_RAGE_PRO6, | |
352 DEVICE_ATI_RAGE_XL2, | |
353 DEVICE_ATI_RAGE_XC2, | |
354 DEVICE_ATI_3D_RAGE_I_II, | |
355 DEVICE_ATI_3D_RAGE_II, | |
356 DEVICE_ATI_3D_RAGE_IIC, | |
357 DEVICE_ATI_3D_RAGE_IIC2, | |
358 DEVICE_ATI_3D_RAGE_IIC3, | |
359 DEVICE_ATI_3D_RAGE_IIC4, | |
360 DEVICE_ATI_3D_RAGE_LT, | |
361 DEVICE_ATI_3D_RAGE_LT2, | |
362 DEVICE_ATI_3D_RAGE_LT_G, | |
363 DEVICE_ATI_3D_RAGE_LT3, | |
364 DEVICE_ATI_RAGE_MOBILITY_P_M, | |
365 DEVICE_ATI_RAGE_MOBILITY_L, | |
366 DEVICE_ATI_3D_RAGE_LT4, | |
367 DEVICE_ATI_3D_RAGE_LT5, | |
368 DEVICE_ATI_RAGE_MOBILITY_P_M2, | |
369 DEVICE_ATI_RAGE_MOBILITY_L2 | |
370 }; | |
371 | |
372 static int find_chip(unsigned chip_id) | |
373 { | |
374 unsigned i; | |
375 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) | |
376 { | |
377 if(chip_id == ati_card_ids[i]) return i; | |
378 } | |
379 return -1; | |
380 } | |
381 | |
382 int vixProbe(int verbose,int force) | |
383 { | |
384 pciinfo_t lst[MAX_PCI_DEVICES]; | |
385 unsigned i,num_pci; | |
386 int err; | |
387 __verbose = verbose; | |
388 err = pci_scan(lst,&num_pci); | |
389 if(err) | |
390 { | |
391 printf("[mach64] Error occured during pci scan: %s\n",strerror(err)); | |
392 return err; | |
393 } | |
394 else | |
395 { | |
396 err = ENXIO; | |
397 for(i=0;i<num_pci;i++) | |
398 { | |
399 if(lst[i].vendor == VENDOR_ATI) | |
400 { | |
401 int idx; | |
402 const char *dname; | |
403 idx = find_chip(lst[i].device); | |
404 if(idx == -1 && force == PROBE_NORMAL) continue; | |
405 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
406 dname = dname ? dname : "Unknown chip"; | |
407 printf("[mach64] Found chip: %s\n",dname); | |
408 if(force > PROBE_NORMAL) | |
409 { | |
410 printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
411 if(idx == -1) | |
412 printf("[mach64] Assuming it as Mach64\n"); | |
413 } | |
414 mach64_cap.device_id = lst[i].device; | |
415 err = 0; | |
416 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
417 probed=1; | |
418 break; | |
419 } | |
420 } | |
421 } | |
422 if(err && verbose) printf("[mach64] Can't find chip\n"); | |
423 return err; | |
424 } | |
425 | |
4721 | 426 static void reset_regs( void ) |
427 { | |
428 size_t i; | |
429 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
430 { | |
431 mach64_fifo_wait(2); | |
4758 | 432 OUTREG(vregs[i].name,0); |
4721 | 433 } |
434 } | |
435 | |
436 | |
4691 | 437 int vixInit(void) |
438 { | |
439 int err; | |
440 if(!probed) | |
441 { | |
442 printf("[mach64] Driver was not probed but is being initializing\n"); | |
443 return EINTR; | |
444 } | |
4721 | 445 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; |
446 mach64_wait_for_idle(); | |
4691 | 447 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; |
448 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; | |
449 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; | |
450 else mach64_ram_size = (mach64_ram_size - 7) * 2048; | |
451 mach64_ram_size *= 0x400; /* KB -> bytes */ | |
452 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; | |
4758 | 453 memset(&besr,0,sizeof(bes_registers_t)); |
4691 | 454 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); |
455 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); | |
456 if(!err) printf("[mach64] Set write-combining type of video memory\n"); | |
4876 | 457 |
458 /* check if planar formats are supported */ | |
459 supports_planar=0; | |
460 mach64_wait_for_idle(); | |
461 mach64_fifo_wait(2); | |
462 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
463 else | |
464 { | |
465 OUTREG(SCALER_BUF0_OFFSET_U, -1); | |
466 | |
467 mach64_wait_vsync(); | |
468 mach64_wait_for_idle(); | |
469 mach64_fifo_wait(2); | |
470 | |
471 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
472 } | |
473 if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); | |
474 else printf("[mach64] Planar YUV formats are not supported :(\n"); | |
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475 |
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476 if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M |
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477 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 |
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478 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L |
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479 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) |
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480 supports_lcd_v_stretch=1; |
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481 else |
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482 supports_lcd_v_stretch=0; |
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|
483 |
4721 | 484 reset_regs(); |
4761 | 485 mach64_vid_make_default(); |
4876 | 486 |
4758 | 487 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4691 | 488 return 0; |
489 } | |
490 | |
491 void vixDestroy(void) | |
492 { | |
493 unmap_phys_mem(mach64_mem_base,mach64_ram_size); | |
4721 | 494 unmap_phys_mem(mach64_mmio_base,0x4000); |
4691 | 495 } |
496 | |
497 int vixGetCapability(vidix_capability_t *to) | |
498 { | |
499 memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); | |
500 return 0; | |
501 } | |
502 | |
4721 | 503 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
504 { | |
505 unsigned pitch,spy,spv,spu; | |
506 spy = spv = spu = 0; | |
507 switch(spitch->y) | |
508 { | |
509 case 16: | |
510 case 32: | |
511 case 64: | |
512 case 128: | |
513 case 256: spy = spitch->y; break; | |
514 default: break; | |
515 } | |
516 switch(spitch->u) | |
517 { | |
518 case 16: | |
519 case 32: | |
520 case 64: | |
521 case 128: | |
522 case 256: spu = spitch->u; break; | |
523 default: break; | |
524 } | |
525 switch(spitch->v) | |
526 { | |
527 case 16: | |
528 case 32: | |
529 case 64: | |
530 case 128: | |
531 case 256: spv = spitch->v; break; | |
532 default: break; | |
533 } | |
534 switch(fourcc) | |
535 { | |
536 /* 4:2:0 */ | |
537 case IMGFMT_IYUV: | |
538 case IMGFMT_YV12: | |
539 case IMGFMT_I420: | |
540 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
541 else pitch = 32; | |
542 break; | |
4872 | 543 case IMGFMT_YVU9: |
544 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; | |
545 else pitch = 64; | |
546 break; | |
4721 | 547 default: |
4722
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|
548 if(spy >= 16) pitch = spy; |
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|
549 else pitch = 16; |
4721 | 550 break; |
551 } | |
552 return pitch; | |
553 } | |
554 | |
555 static void mach64_compute_framesize(vidix_playback_t *info) | |
556 { | |
557 unsigned pitch,awidth; | |
558 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); | |
559 switch(info->fourcc) | |
560 { | |
561 case IMGFMT_I420: | |
562 case IMGFMT_YV12: | |
563 case IMGFMT_IYUV: | |
564 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
565 info->frame_size = awidth*(info->src.h+info->src.h/2); | |
566 break; | |
4872 | 567 case IMGFMT_YVU9: |
568 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
569 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
570 break; | |
571 // case IMGFMT_RGB32: | |
4721 | 572 case IMGFMT_BGR32: |
573 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); | |
574 info->frame_size = (awidth*info->src.h); | |
575 break; | |
576 /* YUY2 YVYU, RGB15, RGB16 */ | |
577 default: | |
578 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
579 info->frame_size = (awidth*info->src.h); | |
580 break; | |
581 } | |
4872 | 582 info->frame_size+=256; // so we have some space for alignment & such |
583 info->frame_size&=~16; | |
4721 | 584 } |
585 | |
586 static void mach64_vid_stop_video( void ) | |
587 { | |
588 mach64_fifo_wait(14); | |
589 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); | |
590 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); | |
591 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); | |
592 OUTREG(SCALER_H_COEFF0, 0x00002000); | |
593 OUTREG(SCALER_H_COEFF1, 0x0D06200D); | |
594 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); | |
595 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); | |
596 OUTREG(SCALER_H_COEFF4, 0x0C14140C); | |
597 OUTREG(VIDEO_FORMAT, 0xB000B); | |
598 OUTREG(OVERLAY_TEST, 0x0); | |
599 } | |
600 | |
601 static void mach64_vid_display_video( void ) | |
602 { | |
603 uint32_t vf; | |
604 mach64_fifo_wait(14); | |
605 | |
606 OUTREG(OVERLAY_Y_X_START, besr.y_x_start); | |
607 OUTREG(OVERLAY_Y_X_END, besr.y_x_end); | |
608 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); | |
609 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); | |
610 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); | |
4866 | 611 OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); |
612 OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); | |
613 OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); | |
614 OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); | |
615 OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); | |
616 OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); | |
4876 | 617 mach64_wait_vsync(); |
618 | |
619 mach64_fifo_wait(4); | |
4758 | 620 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); |
4760 | 621 // OVERLAY_SCALE_CNTL bits & what they seem to affect |
622 // bit 0 no effect | |
623 // bit 1 yuv2rgb coeff related | |
624 // bit 2 horizontal interpolation if 0 | |
625 // bit 3 vertical interpolation if 0 | |
4847 | 626 // bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) |
4760 | 627 // bit 5-6 gamma correction |
628 // bit 7 nothing visible if set | |
629 // bit 8-27 no effect | |
630 // bit 28-31 nothing interresting just crashed my system when i played with them :( | |
4847 | 631 |
4721 | 632 mach64_wait_for_idle(); |
633 vf = INREG(VIDEO_FORMAT); | |
4751 | 634 |
635 // Bits 16-19 seem to select the format | |
4769 | 636 // 0x0 dunno behaves strange |
637 // 0x1 dunno behaves strange | |
638 // 0x2 dunno behaves strange | |
639 // 0x3 BGR15 | |
640 // 0x4 BGR16 | |
641 // 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) | |
642 // 0x6 BGR32 | |
643 // 0x7 BGR32 with somehow mixed even / odd pixels ? | |
644 // 0x8 YYYYUVUV | |
645 // 0x9 YVU9 | |
646 // 0xA YV12 | |
647 // 0xB YUY2 | |
648 // 0xC UYVY | |
4847 | 649 // 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) |
4769 | 650 // 0xE dunno behaves strange |
651 // 0xF dunno behaves strange | |
652 // Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) | |
4751 | 653 // the remaining bits seem to have no effect |
654 | |
4769 | 655 |
4721 | 656 switch(besr.fourcc) |
657 { | |
4769 | 658 /* BGR formats */ |
659 case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; | |
660 case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; | |
661 case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; | |
4721 | 662 /* 4:2:0 */ |
663 case IMGFMT_IYUV: | |
664 case IMGFMT_I420: | |
4769 | 665 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; |
4872 | 666 |
667 case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; | |
4721 | 668 /* 4:2:2 */ |
669 case IMGFMT_YVYU: | |
4769 | 670 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; |
4721 | 671 case IMGFMT_YUY2: |
4769 | 672 default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; |
4721 | 673 } |
4758 | 674 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 675 } |
676 | |
677 static int mach64_vid_init_video( vidix_playback_t *config ) | |
678 { | |
4758 | 679 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; |
4721 | 680 int is_420,best_pitch,mpitch; |
4866 | 681 int src_offset_y, src_offset_u, src_offset_v; |
682 unsigned int i; | |
4872 | 683 |
4721 | 684 mach64_vid_stop_video(); |
4866 | 685 /* warning, if left or top are != 0 this will fail, as the framesize is too small then */ |
686 left = config->src.x; | |
687 top = config->src.y; | |
4721 | 688 src_h = config->src.h; |
689 src_w = config->src.w; | |
690 is_420 = 0; | |
691 if(config->fourcc == IMGFMT_YV12 || | |
692 config->fourcc == IMGFMT_I420 || | |
693 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
694 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); | |
695 mpitch = best_pitch-1; | |
696 switch(config->fourcc) | |
697 { | |
4872 | 698 case IMGFMT_YVU9: |
4721 | 699 /* 4:2:0 */ |
700 case IMGFMT_IYUV: | |
701 case IMGFMT_YV12: | |
702 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; | |
703 config->dest.pitch.y = | |
704 config->dest.pitch.u = | |
705 config->dest.pitch.v = best_pitch; | |
4769 | 706 besr.vid_buf_pitch= pitch; |
4721 | 707 break; |
708 /* RGB 4:4:4:4 */ | |
709 case IMGFMT_RGB32: | |
710 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
711 config->dest.pitch.y = | |
712 config->dest.pitch.u = | |
713 config->dest.pitch.v = best_pitch; | |
4769 | 714 besr.vid_buf_pitch= pitch>>2; |
4721 | 715 break; |
716 /* 4:2:2 */ | |
717 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ | |
718 pitch = ((src_w*2) + mpitch) & ~mpitch; | |
719 config->dest.pitch.y = | |
720 config->dest.pitch.u = | |
721 config->dest.pitch.v = best_pitch; | |
4769 | 722 besr.vid_buf_pitch= pitch>>1; |
4721 | 723 break; |
724 } | |
725 dest_w = config->dest.w; | |
726 dest_h = config->dest.h; | |
727 besr.fourcc = config->fourcc; | |
728 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; | |
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729 if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); |
4861
601e8a796c38
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730 v_inc = src_h * mach64_get_vert_stretch(); |
601e8a796c38
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|
731 |
601e8a796c38
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|
732 if(mach64_is_interlace()) v_inc<<=1; |
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|
733 if(mach64_is_dbl_scan() ) v_inc>>=1; |
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4853
diff
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|
734 v_inc>>=4; // convert 16.16 -> 20.12 |
601e8a796c38
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735 v_inc/= dest_h; |
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changeset
|
736 |
4721 | 737 h_inc = (src_w << (12+ecp)) / dest_w; |
738 /* keep everything in 16.16 */ | |
739 config->offsets[0] = 0; | |
4866 | 740 for(i=1; i<config->num_frames; i++) |
741 config->offsets[i] = config->offsets[i-1] + config->frame_size; | |
742 | |
4872 | 743 /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) |
744 1. the framesize isnt known as the outer src rectangle dimensions arent known | |
745 2. the mach64 needs aligned addresses so it cant work anyway | |
746 -> so we could shift the outer buffer to compensate that but that would mean | |
747 alignment problems for the code which writes into it | |
748 */ | |
749 | |
4721 | 750 if(is_420) |
751 { | |
4866 | 752 config->offset.y= 0; |
4872 | 753 config->offset.u= (pitch*src_h + 15)&~15; |
754 config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; | |
755 | |
4866 | 756 src_offset_y= config->offset.y + top*pitch + left; |
757 src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); | |
758 src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); | |
4872 | 759 |
4721 | 760 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
761 { | |
762 uint32_t tmp; | |
763 tmp = config->offset.u; | |
764 config->offset.u = config->offset.v; | |
765 config->offset.v = tmp; | |
766 } | |
767 } | |
4872 | 768 else if(besr.fourcc == IMGFMT_YVU9) |
769 { | |
770 config->offset.y= 0; | |
771 config->offset.u= (pitch*src_h + 15)&~15; | |
772 config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; | |
773 | |
774 src_offset_y= config->offset.y + top*pitch + left; | |
775 src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); | |
776 src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); | |
777 } | |
4866 | 778 else if(besr.fourcc == IMGFMT_BGR32) |
779 { | |
780 config->offset.y = config->offset.u = config->offset.v = 0; | |
4872 | 781 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); |
4866 | 782 } |
4721 | 783 else |
784 { | |
4866 | 785 config->offset.y = config->offset.u = config->offset.v = 0; |
4872 | 786 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); |
4866 | 787 } |
788 | |
789 num_mach64_buffers= config->num_frames; | |
790 for(i=0; i<config->num_frames; i++) | |
791 { | |
792 mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; | |
793 mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; | |
794 mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; | |
4721 | 795 } |
796 | |
797 leftUV = (left >> 17) & 15; | |
798 left = (left >> 16) & 15; | |
799 besr.scale_inc = ( h_inc << 16 ) | v_inc; | |
4758 | 800 y_pos = config->dest.y; |
801 if(mach64_is_dbl_scan()) y_pos*=2; | |
802 else | |
803 if(mach64_is_interlace()) y_pos/=2; | |
804 besr.y_x_start = y_pos | (config->dest.x << 16); | |
805 y_pos =config->dest.y + dest_h; | |
806 if(mach64_is_dbl_scan()) y_pos*=2; | |
807 else | |
808 if(mach64_is_interlace()) y_pos/=2; | |
809 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); | |
4721 | 810 besr.height_width = ((src_w - left)<<16) | (src_h - top); |
4769 | 811 |
4721 | 812 return 0; |
813 } | |
814 | |
4876 | 815 static int is_supported_fourcc(uint32_t fourcc) |
4721 | 816 { |
4876 | 817 switch(fourcc) |
818 { | |
819 case IMGFMT_YV12: | |
820 case IMGFMT_I420: | |
821 case IMGFMT_YVU9: | |
822 case IMGFMT_IYUV: | |
823 return supports_planar; | |
824 case IMGFMT_YUY2: | |
825 case IMGFMT_UYVY: | |
826 case IMGFMT_BGR15: | |
827 case IMGFMT_BGR16: | |
828 case IMGFMT_BGR32: | |
829 return 1; | |
830 default: | |
831 return 0; | |
832 } | |
4721 | 833 } |
834 | |
4691 | 835 int vixQueryFourcc(vidix_fourcc_t *to) |
836 { | |
4721 | 837 if(is_supported_fourcc(to->fourcc)) |
838 { | |
839 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
840 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
841 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
842 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
843 VID_DEPTH_32BPP; | |
4861
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844 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
4721 | 845 return 0; |
846 } | |
847 else to->depth = to->flags = 0; | |
4691 | 848 return ENOSYS; |
849 } | |
850 | |
851 int vixConfigPlayback(vidix_playback_t *info) | |
852 { | |
4721 | 853 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
4866 | 854 |
4721 | 855 mach64_compute_framesize(info); |
4894
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856 |
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857 if(info->num_frames>4) info->num_frames=4; |
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858 for(;info->num_frames>0; info->num_frames--) |
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859 { |
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860 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; |
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861 mach64_overlay_offset &= 0xffff0000; |
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862 if(mach64_overlay_offset>0) break; |
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863 } |
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864 if(info->num_frames <= 0) return EINVAL; |
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865 |
4721 | 866 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; |
867 mach64_vid_init_video(info); | |
868 return 0; | |
4691 | 869 } |
870 | |
871 int vixPlaybackOn(void) | |
872 { | |
4721 | 873 mach64_vid_display_video(); |
874 return 0; | |
4691 | 875 } |
876 | |
877 int vixPlaybackOff(void) | |
878 { | |
4721 | 879 mach64_vid_stop_video(); |
880 return 0; | |
881 } | |
882 | |
4691 | 883 int vixPlaybackFrameSelect(unsigned int frame) |
884 { | |
4721 | 885 uint32_t off[6]; |
4866 | 886 int i; |
887 int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; | |
888 //printf("Selecting frame %d\n", frame); | |
4721 | 889 /* |
890 buf3-5 always should point onto second buffer for better | |
891 deinterlacing and TV-in | |
892 */ | |
4866 | 893 if(num_mach64_buffers==1) return 0; |
894 | |
895 for(i=0; i<3; i++) | |
4721 | 896 { |
4866 | 897 off[i] = mach64_buffer_base[frame][i]; |
898 off[i+3]= mach64_buffer_base[last_frame][i]; | |
899 } | |
4769 | 900 |
4847 | 901 #if 0 // delay routine so the individual frames can be ssen better |
902 { | |
903 volatile int i=0; | |
904 for(i=0; i<10000000; i++); | |
905 } | |
906 #endif | |
4721 | 907 |
908 mach64_wait_for_idle(); | |
909 mach64_fifo_wait(7); | |
4847 | 910 |
4721 | 911 OUTREG(SCALER_BUF0_OFFSET, off[0]); |
912 OUTREG(SCALER_BUF0_OFFSET_U, off[1]); | |
913 OUTREG(SCALER_BUF0_OFFSET_V, off[2]); | |
914 OUTREG(SCALER_BUF1_OFFSET, off[3]); | |
915 OUTREG(SCALER_BUF1_OFFSET_U, off[4]); | |
916 OUTREG(SCALER_BUF1_OFFSET_V, off[5]); | |
4866 | 917 if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering |
918 | |
4758 | 919 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 920 return 0; |
4691 | 921 } |
4721 | 922 |
923 vidix_video_eq_t equal = | |
924 { | |
925 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | |
926 , | |
927 0, 0, 0, 0, 0, 0, 0, 0 }; | |
928 | |
929 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
930 { | |
931 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
932 return 0; | |
933 } | |
934 | |
935 int vixPlaybackSetEq( const vidix_video_eq_t * eq) | |
936 { | |
937 int br,sat; | |
938 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; | |
939 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; | |
940 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; | |
941 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; | |
942 if(eq->cap & VEQ_CAP_RGB_INTENSITY) | |
943 { | |
944 equal.red_intensity = eq->red_intensity; | |
945 equal.green_intensity = eq->green_intensity; | |
946 equal.blue_intensity = eq->blue_intensity; | |
947 } | |
948 equal.flags = eq->flags; | |
949 br = equal.brightness * 64 / 1000; | |
950 if(br < -64) br = -64; if(br > 63) br = 63; | |
951 sat = (equal.saturation + 1000) * 16 / 1000; | |
952 if(sat < 0) sat = 0; if(sat > 31) sat = 31; | |
953 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
954 return 0; | |
955 } | |
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956 |
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957 int vixGetGrKeys(vidix_grkey_t *grkey) |
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958 { |
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959 memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); |
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960 return(0); |
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961 } |
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962 |
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963 int vixSetGrKeys(const vidix_grkey_t *grkey) |
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964 { |
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965 memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); |
4872 | 966 |
967 if(mach64_grkey.ckey.op == CKEY_TRUE) | |
968 { | |
969 besr.ckey_on=1; | |
970 | |
971 switch(mach64_vid_get_dbpp()) | |
972 { | |
973 case 15: | |
974 besr.graphics_key_msk=0x7FFF; | |
975 besr.graphics_key_clr= | |
976 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
977 | ((mach64_grkey.ckey.green&0xF8)<<2) | |
978 | ((mach64_grkey.ckey.red &0xF8)<<7); | |
979 break; | |
980 case 16: | |
981 besr.graphics_key_msk=0xFFFF; | |
982 besr.graphics_key_clr= | |
983 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
984 | ((mach64_grkey.ckey.green&0xFC)<<3) | |
985 | ((mach64_grkey.ckey.red &0xF8)<<8); | |
986 break; | |
987 case 24: | |
988 besr.graphics_key_msk=0xFFFFFF; | |
989 besr.graphics_key_clr= | |
990 ((mach64_grkey.ckey.blue &0xFF)) | |
991 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
992 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
993 break; | |
994 case 32: | |
995 besr.graphics_key_msk=0xFFFFFF; | |
996 besr.graphics_key_clr= | |
997 ((mach64_grkey.ckey.blue &0xFF)) | |
998 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
999 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1000 break; | |
1001 default: | |
1002 besr.ckey_on=0; | |
1003 besr.graphics_key_msk=0; | |
1004 besr.graphics_key_clr=0; | |
1005 } | |
1006 } | |
1007 else | |
1008 { | |
1009 besr.ckey_on=0; | |
1010 besr.graphics_key_msk=0; | |
1011 besr.graphics_key_clr=0; | |
1012 } | |
1013 | |
1014 mach64_fifo_wait(4); | |
1015 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
1016 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1017 // OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); | |
1018 // OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); | |
1019 if(besr.ckey_on) | |
1020 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
1021 else | |
1022 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); | |
1023 | |
4861
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1024 return(0); |
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1025 } |