Mercurial > mplayer.hg
annotate cpudetect.c @ 8802:dc9f50b54a87
ehh.. 10l again
author | arpi |
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date | Sun, 05 Jan 2003 15:45:55 +0000 |
parents | 9b73b801af55 |
children | 778989dba3a2 |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
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17 #ifdef __NetBSD__ |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
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23 #ifdef __FreeBSD__ |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
2272 | 32 //#define X86_FXSR_MAGIC |
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33 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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34 * help understanding how to use it. Thanks to the Mesa |
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35 * team for SSE support detection and more cpu detect code. |
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36 */ |
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37 |
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38 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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39 |
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40 static void check_os_katmai_support( void ); |
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41 |
2272 | 42 #if 1 |
43 // return TRUE if cpuid supported | |
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44 static int has_cpuid() |
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45 { |
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46 int a, c; |
2272 | 47 |
48 // code from libavcodec: | |
49 __asm__ __volatile__ ( | |
50 /* See if CPUID instruction is supported ... */ | |
51 /* ... Get copies of EFLAGS into eax and ecx */ | |
52 "pushf\n\t" | |
53 "popl %0\n\t" | |
54 "movl %0, %1\n\t" | |
55 | |
56 /* ... Toggle the ID bit in one copy and store */ | |
57 /* to the EFLAGS reg */ | |
58 "xorl $0x200000, %0\n\t" | |
59 "push %0\n\t" | |
60 "popf\n\t" | |
61 | |
62 /* ... Get the (hopefully modified) EFLAGS */ | |
63 "pushf\n\t" | |
64 "popl %0\n\t" | |
65 : "=a" (a), "=c" (c) | |
66 : | |
67 : "cc" | |
68 ); | |
69 | |
70 return (a!=c); | |
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71 } |
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72 #endif |
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73 |
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74 static void |
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75 do_cpuid(unsigned int ax, unsigned int *p) |
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76 { |
2272 | 77 #if 0 |
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78 __asm __volatile( |
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79 "cpuid;" |
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80 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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81 : "0" (ax) |
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82 ); |
2272 | 83 #else |
84 // code from libavcodec: | |
85 __asm __volatile | |
86 ("movl %%ebx, %%esi\n\t" | |
87 "cpuid\n\t" | |
88 "xchgl %%ebx, %%esi" | |
3403 | 89 : "=a" (p[0]), "=S" (p[1]), |
2272 | 90 "=c" (p[2]), "=d" (p[3]) |
91 : "0" (ax)); | |
92 #endif | |
93 | |
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94 } |
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95 |
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96 void GetCpuCaps( CpuCaps *caps) |
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97 { |
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98 unsigned int regs[4]; |
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99 unsigned int regs2[4]; |
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100 |
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101 caps->isX86=1; |
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102 |
3700 | 103 memset(caps, 0, sizeof(*caps)); |
2288 | 104 if (!has_cpuid()) { |
6134 | 105 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 106 return; |
107 } | |
108 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 109 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 110 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 111 if (regs[0]>=0x00000001) |
2280 | 112 { |
2303 | 113 char *tmpstr; |
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114 |
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115 do_cpuid(0x00000001, regs2); |
2301 | 116 |
2303 | 117 tmpstr=GetCpuFriendlyName(regs, regs2); |
5937 | 118 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
2303 | 119 free(tmpstr); |
2301 | 120 |
2288 | 121 caps->cpuType=(regs2[0] >> 8)&0xf; |
122 if(caps->cpuType==0xf){ | |
123 // use extended family (P4, IA64) | |
124 caps->cpuType=8+((regs2[0]>>20)&255); | |
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125 } |
3403 | 126 caps->cpuStepping=regs2[0] & 0xf; |
6135 | 127 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
3403 | 128 caps->cpuType, caps->cpuStepping); |
2288 | 129 |
130 // general feature flags: | |
2272 | 131 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
132 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
133 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 134 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
135 } | |
136 do_cpuid(0x80000000, regs); | |
137 if (regs[0]>=0x80000001) { | |
6134 | 138 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 139 do_cpuid(0x80000001, regs2); |
3840 | 140 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
141 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 142 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
143 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
144 } | |
145 #if 0 | |
5937 | 146 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 147 gCpuCaps.hasMMX, |
148 gCpuCaps.hasMMX2, | |
149 gCpuCaps.hasSSE, | |
150 gCpuCaps.hasSSE2, | |
151 gCpuCaps.has3DNow, | |
152 gCpuCaps.has3DNowExt ); | |
153 #endif | |
154 | |
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155 /* FIXME: Does SSE2 need more OS support, too? */ |
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156 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) |
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157 if (caps->hasSSE) |
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158 check_os_katmai_support(); |
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159 if (!caps->hasSSE) |
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160 caps->hasSSE2 = 0; |
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161 #else |
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162 caps->hasSSE=0; |
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163 caps->hasSSE2 = 0; |
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164 #endif |
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165 // caps->has3DNow=1; |
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166 // caps->hasMMX2 = 0; |
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167 // caps->hasMMX = 0; |
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168 |
4829 | 169 #ifndef HAVE_MMX |
6134 | 170 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 171 caps->hasMMX=0; |
172 #endif | |
173 #ifndef HAVE_MMX2 | |
6134 | 174 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 175 caps->hasMMX2=0; |
176 #endif | |
177 #ifndef HAVE_SSE | |
6134 | 178 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 179 caps->hasSSE=0; |
180 #endif | |
181 #ifndef HAVE_SSE2 | |
6134 | 182 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 183 caps->hasSSE2=0; |
184 #endif | |
185 #ifndef HAVE_3DNOW | |
6134 | 186 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 187 caps->has3DNow=0; |
188 #endif | |
189 #ifndef HAVE_3DNOWEX | |
6134 | 190 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 191 caps->has3DNowExt=0; |
192 #endif | |
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193 } |
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194 |
2301 | 195 |
196 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
197 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
198 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
199 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
200 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
201 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
202 | |
203 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
204 #include "cputable.h" /* get cpuname and cpuvendors */ | |
205 char vendor[17]; | |
2303 | 206 char *retname; |
2301 | 207 int i; |
208 | |
2417 | 209 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 210 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 211 exit(1); |
212 } | |
213 | |
3837 | 214 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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215 |
2301 | 216 for(i=0; i<MAX_VENDORS; i++){ |
217 if(!strcmp(cpuvendors[i].string,vendor)){ | |
218 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
2303 | 219 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 220 } else { |
2303 | 221 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 222 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
223 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
224 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
225 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
226 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
227 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
228 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 229 "to the MPlayer-Developers, so we can add it to the list!\n"); |
230 } | |
231 } | |
232 } | |
233 | |
234 //printf("Detected CPU: %s\n", retname); | |
235 return retname; | |
236 } | |
237 | |
238 #undef CPUID_EXTFAMILY | |
239 #undef CPUID_EXTMODEL | |
240 #undef CPUID_TYPE | |
241 #undef CPUID_FAMILY | |
242 #undef CPUID_MODEL | |
243 #undef CPUID_STEPPING | |
244 | |
245 | |
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246 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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247 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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248 { |
6134 | 249 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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250 |
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251 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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252 * instructions are 3 bytes long. We must increment the instruction |
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253 * pointer manually to avoid repeated execution of the offending |
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254 * instruction. |
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255 * |
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256 * If the SIGILL is caused by a divide-by-zero when unmasked |
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257 * exceptions aren't supported, the SIMD FPU status and control |
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258 * word will be restored at the end of the test, so we don't need |
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259 * to worry about doing it here. Besides, we may not be able to... |
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260 */ |
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261 sc.eip += 3; |
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262 |
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263 gCpuCaps.hasSSE=0; |
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264 } |
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265 |
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266 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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267 { |
6134 | 268 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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269 |
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270 if ( sc.fpstate->magic != 0xffff ) { |
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271 /* Our signal context has the extended FPU state, so reset the |
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272 * divide-by-zero exception mask and clear the divide-by-zero |
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273 * exception bit. |
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274 */ |
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275 sc.fpstate->mxcsr |= 0x00000200; |
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276 sc.fpstate->mxcsr &= 0xfffffffb; |
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277 } else { |
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278 /* If we ever get here, we're completely hosed. |
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279 */ |
6134 | 280 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
281 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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282 } |
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283 } |
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284 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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285 |
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286 /* If we're running on a processor that can do SSE, let's see if we |
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287 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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288 * haven't been configured for a Pentium III but are running on one, |
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289 * and RedHat patched 2.2 kernels that have broken exception handling |
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290 * support for user space apps that do SSE. |
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291 */ |
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292 static void check_os_katmai_support( void ) |
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293 { |
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294 #if defined(__FreeBSD__) |
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295 int has_sse=0, ret; |
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296 size_t len=sizeof(has_sse); |
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297 |
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298 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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299 if (ret || !has_sse) |
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300 gCpuCaps.hasSSE=0; |
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301 |
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302 #elif defined(__NetBSD__) |
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303 #if __NetBSD_Version__ >= 105250000 |
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304 int has_sse, has_sse2, ret, mib[2]; |
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305 size_t varlen; |
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306 |
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307 mib[0] = CTL_MACHDEP; |
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308 mib[1] = CPU_SSE; |
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309 varlen = sizeof(has_sse); |
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310 |
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311 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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312 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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313 if (ret < 0 || !has_sse) { |
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314 gCpuCaps.hasSSE=0; |
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315 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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316 } else { |
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317 gCpuCaps.hasSSE=1; |
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318 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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319 } |
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320 |
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321 mib[1] = CPU_SSE2; |
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322 varlen = sizeof(has_sse2); |
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323 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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324 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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325 if (ret < 0 || !has_sse2) { |
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326 gCpuCaps.hasSSE2=0; |
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327 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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328 } else { |
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329 gCpuCaps.hasSSE2=1; |
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330 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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331 } |
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332 #else |
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333 gCpuCaps.hasSSE = 0; |
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334 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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335 #endif |
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336 #elif defined(__linux__) |
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337 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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338 struct sigaction saved_sigill; |
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339 struct sigaction saved_sigfpe; |
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340 |
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341 /* Save the original signal handlers. |
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342 */ |
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343 sigaction( SIGILL, NULL, &saved_sigill ); |
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344 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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345 |
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346 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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347 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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348 |
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349 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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350 * supports the extended FPU save and restore required for SSE. If |
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351 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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352 * doesn't support Streaming SIMD Exceptions, even if the processor |
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353 * does. |
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354 */ |
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355 if ( gCpuCaps.hasSSE ) { |
6134 | 356 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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357 |
2272 | 358 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
359 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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360 |
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361 if ( gCpuCaps.hasSSE ) { |
6134 | 362 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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363 } else { |
6134 | 364 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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365 } |
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366 } |
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367 |
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368 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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369 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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370 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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371 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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372 * as expected, we're okay but we need to clean up after it. |
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373 * |
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374 * Are we being too stringent in our requirement that the OS support |
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375 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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376 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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377 * doesn't even support them. We at least know the user-space SSE |
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378 * support is good in kernels that do support unmasked exceptions, |
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379 * and therefore to be safe I'm going to leave this test in here. |
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380 */ |
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381 if ( gCpuCaps.hasSSE ) { |
6134 | 382 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
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383 |
2272 | 384 // test_os_katmai_exception_support(); |
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385 |
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386 if ( gCpuCaps.hasSSE ) { |
6134 | 387 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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388 } else { |
6134 | 389 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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390 } |
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391 } |
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392 |
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393 /* Restore the original signal handlers. |
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394 */ |
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395 sigaction( SIGILL, &saved_sigill, NULL ); |
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396 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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397 |
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398 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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399 * safe to go ahead and hook out the SSE code throughout Mesa. |
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400 */ |
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401 if ( gCpuCaps.hasSSE ) { |
6134 | 402 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
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403 } else { |
6134 | 404 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
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405 } |
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406 #else |
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407 /* We can't use POSIX signal handling to test the availability of |
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408 * SSE, so we disable it by default. |
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409 */ |
5937 | 410 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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411 gCpuCaps.hasSSE=0; |
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412 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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413 #else |
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414 /* Do nothing on other platforms for now. |
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415 */ |
6134 | 416 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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417 gCpuCaps.hasSSE=0; |
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418 #endif /* __linux__ */ |
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419 } |
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420 #else /* ARCH_X86 */ |
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421 |
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422 void GetCpuCaps( CpuCaps *caps) |
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423 { |
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424 caps->cpuType=0; |
3403 | 425 caps->cpuStepping=0; |
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426 caps->hasMMX=0; |
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427 caps->hasMMX2=0; |
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428 caps->has3DNow=0; |
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429 caps->has3DNowExt=0; |
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430 caps->hasSSE=0; |
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431 caps->hasSSE2=0; |
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432 caps->isX86=0; |
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433 } |
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434 #endif /* !ARCH_X86 */ |