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1 /*
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2 * drivers/video/radeonfb.c
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3 * framebuffer driver for ATI Radeon chipset video boards
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4 *
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5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
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6 *
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7 *
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8 * ChangeLog:
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9 * 2000-08-03 initial version 0.0.1
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10 * 2000-09-10 more bug fixes, public release 0.0.5
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11 * 2001-02-19 mode bug fixes, 0.0.7
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12 * 2001-07-05 fixed scrolling issues, engine initialization,
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13 * and minor mode tweaking, 0.0.9
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14 *
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1912
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15 * 2001-09-07 Radeon VE support
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1913
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16 * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
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17 * (limitations: on dualhead Radeons (VE, M6, M7)
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18 * driver works only on second head (DVI port).
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19 * TVout is not supported too. M6 & M7 chips
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20 * currently are not supported. Driver has a lot
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21 * of other bugs. Probably they can be solved by
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22 * importing XFree86 code, which has ATI's support).,
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23 * 0.0.11
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24 * 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
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25 * console switching fixes, blanking fixes,
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26 * 0.1.0-ve.0
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27 * 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>),
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28 * Fixed bug of rom bios detection on VE (by NK),
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29 * Minor code cleanup (by NK),
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30 * Enable CRT port on VE (by NK),
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31 * Disable SURFACE_CNTL because mplayer doesn't work
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32 * propertly (by NK)
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33 * 0.1.0-ve.1
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34 * 2001-09-25 MTRR support (by NK)
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35 * 0.1.0-ve.2
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36 * Special thanks to ATI DevRel team for their hardware donations.
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37 *
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38 * LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in
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39 * dual monitor configuration. TVout is not supported too.
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40 * Probably these problems can be solved by importing XFree86 code, which
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41 * has ATI's support.
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42 *
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43 * Mini-HOWTO: This driver doesn't accept any options. It only switches your
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44 * video card to graphics mode. Standard way to change video modes and other
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45 * video attributes is using 'fbset' utility.
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46 * Sample:
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47 *
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48 * #!/bin/sh
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49 * fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767
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50 *
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51 */
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52
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1966
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53 #define RADEON_VERSION "0.1.0-ve.2"
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54
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55 #include <linux/config.h>
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56 #include <linux/module.h>
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57 #include <linux/kernel.h>
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58 #include <linux/errno.h>
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59 #include <linux/string.h>
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60 #include <linux/mm.h>
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61 #include <linux/tty.h>
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1966
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62 #include <linux/slab.h>
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63 #include <linux/delay.h>
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64 #include <linux/fb.h>
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65 #include <linux/console.h>
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66 #include <linux/selection.h>
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67 #include <linux/ioport.h>
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68 #include <linux/init.h>
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69 #include <linux/pci.h>
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2142
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70 #include <linux/unistd.h>
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71
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72 #include <asm/io.h>
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73
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74 #include <video/fbcon.h>
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75 #include <video/fbcon-cfb8.h>
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76 #include <video/fbcon-cfb16.h>
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77 #include <video/fbcon-cfb24.h>
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78 #include <video/fbcon-cfb32.h>
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79
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80 #ifdef CONFIG_MTRR
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81 #include <asm/mtrr.h>
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82 #endif
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83
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84 #include "radeon.h"
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85
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86
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87 #define DEBUG 0
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88
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89 #if DEBUG
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90 #define RTRACE printk
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91 #else
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92 #define RTRACE(...) ((void)0)
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93 #endif
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94
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95
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96
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97 enum radeon_chips {
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98 RADEON_QD,
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99 RADEON_QE,
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100 RADEON_QF,
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101 RADEON_QG,
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102 RADEON_QY,
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103 RADEON_QZ,
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104 RADEON_LY,
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105 RADEON_LZ,
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106 RADEON_LW,
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107 R200_QL,
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108 RV200_QW
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109 };
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110
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111 enum radeon_montype
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112 {
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113 MT_NONE,
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114 MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
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115 MT_LCD, /* Liquid Crystal Display */
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116 MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
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117 MT_CTV, /* Composite TV out (not in VE) */
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118 MT_STV /* S-Video TV out (probably in VE only) */
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119 };
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120
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121 enum radeon_ddctype
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122 {
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123 DDC_NONE_DETECTED,
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124 DDC_MONID,
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125 DDC_DVI,
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126 DDC_VGA,
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127 DDC_CRT2
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128 };
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129
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130 enum radeon_connectortype
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131 {
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132 CONNECTOR_NONE,
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133 CONNECTOR_PROPRIETARY,
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134 CONNECTOR_CRT,
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135 CONNECTOR_DVI_I,
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136 CONNECTOR_DVI_D
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137 };
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138
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139 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
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140 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
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141 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
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142 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
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143 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
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144 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
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145 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
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146 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
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147 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
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148 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
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149 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_R200_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, R200_QL},
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150 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RV200_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RV200_QW},
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151 { 0, }
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152 };
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153 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
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154
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155
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156 typedef struct {
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157 u16 reg;
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158 u32 val;
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159 } reg_val;
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160
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161
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162 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
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163
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164 typedef struct {
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165 u8 clock_chip_type;
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166 u8 struct_size;
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167 u8 accelerator_entry;
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168 u8 VGA_entry;
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169 u16 VGA_table_offset;
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170 u16 POST_table_offset;
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171 u16 XCLK;
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172 u16 MCLK;
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173 u8 num_PLL_blocks;
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174 u8 size_PLL_blocks;
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175 u16 PCLK_ref_freq;
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176 u16 PCLK_ref_divider;
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177 u32 PCLK_min_freq;
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178 u32 PCLK_max_freq;
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179 u16 MCLK_ref_freq;
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180 u16 MCLK_ref_divider;
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181 u32 MCLK_min_freq;
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182 u32 MCLK_max_freq;
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183 u16 XCLK_ref_freq;
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184 u16 XCLK_ref_divider;
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185 u32 XCLK_min_freq;
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186 u32 XCLK_max_freq;
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187 } __attribute__ ((packed)) PLL_BLOCK;
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188
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189
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190 struct pll_info {
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191 int ppll_max;
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192 int ppll_min;
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193 int xclk;
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194 int ref_div;
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195 int ref_clk;
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196 };
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197
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198
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199 struct ram_info {
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200 int ml;
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201 int mb;
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202 int trcd;
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203 int trp;
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204 int twr;
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205 int cl;
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206 int tr2w;
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207 int loop_latency;
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208 int rloop;
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209 };
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210
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211
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212 struct radeon_regs {
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213 /* Common registers */
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214 u32 ovr_clr;
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215 u32 ovr_wid_left_right;
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216 u32 ovr_wid_top_bottom;
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217 u32 ov0_scale_cntl;
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218 u32 mpp_tb_config;
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219 u32 mpp_gp_config;
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220 u32 subpic_cntl;
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221 u32 viph_control;
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222 u32 i2c_cntl_1;
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223 u32 gen_int_cntl;
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224 u32 cap0_trig_cntl;
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225 u32 cap1_trig_cntl;
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226 u32 bus_cntl;
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227 /* Other registers to save for VT switches */
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228 u32 dp_datatype;
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229 u32 rbbm_soft_reset;
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230 u32 clock_cntl_index;
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231 u32 amcgpio_en_reg;
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232 u32 amcgpio_mask;
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233 /* CRTC registers */
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234 u32 crtc_gen_cntl;
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235 u32 crtc_ext_cntl;
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236 u32 dac_cntl;
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237 u32 crtc_h_total_disp;
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238 u32 crtc_h_sync_strt_wid;
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239 u32 crtc_v_total_disp;
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240 u32 crtc_v_sync_strt_wid;
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241 u32 crtc_offset;
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242 u32 crtc_offset_cntl;
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243 u32 crtc_pitch;
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244 /* CRTC2 registers */
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245 u32 crtc2_gen_cntl;
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246 u32 dac2_cntl;
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247 u32 disp_output_cntl;
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248 u32 crtc2_h_total_disp;
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249 u32 crtc2_h_sync_strt_wid;
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250 u32 crtc2_v_total_disp;
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251 u32 crtc2_v_sync_strt_wid;
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252 u32 crtc2_offset;
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253 u32 crtc2_offset_cntl;
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254 u32 crtc2_pitch;
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255 /* Flat panel registers */
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256 u32 fp_crtc_h_total_disp;
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257 u32 fp_crtc_v_total_disp;
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258 u32 fp_gen_cntl;
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259 u32 fp_h_sync_strt_wid;
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260 u32 fp_horz_stretch;
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261 u32 fp_panel_cntl;
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262 u32 fp_v_sync_strt_wid;
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263 u32 fp_vert_stretch;
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264 u32 lvds_gen_cntl;
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265 u32 lvds_pll_cntl;
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266 u32 tmds_crc;
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267 /* DDA registers */
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268 u32 dda_config;
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269 u32 dda_on_off;
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270
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271 /* Computed values for PLL */
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272 u32 dot_clock_freq;
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273 u32 pll_output_freq;
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274 int feedback_div;
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275 int post_div;
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276 /* PLL registers */
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277 u32 ppll_ref_div;
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278 u32 ppll_div_3;
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279 u32 htotal_cntl;
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280 /* Computed values for PLL2 */
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281 u32 dot_clock_freq_2;
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282 u32 pll_output_freq_2;
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283 int feedback_div_2;
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284 int post_div_2;
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285 /* PLL2 registers */
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286 u32 p2pll_ref_div;
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287 u32 p2pll_div_0;
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288 u32 htotal_cntl2;
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289 /* Pallet */
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290 int palette_valid;
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291 u32 palette[256];
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292 u32 palette2[256];
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293
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294 u32 flags;
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295 u32 pix_clock;
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296 int xres, yres;
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297 int bpp;
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298 #if defined(__BIG_ENDIAN)
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299 u32 surface_cntl;
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300 #endif
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301 };
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302
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303
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304 struct radeonfb_info {
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305 struct fb_info info;
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306
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307 struct radeon_regs state;
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308 struct radeon_regs init_state;
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309
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310 char name[17];
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311 char ram_type[12];
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312
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313 int hasCRTC2;
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314 int crtDispType;
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315 int dviDispType;
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316 int hasTVout;
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317 int isM7;
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318 int isM6;
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319 int isR200;
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320 int theatre_num;
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321 /* Computed values for FPs */
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322 int PanelXRes;
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323 int PanelYRes;
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324 int HOverPlus;
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325 int HSyncWidth;
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326 int HBlank;
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327 int VOverPlus;
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328 int VSyncWidth;
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329 int VBlank;
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330 int PanelPwrDly;
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331
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332 u32 mmio_base_phys;
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333 u32 fb_base_phys;
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334
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335 u32 mmio_base;
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336 u32 fb_base;
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337
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338 u32 MemCntl;
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339 u32 BusCntl;
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340
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341 struct pci_dev *pdev;
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342
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343 struct display disp;
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344 int currcon;
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345 struct display *currcon_display;
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346
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347 struct { u8 red, green, blue, pad; } palette[256];
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348
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349 int chipset;
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350 int video_ram;
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351 u8 rev;
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352 int pitch, bpp, depth;
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353 int xres, yres, pixclock;
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354
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355 u32 dp_gui_master_cntl;
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356
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357 struct pll_info pll;
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358 int pll_output_freq, post_div, fb_div;
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359
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360 struct ram_info ram;
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361
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362 #ifdef CONFIG_MTRR
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363 struct { int vram; int vram_valid; } mtrr;
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364 #endif
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365 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
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366 union {
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367 #if defined(FBCON_HAS_CFB16)
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368 u_int16_t cfb16[16];
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369 #endif
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370 #if defined(FBCON_HAS_CFB24)
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371 u_int32_t cfb24[16];
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372 #endif
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373 #if defined(FBCON_HAS_CFB32)
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374 u_int32_t cfb32[16];
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375 #endif
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376 } con_cmap;
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377 #endif
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378 };
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379
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380 #define SINGLE_MONITOR(rinfo) (rinfo->crtDispType == MT_NONE || rinfo->dviDispType == MT_NONE)
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381 /*#define DUAL_MONITOR(rinfo) (rinfo->crtDispType != MT_NONE && rinfo->dviDispType != MT_NONE)*/
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382 /* Disable DUAL monitor support for now */
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383 #define DUAL_MONITOR(rinfo) (0)
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384 #define PRIMARY_MONITOR(rinfo) (rinfo->dviDispType != MT_NONE && rinfo->dviDispType != MT_STV && rinfo->dviDispType != MT_CTV ? rinfo->dviDispType : rinfo->crtDispType)
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385
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386 static struct fb_var_screeninfo radeonfb_default_var = {
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387 640, 480, 640, 480, 0, 0, 8, 0,
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388 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
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389 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
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390 0, FB_VMODE_NONINTERLACED
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391 };
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392
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393
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394 /*
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395 * IO macros
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396 */
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397
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398 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
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399 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
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400 #define INREG(addr) readl((rinfo->mmio_base)+addr)
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401 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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402
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403 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
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404 OUTREG(CLOCK_CNTL_DATA, val)
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405 #define OUTPLLP(addr,val,mask) \
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406 do { \
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407 unsigned int _tmp = INPLL(addr); \
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408 _tmp &= (mask); \
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409 _tmp |= (val); \
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410 OUTPLL(addr, _tmp); \
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411 } while (0)
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412
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413 #define OUTREGP(addr,val,mask) \
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414 do { \
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415 unsigned int _tmp = INREG(addr); \
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416 _tmp &= (mask); \
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417 _tmp |= (val); \
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418 OUTREG(addr, _tmp); \
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419 } while (0)
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420
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421
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422 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
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423 {
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424 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
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425 return (INREG(CLOCK_CNTL_DATA));
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426 }
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427
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428 #define INPLL(addr) _INPLL(rinfo, addr)
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429
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430 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
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431 {
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432 switch (post_div) {
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433 case 1:
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434 return 0x00;
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435 case 2:
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436 return 0x01;
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437 case 3:
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438 return 0x04;
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439 case 4:
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440 return 0x02;
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441 case 6:
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442 return 0x06;
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443 case 8:
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444 return 0x03;
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445 case 12:
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446 return 0x07;
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447 default:
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448 return 0x02;
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449 }
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450 }
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451
|
|
452
|
|
453
|
|
454 static __inline__ int round_div(int num, int den)
|
|
455 {
|
|
456 return (num + (den / 2)) / den;
|
|
457 }
|
|
458
|
|
459
|
|
460
|
|
461 static __inline__ int min_bits_req(int val)
|
|
462 {
|
|
463 int bits_req = 0;
|
|
464
|
|
465 if (val == 0)
|
|
466 bits_req = 1;
|
|
467
|
|
468 while (val) {
|
|
469 val >>= 1;
|
|
470 bits_req++;
|
|
471 }
|
|
472
|
|
473 return (bits_req);
|
|
474 }
|
|
475
|
|
476
|
|
477 static __inline__ int _max(int val1, int val2)
|
|
478 {
|
|
479 if (val1 >= val2)
|
|
480 return val1;
|
|
481 else
|
|
482 return val2;
|
|
483 }
|
|
484
|
1911
|
485
|
|
486 /*
|
|
487 * 2D engine routines
|
|
488 */
|
|
489
|
|
490 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
|
|
491 {
|
|
492 int i;
|
|
493
|
|
494 /* initiate flush */
|
|
495 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
|
|
496 ~RB2D_DC_FLUSH_ALL);
|
|
497
|
|
498 for (i=0; i < 2000000; i++) {
|
|
499 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
|
|
500 break;
|
|
501 }
|
|
502 }
|
|
503
|
|
504
|
|
505 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
|
|
506 {
|
|
507 int i;
|
|
508
|
|
509 for (i=0; i<2000000; i++)
|
|
510 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
|
|
511 return;
|
|
512 }
|
|
513
|
|
514
|
|
515 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
|
|
516 {
|
|
517 int i;
|
|
518
|
|
519 /* ensure FIFO is empty before waiting for idle */
|
|
520 _radeon_fifo_wait (rinfo, 64);
|
|
521
|
|
522 for (i=0; i<2000000; i++) {
|
|
523 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
|
|
524 radeon_engine_flush (rinfo);
|
|
525 return;
|
|
526 }
|
|
527 }
|
|
528 }
|
|
529
|
|
530
|
2037
|
531
|
1911
|
532 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
|
|
533 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
|
|
534
|
|
535
|
|
536
|
|
537 /*
|
|
538 * helper routines
|
|
539 */
|
|
540
|
|
541 static __inline__ u32 radeon_get_dstbpp(u16 depth)
|
|
542 {
|
|
543 switch (depth) {
|
|
544 case 8:
|
|
545 return DST_8BPP;
|
|
546 case 15:
|
|
547 return DST_15BPP;
|
|
548 case 16:
|
|
549 return DST_16BPP;
|
1914
|
550 case 24:
|
|
551 return DST_24BPP;
|
1911
|
552 case 32:
|
|
553 return DST_32BPP;
|
|
554 default:
|
|
555 return 0;
|
|
556 }
|
|
557 }
|
|
558
|
|
559
|
|
560 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
|
|
561 {
|
|
562 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
|
|
563
|
|
564 radeon_engine_flush (rinfo);
|
|
565
|
|
566 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
|
567 mclk_cntl = INPLL(MCLK_CNTL);
|
|
568
|
|
569 OUTPLL(MCLK_CNTL, (mclk_cntl |
|
|
570 FORCEON_MCLKA |
|
|
571 FORCEON_MCLKB |
|
|
572 FORCEON_YCLKA |
|
|
573 FORCEON_YCLKB |
|
|
574 FORCEON_MC |
|
|
575 FORCEON_AIC));
|
|
576 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
|
|
577
|
|
578 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
|
|
579 SOFT_RESET_CP |
|
|
580 SOFT_RESET_HI |
|
|
581 SOFT_RESET_SE |
|
|
582 SOFT_RESET_RE |
|
|
583 SOFT_RESET_PP |
|
|
584 SOFT_RESET_E2 |
|
|
585 SOFT_RESET_RB |
|
|
586 SOFT_RESET_HDP);
|
|
587 INREG(RBBM_SOFT_RESET);
|
|
588 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
|
|
589 ~(SOFT_RESET_CP |
|
|
590 SOFT_RESET_HI |
|
|
591 SOFT_RESET_SE |
|
|
592 SOFT_RESET_RE |
|
|
593 SOFT_RESET_PP |
|
|
594 SOFT_RESET_E2 |
|
|
595 SOFT_RESET_RB |
|
|
596 SOFT_RESET_HDP));
|
|
597 INREG(RBBM_SOFT_RESET);
|
|
598
|
|
599 OUTPLL(MCLK_CNTL, mclk_cntl);
|
|
600 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
|
|
601 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
|
|
602
|
|
603 return;
|
|
604 }
|
|
605
|
|
606 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
|
|
607
|
|
608 /*
|
|
609 * globals
|
|
610 */
|
|
611
|
|
612 static char fontname[40] __initdata;
|
|
613 static char *mode_option __initdata;
|
|
614 static char noaccel __initdata = 0;
|
1951
|
615 static int nomtrr __initdata = 0;
|
1911
|
616
|
1914
|
617 #if 0
|
1911
|
618 #ifdef FBCON_HAS_CFB8
|
|
619 static struct display_switch fbcon_radeon8;
|
|
620 #endif
|
1914
|
621 #endif
|
1911
|
622
|
1951
|
623 #ifdef CONFIG_MTRR
|
|
624 static int mtrr = 1;
|
|
625 #endif
|
|
626
|
1911
|
627 /*
|
|
628 * prototypes
|
|
629 */
|
|
630
|
|
631 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
632 struct fb_info *info);
|
|
633 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
634 struct fb_info *info);
|
|
635 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
636 struct fb_info *info);
|
|
637 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
638 struct fb_info *info);
|
|
639 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
640 struct fb_info *info);
|
|
641 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
642 struct fb_info *info);
|
|
643 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
644 unsigned long arg, int con, struct fb_info *info);
|
|
645 static int radeonfb_switch (int con, struct fb_info *info);
|
|
646 static int radeonfb_updatevar (int con, struct fb_info *info);
|
|
647 static void radeonfb_blank (int blank, struct fb_info *info);
|
|
648 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
|
|
649 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
650 unsigned *blue, unsigned *transp,
|
|
651 struct fb_info *info);
|
|
652 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
653 unsigned blue, unsigned transp, struct fb_info *info);
|
1914
|
654 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
|
2132
|
655 static void radeon_save_mode (struct radeonfb_info *rinfo,
|
|
656 struct radeon_regs *save);
|
1911
|
657 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
658 struct radeon_regs *save);
|
|
659 static void radeon_engine_init (struct radeonfb_info *rinfo);
|
2132
|
660 static int radeon_load_video_mode (struct radeonfb_info *rinfo,
|
1911
|
661 struct fb_var_screeninfo *mode);
|
|
662 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
663 struct radeon_regs *mode);
|
2132
|
664 static void radeon_write_state (struct radeonfb_info *rinfo,
|
|
665 struct radeon_regs *mode);
|
1911
|
666 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
|
|
667 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
|
|
668 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
|
|
669 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
670 const struct pci_device_id *ent);
|
|
671 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
|
|
672 static char *radeon_find_rom(struct radeonfb_info *rinfo);
|
|
673 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
|
1914
|
674 static void do_install_cmap(int con, struct fb_info *info);
|
|
675 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
676 struct fb_var_screeninfo *var,
|
|
677 struct fb_var_screeninfo *v,
|
|
678 int nom, int den);
|
1911
|
679
|
|
680 static struct fb_ops radeon_fb_ops = {
|
|
681 fb_get_fix: radeonfb_get_fix,
|
|
682 fb_get_var: radeonfb_get_var,
|
|
683 fb_set_var: radeonfb_set_var,
|
|
684 fb_get_cmap: radeonfb_get_cmap,
|
|
685 fb_set_cmap: radeonfb_set_cmap,
|
|
686 fb_pan_display: radeonfb_pan_display,
|
|
687 fb_ioctl: radeonfb_ioctl,
|
|
688 };
|
|
689
|
|
690
|
|
691 static struct pci_driver radeonfb_driver = {
|
|
692 name: "radeonfb",
|
|
693 id_table: radeonfb_pci_table,
|
|
694 probe: radeonfb_pci_register,
|
|
695 remove: radeonfb_pci_unregister,
|
|
696 };
|
|
697
|
2037
|
698 static void _radeon_wait_for_idle(struct radeonfb_info *rinfo);
|
|
699 /* Restore the acceleration hardware to its previous state. */
|
|
700 static void _radeon_engine_restore(struct radeonfb_info *rinfo)
|
|
701 {
|
|
702 int pitch64;
|
|
703
|
|
704 radeon_fifo_wait(1);
|
|
705 /* turn of all automatic flushing - we'll do it all */
|
|
706 OUTREG(RB2D_DSTCACHE_MODE, 0);
|
|
707
|
|
708 pitch64 = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6;
|
|
709
|
|
710 radeon_fifo_wait(1);
|
|
711 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) |
|
|
712 (pitch64 << 22));
|
|
713
|
|
714 radeon_fifo_wait(1);
|
|
715 #if defined(__BIG_ENDIAN)
|
|
716 OUTREGP(DP_DATATYPE,
|
|
717 HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
|
|
718 #else
|
|
719 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
720 #endif
|
|
721
|
|
722 radeon_fifo_wait(1);
|
|
723 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX
|
|
724 | DEFAULT_SC_BOTTOM_MAX));
|
|
725 radeon_fifo_wait(1);
|
|
726 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL)
|
|
727 | GMC_BRUSH_SOLID_COLOR
|
|
728 | GMC_SRC_DATATYPE_COLOR));
|
|
729
|
|
730 radeon_fifo_wait(7);
|
|
731 OUTREG(DST_LINE_START, 0);
|
|
732 OUTREG(DST_LINE_END, 0);
|
|
733 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
734 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
735 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
736 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
737 OUTREG(DP_WRITE_MASK, 0xffffffff);
|
|
738
|
|
739 _radeon_wait_for_idle(rinfo);
|
|
740 }
|
|
741
|
|
742 /* The FIFO has 64 slots. This routines waits until at least `entries' of
|
|
743 these slots are empty. */
|
|
744 #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
|
|
745 static void _radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries)
|
|
746 {
|
|
747 int i;
|
|
748
|
|
749 for (;;) {
|
|
750 for (i = 0; i < RADEON_TIMEOUT; i++) {
|
|
751 if((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) return;
|
|
752 }
|
|
753 radeon_engine_reset();
|
|
754 _radeon_engine_restore(rinfo);
|
|
755 /* it might be that DRI has been compiled in, but corresponding
|
|
756 library was not loaded.. */
|
|
757 }
|
|
758 }
|
|
759 /* Wait for the graphics engine to be completely idle: the FIFO has
|
|
760 drained, the Pixel Cache is flushed, and the engine is idle. This is a
|
|
761 standard "sync" function that will make the hardware "quiescent". */
|
|
762 static void _radeon_wait_for_idle(struct radeonfb_info *rinfo)
|
|
763 {
|
|
764 int i;
|
|
765
|
|
766 _radeon_wait_for_fifo_function(rinfo, 64);
|
|
767
|
|
768 for (;;) {
|
|
769 for (i = 0; i < RADEON_TIMEOUT; i++) {
|
|
770 if (!(INREG(RBBM_STATUS) & RBBM_ACTIVE)) {
|
|
771 radeon_engine_flush(rinfo);
|
|
772 return;
|
|
773 }
|
|
774 }
|
|
775 _radeon_engine_reset(rinfo);
|
|
776 _radeon_engine_restore(rinfo);
|
|
777 }
|
|
778 }
|
|
779
|
|
780
|
|
781 static u32 RADEONVIP_idle(struct radeonfb_info *rinfo)
|
|
782 {
|
|
783 u32 timeout;
|
|
784
|
|
785 _radeon_wait_for_idle(rinfo);
|
|
786 timeout = INREG(VIPH_TIMEOUT_STAT);
|
|
787 if(timeout & VIPH_TIMEOUT_STAT__VIPH_REG_STAT) /* lockup ?? */
|
|
788 {
|
|
789 radeon_fifo_wait(2);
|
|
790 OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REG_AK);
|
|
791 _radeon_wait_for_idle(rinfo);
|
|
792 return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
|
|
793 }
|
|
794 _radeon_wait_for_idle(rinfo);
|
|
795 return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
|
|
796 }
|
|
797
|
1911
|
798
|
|
799 int __init radeonfb_init (void)
|
|
800 {
|
1951
|
801 #ifdef CONFIG_MTRR
|
|
802 if (nomtrr) {
|
|
803 mtrr = 0;
|
|
804 printk("radeonfb: Parameter NOMTRR set\n");
|
|
805 }
|
|
806 #endif
|
|
807 return pci_module_init (&radeonfb_driver);
|
1911
|
808 }
|
|
809
|
|
810
|
|
811 void __exit radeonfb_exit (void)
|
|
812 {
|
|
813 pci_unregister_driver (&radeonfb_driver);
|
|
814 }
|
|
815
|
|
816
|
|
817 int __init radeonfb_setup (char *options)
|
|
818 {
|
|
819 char *this_opt;
|
|
820
|
|
821 if (!options || !*options)
|
|
822 return 0;
|
|
823
|
|
824 for (this_opt = strtok (options, ","); this_opt;
|
|
825 this_opt = strtok (NULL, ",")) {
|
|
826 if (!strncmp (this_opt, "font:", 5)) {
|
|
827 char *p;
|
|
828 int i;
|
|
829
|
|
830 p = this_opt + 5;
|
|
831 for (i=0; i<sizeof (fontname) - 1; i++)
|
|
832 if (!*p || *p == ' ' || *p == ',')
|
|
833 break;
|
|
834 memcpy(fontname, this_opt + 5, i);
|
|
835 } else if (!strncmp(this_opt, "noaccel", 7)) {
|
|
836 noaccel = 1;
|
|
837 }
|
1951
|
838 #ifdef CONFIG_MTRR
|
|
839 else if(!strncmp(this_opt, "nomtrr", 6)) {
|
|
840 mtrr = 0;
|
|
841 }
|
|
842 #endif
|
1911
|
843 else mode_option = this_opt;
|
|
844 }
|
|
845
|
|
846 return 0;
|
|
847 }
|
|
848
|
|
849 #ifdef MODULE
|
|
850 module_init(radeonfb_init);
|
|
851 module_exit(radeonfb_exit);
|
|
852 #endif
|
|
853
|
|
854
|
1915
|
855 MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)");
|
|
856 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION);
|
1951
|
857 #ifdef CONFIG_MTRR
|
|
858 MODULE_PARM(nomtrr, "i");
|
|
859 MODULE_PARM_DESC(nomtrr, "Don't touch MTRR (touch=0(default))");
|
|
860 #endif
|
1911
|
861
|
2037
|
862 /* address format:
|
|
863 ((device & 0x3)<<14) | (fifo << 12) | (addr)
|
|
864 */
|
|
865
|
|
866 static int RADEONVIP_read(struct radeonfb_info *rinfo, u32 address, u32 count, u8 *buffer)
|
|
867 {
|
|
868 u32 status,tmp;
|
|
869
|
|
870 if((count!=1) && (count!=2) && (count!=4))
|
|
871 {
|
|
872 printk("radeonfb: Attempt to access VIP bus with non-stadard transaction length\n");
|
|
873 return 0;
|
|
874 }
|
|
875
|
|
876 radeon_fifo_wait(2);
|
|
877 OUTREG(VIPH_REG_ADDR, address | 0x2000);
|
|
878 while(VIP_BUSY == (status = RADEONVIP_idle(rinfo)));
|
|
879 if(VIP_IDLE != status) return 0;
|
|
880
|
|
881 /*
|
|
882 disable VIPH_REGR_DIS to enable VIP cycle.
|
|
883 The LSB of VIPH_TIMEOUT_STAT are set to 0
|
|
884 because 1 would have acknowledged various VIP
|
|
885 interrupts unexpectedly
|
|
886 */
|
|
887 radeon_fifo_wait(2);
|
|
888 OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
|
|
889 /*
|
|
890 the value returned here is garbage. The read merely initiates
|
|
891 a register cycle
|
|
892 */
|
|
893 _radeon_wait_for_idle(rinfo);
|
|
894 INREG(VIPH_REG_DATA);
|
|
895
|
|
896 while(VIP_BUSY == (status = RADEONVIP_idle(rinfo)));
|
|
897 if(VIP_IDLE != status) return 0;
|
|
898 /*
|
|
899 set VIPH_REGR_DIS so that the read won't take too long.
|
|
900 */
|
|
901 _radeon_wait_for_idle(rinfo);
|
|
902 tmp=INREG(VIPH_TIMEOUT_STAT);
|
|
903 OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
|
|
904 _radeon_wait_for_idle(rinfo);
|
|
905 switch(count){
|
|
906 case 1:
|
|
907 *buffer=(u8)(INREG(VIPH_REG_DATA) & 0xff);
|
|
908 break;
|
|
909 case 2:
|
|
910 *(u16 *)buffer=(u16) (INREG(VIPH_REG_DATA) & 0xffff);
|
|
911 break;
|
|
912 case 4:
|
|
913 *(u32 *)buffer=(u32) ( INREG(VIPH_REG_DATA) & 0xffffffff);
|
|
914 break;
|
|
915 }
|
|
916 while(VIP_BUSY == (status = RADEONVIP_idle(rinfo)));
|
|
917 if(VIP_IDLE != status) return 0;
|
|
918 /*
|
|
919 so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
|
|
920 */
|
|
921 OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
|
|
922 return 1;
|
|
923 }
|
|
924
|
|
925 static int theatre_read(struct radeonfb_info *rinfo,u32 reg, u32 *data)
|
|
926 {
|
|
927 if(rinfo->theatre_num<0) return 0;
|
|
928 return RADEONVIP_read(rinfo, ((rinfo->theatre_num & 0x3)<<14) | reg,4, (u8 *) data);
|
|
929 }
|
|
930
|
1915
|
931 static char * GET_MON_NAME(int type)
|
|
932 {
|
|
933 char *pret;
|
|
934 switch(type)
|
|
935 {
|
|
936 case MT_NONE: pret = "no"; break;
|
|
937 case MT_CRT: pret = "CRT"; break;
|
|
938 case MT_DFP: pret = "DFP"; break;
|
|
939 case MT_LCD: pret = "LCD"; break;
|
|
940 case MT_CTV: pret = "CTV"; break;
|
|
941 case MT_STV: pret = "STV"; break;
|
|
942 default: pret = "Unknown";
|
|
943 }
|
|
944 return pret;
|
|
945 }
|
1911
|
946
|
2135
|
947 /*This funtion is used to reverse calculate
|
|
948 panel information from register settings in VGA mode.
|
|
949 More graceful way is to use EDID information... if it can be detected.
|
|
950 This way may be better than directly probing BIOS image. Because
|
|
951 BIOS image could change from version to version, while the
|
|
952 registers should always(?) contain right information, otherwise
|
|
953 the VGA mode display will not be correct. Well, if someone
|
|
954 messes up these registers before our driver is loaded, we'll be in
|
|
955 trouble...*/
|
|
956 static int radeon_get_dfp_info(struct radeonfb_info *rinfo)
|
|
957 {
|
|
958 unsigned long r;
|
|
959 unsigned short a, b;
|
|
960
|
|
961 r = INREG(FP_VERT_STRETCH);
|
|
962 r &= 0x00fff000;
|
|
963 rinfo->PanelYRes = (unsigned short)(r >> 0x0c) + 1;
|
|
964
|
|
965 switch(rinfo->PanelYRes)
|
|
966 {
|
|
967 case 480: rinfo->PanelXRes = 640;
|
|
968 break;
|
|
969 case 600: rinfo->PanelXRes = 800;
|
|
970 break;
|
|
971 case 768: rinfo->PanelXRes = 1024;
|
|
972 break;
|
|
973 case 1024: rinfo->PanelXRes = 1280;
|
|
974 break;
|
|
975 case 1050: rinfo->PanelXRes = 1400;
|
|
976 break;
|
|
977 case 1200: rinfo->PanelXRes = 1600;
|
|
978 break;
|
|
979 default:
|
|
980 printk("radeonfb: Failed to detect the DFP panel size.\n");
|
|
981 return 0;
|
|
982
|
|
983 }
|
|
984
|
|
985 printk("Detected DFP panel size: %dx%d\n", rinfo->PanelXRes, rinfo->PanelYRes);
|
|
986
|
|
987 r = INREG(FP_CRTC_H_TOTAL_DISP);
|
|
988 a = (r & FP_CRTC_H_TOTAL_MASK) + 4;
|
|
989 b = (r & 0x01FF0000) >> FP_CRTC_H_DISP_SHIFT;
|
|
990 rinfo->HBlank = (a - b + 1) * 8;
|
|
991
|
|
992 r = INREG(FP_H_SYNC_STRT_WID);
|
|
993 rinfo->HOverPlus =
|
|
994 (unsigned short)((r & FP_H_SYNC_STRT_CHAR_MASK)
|
|
995 >> FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
|
|
996 rinfo->HOverPlus *= 8;
|
|
997 rinfo->HSyncWidth =
|
|
998 (unsigned short)((r & FP_H_SYNC_WID_MASK)
|
|
999 >> FP_H_SYNC_WID_SHIFT);
|
|
1000 rinfo->HSyncWidth *= 8;
|
|
1001 r = INREG(FP_CRTC_V_TOTAL_DISP);
|
|
1002 a = (r & FP_CRTC_V_TOTAL_MASK) + 1;
|
|
1003 b = (r & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
|
|
1004 rinfo->VBlank = a - b /*+ 24*/;
|
|
1005
|
|
1006 r = INREG(FP_V_SYNC_STRT_WID);
|
|
1007 rinfo->VOverPlus = (unsigned short)(r & FP_V_SYNC_STRT_MASK)
|
|
1008 - b + 1;
|
|
1009 rinfo->VSyncWidth = (unsigned short)((r & FP_V_SYNC_WID_MASK)
|
|
1010 >> FP_V_SYNC_WID_SHIFT);
|
|
1011
|
|
1012 return 1;
|
|
1013 }
|
1911
|
1014
|
|
1015 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
1016 const struct pci_device_id *ent)
|
|
1017 {
|
|
1018 struct radeonfb_info *rinfo;
|
|
1019 u32 tmp;
|
|
1020 int i, j;
|
|
1021 char *bios_seg = NULL;
|
|
1022
|
|
1023 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
|
|
1024 if (!rinfo) {
|
|
1025 printk ("radeonfb: could not allocate memory\n");
|
|
1026 return -ENODEV;
|
|
1027 }
|
|
1028
|
|
1029 memset (rinfo, 0, sizeof (struct radeonfb_info));
|
|
1030
|
|
1031 /* enable device */
|
|
1032 {
|
|
1033 int err;
|
|
1034
|
|
1035 if ((err = pci_enable_device(pdev))) {
|
|
1036 printk("radeonfb: cannot enable device\n");
|
|
1037 kfree (rinfo);
|
|
1038 return -ENODEV;
|
|
1039 }
|
|
1040 }
|
|
1041
|
|
1042 /* set base addrs */
|
|
1043 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
|
|
1044 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
|
|
1045
|
|
1046 /* request the mem regions */
|
|
1047 if (!request_mem_region (rinfo->fb_base_phys,
|
|
1048 pci_resource_len(pdev, 0), "radeonfb")) {
|
|
1049 printk ("radeonfb: cannot reserve FB region\n");
|
|
1050 kfree (rinfo);
|
|
1051 return -ENODEV;
|
|
1052 }
|
|
1053
|
|
1054 if (!request_mem_region (rinfo->mmio_base_phys,
|
|
1055 pci_resource_len(pdev, 2), "radeonfb")) {
|
|
1056 printk ("radeonfb: cannot reserve MMIO region\n");
|
|
1057 release_mem_region (rinfo->fb_base_phys,
|
|
1058 pci_resource_len(pdev, 0));
|
|
1059 kfree (rinfo);
|
|
1060 return -ENODEV;
|
|
1061 }
|
|
1062
|
|
1063 /* map the regions */
|
|
1064 rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
|
|
1065 RADEON_REGSIZE);
|
|
1066 if (!rinfo->mmio_base) {
|
|
1067 printk ("radeonfb: cannot map MMIO\n");
|
|
1068 release_mem_region (rinfo->mmio_base_phys,
|
|
1069 pci_resource_len(pdev, 2));
|
|
1070 release_mem_region (rinfo->fb_base_phys,
|
|
1071 pci_resource_len(pdev, 0));
|
|
1072 kfree (rinfo);
|
|
1073 return -ENODEV;
|
|
1074 }
|
|
1075
|
|
1076 /* chipset */
|
|
1077 switch (pdev->device) {
|
|
1078 case PCI_DEVICE_ID_RADEON_QD:
|
|
1079 strcpy(rinfo->name, "Radeon QD ");
|
|
1080 break;
|
|
1081 case PCI_DEVICE_ID_RADEON_QE:
|
|
1082 strcpy(rinfo->name, "Radeon QE ");
|
|
1083 break;
|
|
1084 case PCI_DEVICE_ID_RADEON_QF:
|
|
1085 strcpy(rinfo->name, "Radeon QF ");
|
|
1086 break;
|
|
1087 case PCI_DEVICE_ID_RADEON_QG:
|
|
1088 strcpy(rinfo->name, "Radeon QG ");
|
|
1089 break;
|
1913
|
1090 case PCI_DEVICE_ID_RADEON_QY:
|
1915
|
1091 rinfo->hasCRTC2 = 1;
|
|
1092 strcpy(rinfo->name, "Radeon VE QY ");
|
1913
|
1093 break;
|
|
1094 case PCI_DEVICE_ID_RADEON_QZ:
|
1915
|
1095 rinfo->hasCRTC2 = 1;
|
|
1096 strcpy(rinfo->name, "Radeon VE QZ ");
|
|
1097 break;
|
|
1098 case PCI_DEVICE_ID_RADEON_LY:
|
|
1099 rinfo->hasCRTC2 = 1;
|
2132
|
1100 rinfo->isM6 = 1;
|
1915
|
1101 strcpy(rinfo->name, "Radeon M6 LY ");
|
|
1102 break;
|
|
1103 case PCI_DEVICE_ID_RADEON_LZ:
|
|
1104 rinfo->hasCRTC2 = 1;
|
2132
|
1105 rinfo->isM6 = 1;
|
1915
|
1106 strcpy(rinfo->name, "Radeon M6 LZ ");
|
|
1107 break;
|
|
1108 case PCI_DEVICE_ID_RADEON_LW:
|
|
1109 /* Note: Only difference between VE,M6 and M7 is initialization CRTC2
|
|
1110 registers in dual monitor configuration!!! */
|
|
1111 rinfo->hasCRTC2 = 1;
|
|
1112 rinfo->isM7 = 1;
|
|
1113 strcpy(rinfo->name, "Radeon M7 LW ");
|
1912
|
1114 break;
|
1967
|
1115 case PCI_DEVICE_ID_R200_QL:
|
|
1116 rinfo->hasCRTC2 = 1;
|
|
1117 rinfo->isR200 = 1;
|
1969
|
1118 strcpy(rinfo->name, "Radeon2 8500 QL ");
|
1967
|
1119 break;
|
|
1120 case PCI_DEVICE_ID_RV200_QW:
|
|
1121 rinfo->hasCRTC2 = 1;
|
|
1122 rinfo->isM7 = 1;
|
|
1123 strcpy(rinfo->name, "Radeon2 7500 QW ");
|
|
1124 break;
|
1911
|
1125 default:
|
1915
|
1126 release_mem_region (rinfo->mmio_base_phys,
|
|
1127 pci_resource_len(pdev, 2));
|
|
1128 release_mem_region (rinfo->fb_base_phys,
|
|
1129 pci_resource_len(pdev, 0));
|
|
1130 kfree (rinfo);
|
1911
|
1131 return -ENODEV;
|
|
1132 }
|
|
1133
|
|
1134 /* framebuffer size */
|
|
1135 tmp = INREG(CONFIG_MEMSIZE);
|
|
1136
|
|
1137 /* mem size is bits [28:0], mask off the rest */
|
|
1138 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
|
1139
|
|
1140 /* ram type */
|
2132
|
1141 rinfo->MemCntl = INREG(MEM_SDRAM_MODE_REG);
|
|
1142 switch ((MEM_CFG_TYPE & rinfo->MemCntl) >> 30) {
|
1911
|
1143 case 0:
|
|
1144 /* SDR SGRAM (2:1) */
|
|
1145 strcpy(rinfo->ram_type, "SDR SGRAM");
|
|
1146 rinfo->ram.ml = 4;
|
|
1147 rinfo->ram.mb = 4;
|
|
1148 rinfo->ram.trcd = 1;
|
|
1149 rinfo->ram.trp = 2;
|
|
1150 rinfo->ram.twr = 1;
|
|
1151 rinfo->ram.cl = 2;
|
|
1152 rinfo->ram.loop_latency = 16;
|
|
1153 rinfo->ram.rloop = 16;
|
|
1154
|
|
1155 break;
|
|
1156 case 1:
|
|
1157 /* DDR SGRAM */
|
|
1158 strcpy(rinfo->ram_type, "DDR SGRAM");
|
|
1159 rinfo->ram.ml = 4;
|
|
1160 rinfo->ram.mb = 4;
|
|
1161 rinfo->ram.trcd = 3;
|
|
1162 rinfo->ram.trp = 3;
|
|
1163 rinfo->ram.twr = 2;
|
|
1164 rinfo->ram.cl = 3;
|
|
1165 rinfo->ram.tr2w = 1;
|
|
1166 rinfo->ram.loop_latency = 16;
|
|
1167 rinfo->ram.rloop = 16;
|
|
1168
|
|
1169 break;
|
|
1170 default:
|
|
1171 /* 64-bit SDR SGRAM */
|
|
1172 strcpy(rinfo->ram_type, "SDR SGRAM 64");
|
|
1173 rinfo->ram.ml = 4;
|
|
1174 rinfo->ram.mb = 8;
|
|
1175 rinfo->ram.trcd = 3;
|
|
1176 rinfo->ram.trp = 3;
|
|
1177 rinfo->ram.twr = 1;
|
|
1178 rinfo->ram.cl = 3;
|
|
1179 rinfo->ram.tr2w = 1;
|
|
1180 rinfo->ram.loop_latency = 17;
|
|
1181 rinfo->ram.rloop = 17;
|
|
1182
|
|
1183 break;
|
|
1184 }
|
2132
|
1185 /* Bus type */
|
|
1186 rinfo->BusCntl = INREG(BUS_CNTL);
|
1911
|
1187
|
|
1188 bios_seg = radeon_find_rom(rinfo);
|
|
1189 radeon_get_pllinfo(rinfo, bios_seg);
|
|
1190
|
|
1191 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
|
|
1192 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
|
|
1193
|
|
1194 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
|
1195
|
1915
|
1196 /*****
|
|
1197 VE and M6 have both DVI and CRT ports (for M6 DVI port can be switch to
|
|
1198 DFP port). The DVI port can also be conneted to a CRT with an adapter.
|
|
1199 Here is the definition of ports for this driver---
|
|
1200 (1) If both port are connected, DVI port will be treated as the Primary
|
|
1201 port (uses CRTC1) and CRT port will be treated as the Secondary port
|
|
1202 (uses CRTC2)
|
|
1203 (2) If only one port is connected, it will treated as the Primary port
|
|
1204 (??? uses CRTC1 ???)
|
|
1205 *****/
|
|
1206 if(rinfo->hasCRTC2) {
|
|
1207 /* Using BIOS scratch registers works with for VE/M6,
|
|
1208 no such registers in regular RADEON!!!*/
|
|
1209 tmp = INREG(RADEON_BIOS_4_SCRATCH);
|
|
1210 /*check Primary (DVI/DFP port)*/
|
|
1211 if(tmp & 0x08) rinfo->dviDispType = MT_DFP;
|
|
1212 else if(tmp & 0x04) rinfo->dviDispType = MT_LCD;
|
|
1213 else if(tmp & 0x0200) rinfo->dviDispType = MT_CRT;
|
|
1214 else if(tmp & 0x10) rinfo->dviDispType = MT_CTV;
|
|
1215 else if(tmp & 0x20) rinfo->dviDispType = MT_STV;
|
|
1216 /*check Secondary (CRT port).*/
|
|
1217 if(tmp & 0x02) rinfo->crtDispType = MT_CRT;
|
|
1218 else if(tmp & 0x800) rinfo->crtDispType = MT_DFP;
|
|
1219 else if(tmp & 0x400) rinfo->crtDispType = MT_LCD;
|
|
1220 else if(tmp & 0x1000) rinfo->crtDispType = MT_CTV;
|
|
1221 else if(tmp & 0x2000) rinfo->crtDispType = MT_STV;
|
|
1222 if(rinfo->dviDispType == MT_NONE &&
|
|
1223 rinfo->crtDispType == MT_NONE) {
|
|
1224 printk("radeonfb: No monitor detected!!!\n");
|
|
1225 release_mem_region (rinfo->mmio_base_phys,
|
|
1226 pci_resource_len(pdev, 2));
|
|
1227 release_mem_region (rinfo->fb_base_phys,
|
|
1228 pci_resource_len(pdev, 0));
|
|
1229 kfree (rinfo);
|
|
1230 return -ENODEV;
|
|
1231 }
|
|
1232 }
|
|
1233 else {
|
|
1234 /*Regular Radeon ASIC, only one CRTC, but it could be
|
|
1235 used for DFP with a DVI output, like AIW board*/
|
|
1236 rinfo->dviDispType = MT_NONE;
|
|
1237 tmp = INREG(FP_GEN_CNTL);
|
|
1238 if(tmp & FP_EN_TMDS) rinfo->crtDispType = MT_DFP;
|
|
1239 else rinfo->crtDispType = MT_CRT;
|
|
1240 }
|
|
1241
|
|
1242 if(bios_seg) {
|
|
1243 /*
|
|
1244 FIXME!!! TVout support currently is incomplete
|
|
1245 On Radeon VE TVout is recognized as STV monitor on DVI port.
|
|
1246 */
|
|
1247 char * bios_ptr = bios_seg + 0x48L;
|
|
1248 rinfo->hasTVout = readw(bios_ptr+0x32);
|
|
1249 }
|
|
1250
|
2135
|
1251 if((rinfo->dviDispType == MT_DFP || rinfo->dviDispType == MT_LCD ||
|
|
1252 rinfo->crtDispType == MT_DFP))
|
|
1253 if(!radeon_get_dfp_info(rinfo)) goto reg_err;
|
1911
|
1254 rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
|
1255 rinfo->video_ram);
|
|
1256 if (!rinfo->fb_base) {
|
|
1257 printk ("radeonfb: cannot map FB\n");
|
2135
|
1258 reg_err:
|
1911
|
1259 iounmap ((void*)rinfo->mmio_base);
|
|
1260 release_mem_region (rinfo->mmio_base_phys,
|
|
1261 pci_resource_len(pdev, 2));
|
|
1262 release_mem_region (rinfo->fb_base_phys,
|
|
1263 pci_resource_len(pdev, 0));
|
|
1264 kfree (rinfo);
|
|
1265 return -ENODEV;
|
|
1266 }
|
|
1267
|
|
1268 /* XXX turn off accel for now, blts aren't working right */
|
|
1269 noaccel = 1;
|
|
1270
|
|
1271 /* set all the vital stuff */
|
|
1272 radeon_set_fbinfo (rinfo);
|
|
1273
|
|
1274 /* save current mode regs before we switch into the new one
|
|
1275 * so we can restore this upon __exit
|
|
1276 */
|
|
1277 radeon_save_state (rinfo, &rinfo->init_state);
|
|
1278
|
|
1279 /* init palette */
|
|
1280 for (i=0; i<16; i++) {
|
|
1281 j = color_table[i];
|
|
1282 rinfo->palette[i].red = default_red[j];
|
|
1283 rinfo->palette[i].green = default_grn[j];
|
|
1284 rinfo->palette[i].blue = default_blu[j];
|
|
1285 }
|
|
1286
|
|
1287 pdev->driver_data = rinfo;
|
|
1288
|
|
1289 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
|
|
1290 printk ("radeonfb: could not register framebuffer\n");
|
|
1291 iounmap ((void*)rinfo->fb_base);
|
|
1292 iounmap ((void*)rinfo->mmio_base);
|
|
1293 release_mem_region (rinfo->mmio_base_phys,
|
|
1294 pci_resource_len(pdev, 2));
|
|
1295 release_mem_region (rinfo->fb_base_phys,
|
|
1296 pci_resource_len(pdev, 0));
|
|
1297 kfree (rinfo);
|
|
1298 return -ENODEV;
|
|
1299 }
|
|
1300
|
|
1301 if (!noaccel) {
|
|
1302 /* initialize the engine */
|
|
1303 radeon_engine_init (rinfo);
|
|
1304 }
|
|
1305
|
1915
|
1306 printk ("radeonfb: ATI %s %s %d MB\n",rinfo->name,rinfo->ram_type,
|
1911
|
1307 (rinfo->video_ram/(1024*1024)));
|
1915
|
1308 if(rinfo->hasCRTC2) {
|
|
1309 printk("radeonfb: DVI port has %s monitor connected\n",GET_MON_NAME(rinfo->dviDispType));
|
|
1310 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
1311 }
|
|
1312 else
|
|
1313 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
1314 printk("radeonfb: This card has %sTVout\n",rinfo->hasTVout ? "" : "no ");
|
1951
|
1315 #ifdef CONFIG_MTRR
|
|
1316 if (mtrr) {
|
|
1317 rinfo->mtrr.vram = mtrr_add(rinfo->fb_base_phys,
|
|
1318 rinfo->video_ram, MTRR_TYPE_WRCOMB, 1);
|
|
1319 rinfo->mtrr.vram_valid = 1;
|
|
1320 /* let there be speed */
|
|
1321 printk("radeonfb: MTRR set to ON\n");
|
|
1322 }
|
|
1323 #endif /* CONFIG_MTRR */
|
2037
|
1324 rinfo->theatre_num = -1;
|
|
1325 for(i=0;i<4;i++)
|
|
1326 {
|
|
1327 if(RADEONVIP_read(rinfo, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (u8 *)&tmp) &&
|
|
1328 (tmp==RT_ATI_ID))
|
|
1329 {
|
|
1330 rinfo->theatre_num=i;
|
|
1331 break;
|
|
1332 }
|
|
1333 }
|
|
1334 if(rinfo->theatre_num >= 0) {
|
|
1335 printk("radeonfb: Device %d on VIP bus ids as %x\n",i,tmp);
|
|
1336 theatre_read(rinfo,VIP_VIP_REVISION_ID, &tmp);
|
|
1337 printk("radeonfb: Detected Rage Theatre revision %8.8X\n", tmp);
|
|
1338 }
|
2046
|
1339 else printk("radeonfb: Rage Theatre was not detected\n");
|
2037
|
1340 return 0;
|
1911
|
1341 }
|
|
1342
|
|
1343
|
|
1344
|
|
1345 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
|
|
1346 {
|
|
1347 struct radeonfb_info *rinfo = pdev->driver_data;
|
|
1348
|
|
1349 if (!rinfo)
|
|
1350 return;
|
|
1351
|
|
1352 /* restore original state */
|
2132
|
1353 radeon_write_state (rinfo, &rinfo->init_state);
|
1911
|
1354
|
|
1355 unregister_framebuffer ((struct fb_info *) rinfo);
|
1951
|
1356 #ifdef CONFIG_MTRR
|
|
1357 if (rinfo->mtrr.vram_valid)
|
|
1358 mtrr_del(rinfo->mtrr.vram, rinfo->fb_base_phys,
|
|
1359 rinfo->video_ram);
|
|
1360 #endif /* CONFIG_MTRR */
|
1911
|
1361 iounmap ((void*)rinfo->mmio_base);
|
|
1362 iounmap ((void*)rinfo->fb_base);
|
|
1363
|
|
1364 release_mem_region (rinfo->mmio_base_phys,
|
|
1365 pci_resource_len(pdev, 2));
|
|
1366 release_mem_region (rinfo->fb_base_phys,
|
|
1367 pci_resource_len(pdev, 0));
|
|
1368
|
|
1369 kfree (rinfo);
|
|
1370 }
|
|
1371
|
|
1372
|
|
1373
|
|
1374 static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
|
1375 {
|
1914
|
1376 #if defined(__i386__)
|
1911
|
1377 u32 segstart;
|
|
1378 char *rom_base;
|
|
1379 char *rom;
|
|
1380 int stage;
|
1915
|
1381 int i,j;
|
1911
|
1382 char aty_rom_sig[] = "761295520";
|
1915
|
1383 char *radeon_sig[] = {
|
|
1384 "RG6",
|
|
1385 "RADEON"
|
|
1386 };
|
1911
|
1387
|
|
1388 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
|
1389 stage = 1;
|
|
1390
|
|
1391 rom_base = (char *)ioremap(segstart, 0x1000);
|
|
1392
|
|
1393 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
|
|
1394 stage = 2;
|
|
1395
|
|
1396
|
|
1397 if (stage != 2) {
|
|
1398 iounmap(rom_base);
|
|
1399 continue;
|
|
1400 }
|
|
1401
|
|
1402 rom = rom_base;
|
|
1403
|
|
1404 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
|
|
1405 if (aty_rom_sig[0] == *rom)
|
|
1406 if (strncmp(aty_rom_sig, rom,
|
|
1407 strlen(aty_rom_sig)) == 0)
|
|
1408 stage = 3;
|
|
1409 rom++;
|
|
1410 }
|
|
1411 if (stage != 3) {
|
|
1412 iounmap(rom_base);
|
|
1413 continue;
|
|
1414 }
|
|
1415 rom = rom_base;
|
|
1416
|
|
1417 for (i = 0; (i < 512) && (stage != 4); i++) {
|
1915
|
1418 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
|
|
1419 if (radeon_sig[j][0] == *rom)
|
|
1420 if (strncmp(radeon_sig[j], rom,
|
|
1421 strlen(radeon_sig[j])) == 0) {
|
|
1422 stage = 4;
|
|
1423 break;
|
|
1424 }
|
|
1425 }
|
1911
|
1426 rom++;
|
|
1427 }
|
|
1428 if (stage != 4) {
|
|
1429 iounmap(rom_base);
|
|
1430 continue;
|
|
1431 }
|
|
1432
|
|
1433 return rom_base;
|
|
1434 }
|
|
1435 #endif
|
|
1436 return NULL;
|
|
1437 }
|
|
1438
|
|
1439
|
|
1440
|
|
1441 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
|
|
1442 {
|
|
1443 void *bios_header;
|
|
1444 void *header_ptr;
|
|
1445 u16 bios_header_offset, pll_info_offset;
|
|
1446 PLL_BLOCK pll;
|
|
1447
|
|
1448 if (bios_seg) {
|
|
1449 bios_header = bios_seg + 0x48L;
|
|
1450 header_ptr = bios_header;
|
|
1451
|
|
1452 bios_header_offset = readw(header_ptr);
|
|
1453 bios_header = bios_seg + bios_header_offset;
|
|
1454 bios_header += 0x30;
|
|
1455
|
|
1456 header_ptr = bios_header;
|
|
1457 pll_info_offset = readw(header_ptr);
|
|
1458 header_ptr = bios_seg + pll_info_offset;
|
|
1459
|
|
1460 memcpy_fromio(&pll, header_ptr, 50);
|
|
1461
|
|
1462 rinfo->pll.xclk = (u32)pll.XCLK;
|
|
1463 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
|
|
1464 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
|
|
1465 rinfo->pll.ppll_min = pll.PCLK_min_freq;
|
|
1466 rinfo->pll.ppll_max = pll.PCLK_max_freq;
|
|
1467 } else {
|
|
1468 /* no BIOS or BIOS not found, use defaults */
|
|
1469
|
|
1470 rinfo->pll.ppll_max = 35000;
|
|
1471 rinfo->pll.ppll_min = 12000;
|
|
1472 rinfo->pll.xclk = 16600;
|
|
1473 rinfo->pll.ref_div = 67;
|
|
1474 rinfo->pll.ref_clk = 2700;
|
|
1475 }
|
|
1476 }
|
|
1477
|
2132
|
1478 static void radeon_init_common_regs(struct radeonfb_info *rinfo,
|
|
1479 struct radeon_regs *save)
|
|
1480 {
|
|
1481 RTRACE("radeonfb: radeon_init_common_regs is called\n");
|
|
1482 save->ovr_clr = 0;
|
|
1483 save->ovr_wid_left_right= 0;
|
|
1484 save->ovr_wid_top_bottom= 0;
|
|
1485 save->ov0_scale_cntl = 0;
|
|
1486 save->mpp_tb_config = 0;
|
|
1487 save->mpp_gp_config = 0;
|
|
1488 save->subpic_cntl = 0;
|
|
1489 save->viph_control = 0;
|
|
1490 save->i2c_cntl_1 = 0;
|
|
1491 save->rbbm_soft_reset = 0;
|
|
1492 save->cap0_trig_cntl = 0;
|
|
1493 save->cap1_trig_cntl = 0;
|
|
1494 save->bus_cntl = rinfo->BusCntl;
|
|
1495 /*
|
|
1496 * If bursts are enabled, turn on discards
|
|
1497 * Radeon doesn't have write bursts
|
|
1498 */
|
2160
|
1499 if (save->bus_cntl & (BUS_READ_BURST))
|
|
1500 save->bus_cntl |= BUS_RD_DISCARD_EN;
|
2132
|
1501 }
|
2142
|
1502
|
2132
|
1503 static int radeon_init_crtc_regs(struct radeonfb_info *rinfo,
|
|
1504 struct radeon_regs *save,
|
|
1505 struct fb_var_screeninfo *mode)
|
|
1506 {
|
|
1507 int hTotal, vTotal, hSyncStart, hSyncEnd,
|
2142
|
1508 vSyncStart, vSyncEnd, cSync;
|
2132
|
1509 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
|
|
1510 u8 hsync_fudge_fp[] = { 2, 2, 0, 0, 5, 5 };
|
2142
|
1511 u32 sync;
|
2132
|
1512 int format = 0;
|
|
1513 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
|
|
1514 int prim_mon;
|
|
1515
|
|
1516 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
1517
|
|
1518 rinfo->xres = mode->xres;
|
|
1519 rinfo->yres = mode->yres;
|
|
1520 rinfo->pixclock = mode->pixclock;
|
|
1521
|
|
1522 hSyncStart = mode->xres + mode->right_margin;
|
|
1523 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1524 hTotal = hSyncEnd + mode->left_margin;
|
|
1525
|
|
1526 vSyncStart = mode->yres + mode->lower_margin;
|
|
1527 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1528 vTotal = vSyncEnd + mode->upper_margin;
|
|
1529
|
2135
|
1530 if(((prim_mon == MT_DFP) || (prim_mon == MT_LCD)))
|
|
1531 {
|
|
1532 if(rinfo->PanelXRes < mode->xres)
|
|
1533 rinfo->xres = mode->xres = rinfo->PanelXRes;
|
|
1534 if(rinfo->PanelYRes < mode->yres)
|
|
1535 rinfo->yres = mode->yres = rinfo->PanelYRes;
|
|
1536 hTotal = mode->xres + rinfo->HBlank + mode->left_margin;
|
|
1537 hSyncStart = mode->xres + rinfo->HOverPlus + mode->right_margin;
|
|
1538 hSyncEnd = hSyncStart + rinfo->HSyncWidth + mode->hsync_len;
|
|
1539 vTotal = mode->yres + rinfo->VBlank + mode->upper_margin;
|
|
1540 vSyncStart = mode->yres + rinfo->VOverPlus + mode->lower_margin;
|
|
1541 vSyncEnd = vSyncStart + rinfo->VSyncWidth + mode->vsync_len;
|
|
1542 }
|
|
1543
|
2132
|
1544 sync = mode->sync;
|
|
1545
|
|
1546 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
|
|
1547 hSyncStart, hSyncEnd, hTotal);
|
|
1548 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
|
|
1549 vSyncStart, vSyncEnd, vTotal);
|
|
1550
|
|
1551 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1552 vsync_wid = vSyncEnd - vSyncStart;
|
|
1553 if (hsync_wid == 0)
|
|
1554 hsync_wid = 1;
|
|
1555 else if (hsync_wid > 0x3f) /* max */
|
|
1556 hsync_wid = 0x3f;
|
|
1557 vsync_wid = mode->vsync_len;
|
|
1558 if (vsync_wid == 0)
|
|
1559 vsync_wid = 1;
|
|
1560 else if (vsync_wid > 0x1f) /* max */
|
|
1561 vsync_wid = 0x1f;
|
|
1562
|
|
1563 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
|
1564
|
|
1565 switch (mode->bits_per_pixel) {
|
|
1566 case 8:
|
|
1567 format = DST_8BPP;
|
|
1568 bytpp = 1;
|
|
1569 break;
|
|
1570 case 16:
|
|
1571 format = DST_16BPP;
|
|
1572 bytpp = 2;
|
|
1573 break;
|
|
1574 case 24:
|
|
1575 format = DST_24BPP;
|
|
1576 bytpp = 3;
|
|
1577 break;
|
|
1578 case 32:
|
|
1579 format = DST_32BPP;
|
|
1580 bytpp = 4;
|
|
1581 break;
|
2142
|
1582 default:
|
|
1583 printk("radeonfb: Unsupported pixel depth (%d)\n", mode->bits_per_pixel);
|
|
1584 return 0;
|
2132
|
1585 }
|
|
1586
|
|
1587 if ((prim_mon == MT_DFP) || (prim_mon == MT_LCD))
|
|
1588 hsync_fudge = hsync_fudge_fp[format-1];
|
|
1589 else
|
|
1590 hsync_fudge = hsync_adj_tab[format-1];
|
|
1591
|
|
1592 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1593 save->crtc_gen_cntl = (CRTC_EXT_DISP_EN
|
|
1594 | CRTC_EN
|
|
1595 | (format << 8)
|
|
1596 /* | CRTC_DBL_SCAN_EN*/);
|
|
1597
|
2142
|
1598 if((prim_mon == MT_DFP) || (prim_mon == MT_LCD)) {
|
2132
|
1599 save->crtc_ext_cntl = VGA_ATI_LINEAR |
|
|
1600 XCRT_CNT_EN;
|
|
1601 save->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
|
|
1602 CRTC_INTERLACE_EN);
|
|
1603 }
|
|
1604 else
|
|
1605 save->crtc_ext_cntl = VGA_ATI_LINEAR |
|
|
1606 XCRT_CNT_EN |
|
|
1607 CRTC_CRT_ON;
|
|
1608
|
2142
|
1609 save->dac_cntl = (DAC_MASK_ALL
|
|
1610 | DAC_VGA_ADR_EN
|
|
1611 | DAC_8BIT_EN);
|
2132
|
1612
|
|
1613 save->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
|
|
1614 ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
|
1615
|
|
1616 save->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
|
1617 ((mode->yres - 1) << 16);
|
|
1618
|
2142
|
1619 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
|
|
1620 | (hsync_wid << 16)
|
|
1621 | (mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0
|
|
1622 : CRTC_H_SYNC_POL));
|
|
1623
|
|
1624 save->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff)
|
|
1625 | (vsync_wid << 16)
|
|
1626 | (mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0
|
|
1627 : CRTC_V_SYNC_POL));
|
|
1628
|
|
1629 save->crtc_pitch = ((mode->xres * bytpp) +
|
|
1630 ((mode->bits_per_pixel) - 1)) /
|
|
1631 (mode->bits_per_pixel);
|
|
1632 save->crtc_pitch |= save->crtc_pitch<<16;
|
2132
|
1633
|
|
1634 #if defined(__BIG_ENDIAN)
|
|
1635 save->surface_cntl = SURF_TRANSLATION_DIS;
|
|
1636 switch (mode->bits_per_pixel) {
|
|
1637 case 16:
|
|
1638 save->surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
|
1639 break;
|
|
1640 case 24:
|
|
1641 case 32:
|
|
1642 save->surface_cntl |= NONSURF_AP0_SWP_32BPP;
|
|
1643 break;
|
|
1644 }
|
|
1645 #endif
|
|
1646
|
|
1647 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
|
1648 & ~(0x3f)) / 64;
|
|
1649
|
|
1650 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
|
2142
|
1651 save->crtc_h_total_disp, save->crtc_h_sync_strt_wid);
|
2132
|
1652 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
|
2142
|
1653 save->crtc_v_total_disp, save->crtc_v_sync_strt_wid);
|
2132
|
1654
|
|
1655 save->xres = mode->xres;
|
|
1656 save->yres = mode->yres;
|
|
1657
|
|
1658 save->crtc_offset = 0;
|
|
1659 save->crtc_offset_cntl = 0;
|
|
1660
|
|
1661 rinfo->bpp = mode->bits_per_pixel;
|
2133
|
1662 return 1;
|
2132
|
1663 }
|
|
1664
|
|
1665 static int radeon_init_crtc2_regs(struct radeonfb_info *rinfo,
|
|
1666 struct radeon_regs *save,
|
|
1667 struct fb_var_screeninfo *mode)
|
|
1668 {
|
|
1669 int format;
|
|
1670 int hsync_start;
|
|
1671 int hsync_wid;
|
|
1672 int hsync_fudge;
|
|
1673 int vsync_wid;
|
|
1674 int bytpp;
|
|
1675 int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
|
|
1676 int hTotal, vTotal, hSyncStart, hSyncEnd;
|
|
1677 int vSyncStart, vSyncEnd;
|
|
1678 RTRACE("radeonfb: radeon_init_crtc2_regs is called\n");
|
|
1679
|
|
1680 switch (mode->bits_per_pixel) {
|
|
1681 case 8: format = 2; bytpp = 1; break;
|
|
1682 case 16: format = 4; bytpp = 2; break; /* 565 */
|
|
1683 case 24: format = 5; bytpp = 3; break; /* RGB */
|
|
1684 case 32: format = 6; bytpp = 4; break; /* xRGB */
|
|
1685 default:
|
|
1686 printk("radeonfb: Unsupported pixel depth (%d)\n", mode->bits_per_pixel);
|
|
1687 return 0;
|
|
1688 }
|
|
1689
|
|
1690 hsync_fudge = hsync_fudge_default[format-1];
|
|
1691
|
|
1692 save->crtc2_gen_cntl = (CRTC2_EN
|
|
1693 | CRTC2_CRT2_ON
|
|
1694 | (format << 8)
|
|
1695 /*| CRTC2_DBL_SCAN_EN*/);
|
|
1696
|
|
1697 if(!rinfo->isM7)
|
|
1698 save->dac2_cntl = rinfo->init_state.dac2_cntl
|
|
1699 /*| DAC2_DAC2_CLK_SEL*/
|
|
1700 | DAC2_DAC_CLK_SEL;
|
|
1701 else
|
|
1702 {
|
|
1703 save->disp_output_cntl =
|
|
1704 ((rinfo->init_state.disp_output_cntl &
|
|
1705 (u32)~DISP_DAC_SOURCE_MASK)
|
|
1706 | DISP_DAC_SOURCE_CRTC2);
|
|
1707 }
|
|
1708
|
|
1709 hSyncStart = mode->xres + mode->right_margin;
|
|
1710 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1711 hTotal = hSyncEnd + mode->left_margin;
|
|
1712
|
|
1713 vSyncStart = mode->yres + mode->lower_margin;
|
|
1714 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1715 vTotal = vSyncEnd + mode->upper_margin;
|
|
1716
|
|
1717 save->crtc2_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff)
|
|
1718 | ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
|
1719
|
|
1720 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1721 if (!hsync_wid) hsync_wid = 1;
|
|
1722 if (hsync_wid > 0x3f) hsync_wid = 0x3f;
|
|
1723 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1724
|
|
1725 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
|
|
1726 | (hsync_wid << 16)
|
|
1727 | ((mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
|
1728 ? 0
|
|
1729 : CRTC_H_SYNC_POL));
|
|
1730
|
|
1731 /* This works for double scan mode. */
|
|
1732 save->crtc2_v_total_disp = (((vTotal - 1) & 0xffff)
|
|
1733 | ((mode->yres - 1) << 16));
|
|
1734
|
|
1735 vsync_wid = vSyncEnd - vSyncStart;
|
|
1736 if (!vsync_wid) vsync_wid = 1;
|
|
1737 if (vsync_wid > 0x1f) vsync_wid = 0x1f;
|
|
1738
|
|
1739 save->crtc2_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff)
|
|
1740 | (vsync_wid << 16)
|
|
1741 | ((mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
|
1742 ? 0
|
|
1743 : CRTC2_V_SYNC_POL));
|
|
1744
|
|
1745 save->crtc2_offset = 0;
|
|
1746 save->crtc2_offset_cntl = 0;
|
|
1747
|
|
1748 save->crtc2_pitch = ((mode->xres * bytpp) +
|
|
1749 ((mode->bits_per_pixel) -1)) /
|
|
1750 (mode->bits_per_pixel);
|
|
1751 save->crtc2_pitch |= save->crtc2_pitch << 16;
|
|
1752
|
|
1753 RTRACE("radeonfb: radeon_init_crtc2_regs returns SUCCESS\n");
|
|
1754 return 1;
|
|
1755 }
|
|
1756
|
|
1757 static void radeon_init_fp_regs(struct radeonfb_info *rinfo,
|
|
1758 struct radeon_regs *save,
|
|
1759 struct fb_var_screeninfo *mode)
|
|
1760 {
|
|
1761 float Hratio, Vratio;
|
|
1762 int prim_mon;
|
|
1763 RTRACE("radeonfb: radeon_init_fp_regs is called\n");
|
|
1764 if(rinfo->PanelXRes == 0 || rinfo->PanelYRes == 0)
|
|
1765 {
|
|
1766 Hratio = 1;
|
|
1767 Vratio = 1;
|
|
1768 }
|
|
1769 else
|
|
1770 {
|
|
1771 if (mode->xres > rinfo->PanelXRes) mode->xres = rinfo->PanelXRes;
|
|
1772 if (mode->yres > rinfo->PanelYRes) mode->yres = rinfo->PanelYRes;
|
|
1773
|
|
1774 Hratio = (float)mode->xres/(float)rinfo->PanelXRes;
|
|
1775 Vratio = (float)mode->yres/(float)rinfo->PanelYRes;
|
|
1776 }
|
|
1777
|
|
1778 if (Hratio == 1.0)
|
|
1779 {
|
|
1780 save->fp_horz_stretch = rinfo->init_state.fp_horz_stretch;
|
|
1781 save->fp_horz_stretch &= ~(HORZ_STRETCH_BLEND |
|
|
1782 HORZ_STRETCH_ENABLE);
|
|
1783 }
|
|
1784 else
|
|
1785 {
|
|
1786 save->fp_horz_stretch =
|
|
1787 ((((unsigned long)(Hratio * HORZ_STRETCH_RATIO_MAX +
|
|
1788 0.5)) & HORZ_STRETCH_RATIO_MASK)) |
|
|
1789 (rinfo->init_state.fp_horz_stretch & (HORZ_PANEL_SIZE |
|
|
1790 HORZ_FP_LOOP_STRETCH |
|
|
1791 HORZ_AUTO_RATIO_INC));
|
|
1792 save->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
|
|
1793 HORZ_STRETCH_ENABLE);
|
|
1794 }
|
|
1795 save->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
|
|
1796
|
|
1797 if (Vratio == 1.0)
|
|
1798 {
|
|
1799 save->fp_vert_stretch = rinfo->init_state.fp_vert_stretch;
|
|
1800 save->fp_vert_stretch &= ~(VERT_STRETCH_ENABLE|
|
|
1801 VERT_STRETCH_BLEND);
|
|
1802 }
|
|
1803 else
|
|
1804 {
|
|
1805 save->fp_vert_stretch =
|
|
1806 (((((unsigned long)(Vratio * VERT_STRETCH_RATIO_MAX +
|
|
1807 0.5)) & VERT_STRETCH_RATIO_MASK)) |
|
|
1808 (rinfo->init_state.fp_vert_stretch & (VERT_PANEL_SIZE |
|
|
1809 VERT_STRETCH_RESERVED)));
|
|
1810 save->fp_vert_stretch |= (VERT_STRETCH_ENABLE |
|
|
1811 VERT_STRETCH_BLEND);
|
|
1812 }
|
|
1813 save->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
|
|
1814
|
|
1815 save->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
|
|
1816 ~(FP_SEL_CRTC2 |
|
|
1817 FP_RMX_HVSYNC_CONTROL_EN |
|
|
1818 FP_DFP_SYNC_SEL |
|
|
1819 FP_CRT_SYNC_SEL |
|
|
1820 FP_CRTC_LOCK_8DOT |
|
|
1821 FP_USE_SHADOW_EN |
|
|
1822 FP_CRTC_USE_SHADOW_VEND |
|
|
1823 FP_CRT_SYNC_ALT));
|
|
1824 save->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
|
|
1825 FP_CRTC_DONT_SHADOW_HEND );
|
|
1826
|
|
1827 save->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
|
|
1828 save->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
|
|
1829 save->tmds_crc = rinfo->init_state.tmds_crc;
|
|
1830
|
|
1831 /* Disable CRT output by disabling CRT output for DFP*/
|
|
1832 save->crtc_ext_cntl &= ~CRTC_CRT_ON;
|
|
1833 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
1834 if(prim_mon == MT_LCD)
|
|
1835 {
|
|
1836 save->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
|
|
1837 save->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
|
|
1838 }
|
|
1839 else if(prim_mon == MT_DFP)
|
|
1840 save->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
|
|
1841
|
|
1842 save->fp_crtc_h_total_disp = rinfo->init_state.fp_crtc_h_total_disp;
|
|
1843 save->fp_crtc_v_total_disp = rinfo->init_state.fp_crtc_v_total_disp;
|
|
1844 save->fp_h_sync_strt_wid = rinfo->init_state.fp_h_sync_strt_wid;
|
|
1845 save->fp_v_sync_strt_wid = rinfo->init_state.fp_v_sync_strt_wid;
|
|
1846 }
|
|
1847
|
|
1848 static void radeon_init_pll_regs(struct radeonfb_info *rinfo,
|
|
1849 struct radeon_regs *save,
|
|
1850 struct fb_var_screeninfo *mode)
|
|
1851 {
|
|
1852 u32 dot_clock = 1000000000 / mode->pixclock;
|
|
1853 u32 freq = dot_clock / 10; /* x 100 */
|
|
1854 struct {
|
|
1855 int divider;
|
|
1856 int bitvalue;
|
|
1857 } *post_div, post_divs[] = {
|
|
1858 { 1, 0 },
|
|
1859 { 2, 1 },
|
|
1860 { 4, 2 },
|
|
1861 { 8, 3 },
|
|
1862 { 3, 4 },
|
|
1863 { 16, 5 },
|
|
1864 { 6, 6 },
|
|
1865 { 12, 7 },
|
|
1866 { 0, 0 },
|
|
1867 };
|
|
1868 if (freq > rinfo->pll.ppll_max) freq = rinfo->pll.ppll_max;
|
|
1869 if (freq*12 < rinfo->pll.ppll_min) freq = rinfo->pll.ppll_min / 12;
|
|
1870
|
|
1871 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
1872 rinfo->pll_output_freq = post_div->divider * freq;
|
|
1873 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
|
|
1874 rinfo->pll_output_freq <= rinfo->pll.ppll_max) break;
|
|
1875 }
|
|
1876
|
|
1877 rinfo->post_div = post_div->divider;
|
|
1878 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
|
|
1879 rinfo->pll.ref_clk);
|
|
1880 save->ppll_ref_div = rinfo->pll.ref_div;
|
|
1881 save->ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
|
|
1882 save->htotal_cntl = 0;
|
|
1883
|
|
1884 RTRACE("post div = 0x%x\n", rinfo->post_div);
|
|
1885 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
|
2142
|
1886 RTRACE("ppll_div_3 = 0x%x\n", save->ppll_div_3);
|
2132
|
1887 }
|
|
1888
|
|
1889 static void radeon_init_pll2_regs(struct radeonfb_info *rinfo,
|
|
1890 struct radeon_regs *save,
|
|
1891 struct fb_var_screeninfo *mode)
|
|
1892 {
|
|
1893 u32 dot_clock = 1000000000 / mode->pixclock;
|
|
1894 u32 freq = dot_clock * 100;
|
|
1895 struct {
|
|
1896 int divider;
|
|
1897 int bitvalue;
|
|
1898 } *post_div,
|
|
1899 post_divs[] = {
|
|
1900 /* From RAGE 128 VR/RAGE 128 GL Register
|
|
1901 Reference Manual (Technical Reference
|
|
1902 Manual P/N RRG-G04100-C Rev. 0.04), page
|
|
1903 3-17 (PLL_DIV_[3:0]). */
|
|
1904 { 1, 0 }, /* VCLK_SRC */
|
|
1905 { 2, 1 }, /* VCLK_SRC/2 */
|
|
1906 { 4, 2 }, /* VCLK_SRC/4 */
|
|
1907 { 8, 3 }, /* VCLK_SRC/8 */
|
|
1908 { 3, 4 }, /* VCLK_SRC/3 */
|
|
1909 { 16, 5 }, /* VCLK_SRC/16 */
|
|
1910 { 6, 6 }, /* VCLK_SRC/6 */
|
|
1911 { 12, 7 }, /* VCLK_SRC/12 */
|
|
1912 { 0, 0 }
|
|
1913 };
|
|
1914 RTRACE("radeonfb: radeon_init_pll2_regs is called\n");
|
|
1915
|
|
1916 if (freq > rinfo->pll.ppll_max) freq = rinfo->pll.ppll_max;
|
|
1917 if (freq*12 < rinfo->pll.ppll_min) freq = rinfo->pll.ppll_min/12;
|
|
1918
|
|
1919 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
1920 save->pll_output_freq_2 = post_div->divider * freq;
|
|
1921 if (save->pll_output_freq_2 >= rinfo->pll.ppll_min
|
|
1922 && save->pll_output_freq_2 <= rinfo->pll.ppll_max) break;
|
|
1923 }
|
|
1924
|
|
1925 save->dot_clock_freq_2 = freq;
|
|
1926 save->feedback_div_2 = round_div(rinfo->pll.ref_div
|
|
1927 * save->pll_output_freq_2,
|
|
1928 rinfo->pll.ref_clk);
|
|
1929 save->post_div_2 = post_div->divider;
|
|
1930
|
|
1931 save->p2pll_ref_div = rinfo->pll.ref_div;
|
|
1932 save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
|
|
1933 save->htotal_cntl2 = 0;
|
|
1934 }
|
|
1935
|
|
1936 static int radeon_init_dda_regs(struct radeonfb_info *rinfo,
|
|
1937 struct radeon_regs *save,
|
|
1938 struct fb_var_screeninfo *mode)
|
|
1939 {
|
|
1940 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
|
|
1941 int useable_precision, roff, ron;
|
|
1942 int min_bits;
|
|
1943 const int DispFifoWidth=128,DispFifoDepth=32;
|
|
1944 /* DDA */
|
|
1945 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
|
|
1946 rinfo->pll.ref_div * rinfo->post_div);
|
|
1947 xclk_freq = rinfo->pll.xclk;
|
|
1948
|
|
1949 xclk_per_trans = round_div(xclk_freq * DispFifoWidth,
|
|
1950 vclk_freq * mode->bits_per_pixel);
|
|
1951
|
|
1952 min_bits = min_bits_req(xclk_per_trans);
|
|
1953 useable_precision = min_bits + 1;
|
|
1954
|
|
1955 xclk_per_trans_precise = round_div((xclk_freq * DispFifoWidth)
|
|
1956 << (11 - useable_precision),
|
|
1957 vclk_freq * mode->bits_per_pixel);
|
|
1958
|
|
1959 ron = (4 * rinfo->ram.mb +
|
|
1960 3 * _max(rinfo->ram.trcd - 2, 0) +
|
|
1961 2 * rinfo->ram.trp +
|
|
1962 rinfo->ram.twr +
|
|
1963 rinfo->ram.cl +
|
|
1964 rinfo->ram.tr2w +
|
|
1965 xclk_per_trans) << (11 - useable_precision);
|
|
1966 roff = xclk_per_trans_precise * (DispFifoDepth - 4);
|
|
1967
|
|
1968 RTRACE("ron = %d, roff = %d\n", ron, roff);
|
|
1969 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
|
|
1970
|
|
1971 if ((ron + rinfo->ram.rloop) >= roff) {
|
|
1972 printk("radeonfb: error ron out of range\n");
|
|
1973 return -1;
|
|
1974 }
|
|
1975
|
|
1976 save->dda_config = (xclk_per_trans_precise |
|
|
1977 (useable_precision << 16) |
|
|
1978 (rinfo->ram.rloop << 20));
|
|
1979 save->dda_on_off = (ron << 16) | roff;
|
2134
|
1980 return 1;
|
2132
|
1981 }
|
|
1982
|
|
1983 /*
|
|
1984 static void radeon_init_palette(struct radeon_regs *save)
|
|
1985 {
|
|
1986 save->palette_valid = 0;
|
|
1987 }
|
|
1988 */
|
|
1989
|
|
1990 static int radeon_init_mode(struct radeonfb_info *rinfo,
|
|
1991 struct radeon_regs *save,
|
|
1992 struct fb_var_screeninfo *mode)
|
|
1993 {
|
|
1994 int prim_mon;
|
|
1995 RTRACE("radeonfb: radeon_init_mode is called\n");
|
|
1996 if(DUAL_MONITOR(rinfo))
|
|
1997 {
|
|
1998 if (!radeon_init_crtc2_regs(rinfo, save, mode))
|
|
1999 return 0;
|
|
2000 radeon_init_pll2_regs(rinfo, save, mode);
|
|
2001 }
|
|
2002 radeon_init_common_regs(rinfo, save);
|
|
2003 if(!radeon_init_crtc_regs(rinfo, save, mode))
|
|
2004 return 0;
|
|
2005 if(mode->pixclock)
|
|
2006 {
|
|
2007 radeon_init_pll_regs(rinfo, save, mode);
|
|
2008 if (!radeon_init_dda_regs(rinfo, save, mode))
|
|
2009 return 0;
|
|
2010 }
|
|
2011 else
|
|
2012 {
|
|
2013 save->ppll_ref_div = rinfo->init_state.ppll_ref_div;
|
|
2014 save->ppll_div_3 = rinfo->init_state.ppll_div_3;
|
|
2015 save->htotal_cntl = rinfo->init_state.htotal_cntl;
|
|
2016 save->dda_config = rinfo->init_state.dda_config;
|
|
2017 save->dda_on_off = rinfo->init_state.dda_on_off;
|
|
2018 }
|
|
2019 /* radeon_init_palete here */
|
|
2020 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
2021 if (((prim_mon == MT_DFP) || (prim_mon == MT_LCD)))
|
|
2022 {
|
2135
|
2023 radeon_init_fp_regs(rinfo, save, mode);
|
2132
|
2024 }
|
|
2025
|
|
2026 RTRACE("radeonfb: radeon_init_mode returns SUCCESS\n");
|
|
2027 return 1;
|
|
2028 }
|
|
2029
|
1911
|
2030 static void radeon_engine_init (struct radeonfb_info *rinfo)
|
|
2031 {
|
|
2032 u32 temp;
|
|
2033
|
|
2034 /* disable 3D engine */
|
|
2035 OUTREG(RB3D_CNTL, 0);
|
|
2036
|
|
2037 radeon_engine_reset ();
|
|
2038
|
|
2039 radeon_fifo_wait (1);
|
|
2040 OUTREG(DSTCACHE_MODE, 0);
|
|
2041
|
|
2042 /* XXX */
|
|
2043 rinfo->pitch = ((rinfo->xres * (rinfo->depth / 8) + 0x3f)) >> 6;
|
|
2044
|
|
2045 radeon_fifo_wait (1);
|
|
2046 temp = INREG(DEFAULT_PITCH_OFFSET);
|
|
2047 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
|
|
2048 (rinfo->pitch << 0x16)));
|
|
2049
|
|
2050 radeon_fifo_wait (1);
|
|
2051 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
2052
|
|
2053 radeon_fifo_wait (1);
|
|
2054 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
|
|
2055 DEFAULT_SC_BOTTOM_MAX));
|
|
2056
|
|
2057 temp = radeon_get_dstbpp(rinfo->depth);
|
|
2058 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
|
|
2059 radeon_fifo_wait (1);
|
|
2060 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2061 GMC_BRUSH_SOLID_COLOR |
|
|
2062 GMC_SRC_DATATYPE_COLOR));
|
|
2063
|
|
2064 radeon_fifo_wait (7);
|
|
2065
|
|
2066 /* clear line drawing regs */
|
|
2067 OUTREG(DST_LINE_START, 0);
|
|
2068 OUTREG(DST_LINE_END, 0);
|
|
2069
|
|
2070 /* set brush color regs */
|
|
2071 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
2072 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
2073
|
|
2074 /* set source color regs */
|
|
2075 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
2076 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
2077
|
|
2078 /* default write mask */
|
|
2079 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2080
|
|
2081 radeon_engine_idle ();
|
|
2082 }
|
|
2083
|
|
2084
|
|
2085
|
|
2086 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
|
|
2087 {
|
|
2088 struct fb_info *info;
|
|
2089
|
|
2090 info = &rinfo->info;
|
|
2091
|
|
2092 strcpy (info->modename, rinfo->name);
|
|
2093 info->node = -1;
|
|
2094 info->flags = FBINFO_FLAG_DEFAULT;
|
|
2095 info->fbops = &radeon_fb_ops;
|
|
2096 info->display_fg = NULL;
|
|
2097 strncpy (info->fontname, fontname, sizeof (info->fontname));
|
|
2098 info->fontname[sizeof (info->fontname) - 1] = 0;
|
|
2099 info->changevar = NULL;
|
|
2100 info->switch_con = radeonfb_switch;
|
|
2101 info->updatevar = radeonfb_updatevar;
|
|
2102 info->blank = radeonfb_blank;
|
|
2103
|
|
2104 if (radeon_init_disp (rinfo) < 0)
|
|
2105 return -1;
|
|
2106
|
|
2107 return 0;
|
|
2108 }
|
|
2109
|
|
2110
|
|
2111
|
|
2112 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
|
|
2113 {
|
|
2114 struct fb_info *info;
|
|
2115 struct display *disp;
|
|
2116
|
|
2117 info = &rinfo->info;
|
|
2118 disp = &rinfo->disp;
|
|
2119
|
|
2120 disp->var = radeonfb_default_var;
|
|
2121 info->disp = disp;
|
|
2122
|
1914
|
2123 radeon_set_dispsw (rinfo, disp);
|
1911
|
2124
|
|
2125 if (noaccel)
|
|
2126 disp->scrollmode = SCROLL_YREDRAW;
|
|
2127 else
|
|
2128 disp->scrollmode = 0;
|
|
2129
|
|
2130 rinfo->currcon_display = disp;
|
|
2131
|
|
2132 if ((radeon_init_disp_var (rinfo)) < 0)
|
|
2133 return -1;
|
|
2134
|
|
2135 return 0;
|
|
2136 }
|
|
2137
|
|
2138
|
|
2139
|
|
2140 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
|
|
2141 {
|
|
2142 #ifndef MODULE
|
|
2143 if (mode_option)
|
|
2144 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
|
|
2145 NULL, 0, NULL, 8);
|
|
2146 else
|
|
2147 #endif
|
|
2148 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
|
|
2149 NULL, 0, NULL, 0);
|
|
2150
|
|
2151 if (noaccel)
|
|
2152 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
|
|
2153 else
|
|
2154 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
|
|
2155
|
|
2156 return 0;
|
|
2157 }
|
|
2158
|
|
2159
|
1914
|
2160 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
|
1911
|
2161 {
|
|
2162 int accel;
|
|
2163
|
|
2164 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
|
|
2165
|
|
2166 disp->dispsw_data = NULL;
|
|
2167
|
|
2168 disp->screen_base = (char*)rinfo->fb_base;
|
|
2169 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
2170 disp->type_aux = 0;
|
|
2171 disp->ypanstep = 1;
|
|
2172 disp->ywrapstep = 0;
|
|
2173 disp->can_soft_blank = 1;
|
|
2174 disp->inverse = 0;
|
|
2175
|
|
2176 rinfo->depth = disp->var.bits_per_pixel;
|
|
2177 switch (disp->var.bits_per_pixel) {
|
|
2178 #ifdef FBCON_HAS_CFB8
|
|
2179 case 8:
|
1914
|
2180 disp->dispsw = &fbcon_cfb8;
|
1911
|
2181 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
2182 disp->line_length = disp->var.xres_virtual;
|
|
2183 break;
|
|
2184 #endif
|
|
2185 #ifdef FBCON_HAS_CFB16
|
|
2186 case 16:
|
|
2187 disp->dispsw = &fbcon_cfb16;
|
|
2188 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
2189 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2190 disp->line_length = disp->var.xres_virtual * 2;
|
|
2191 break;
|
|
2192 #endif
|
|
2193 #ifdef FBCON_HAS_CFB32
|
1914
|
2194 case 24:
|
|
2195 disp->dispsw = &fbcon_cfb24;
|
|
2196 disp->dispsw_data = &rinfo->con_cmap.cfb24;
|
|
2197 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2198 disp->line_length = disp->var.xres_virtual * 4;
|
|
2199 break;
|
|
2200 #endif
|
|
2201 #ifdef FBCON_HAS_CFB32
|
1911
|
2202 case 32:
|
|
2203 disp->dispsw = &fbcon_cfb32;
|
|
2204 disp->dispsw_data = &rinfo->con_cmap.cfb32;
|
|
2205 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2206 disp->line_length = disp->var.xres_virtual * 4;
|
|
2207 break;
|
|
2208 #endif
|
|
2209 default:
|
|
2210 printk ("radeonfb: setting fbcon_dummy renderer\n");
|
|
2211 disp->dispsw = &fbcon_dummy;
|
|
2212 }
|
|
2213
|
|
2214 return;
|
|
2215 }
|
|
2216
|
|
2217
|
|
2218
|
|
2219 /*
|
|
2220 * fb ops
|
|
2221 */
|
|
2222
|
|
2223 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
2224 struct fb_info *info)
|
|
2225 {
|
|
2226 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2227 struct display *disp;
|
|
2228
|
|
2229 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2230
|
|
2231 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
|
|
2232 strcpy (fix->id, rinfo->name);
|
|
2233
|
|
2234 fix->smem_start = rinfo->fb_base_phys;
|
|
2235 fix->smem_len = rinfo->video_ram;
|
|
2236
|
|
2237 fix->type = disp->type;
|
|
2238 fix->type_aux = disp->type_aux;
|
|
2239 fix->visual = disp->visual;
|
|
2240
|
|
2241 fix->xpanstep = 1;
|
|
2242 fix->ypanstep = 1;
|
|
2243 fix->ywrapstep = 0;
|
|
2244
|
|
2245 fix->line_length = disp->line_length;
|
|
2246
|
|
2247 fix->mmio_start = rinfo->mmio_base_phys;
|
|
2248 fix->mmio_len = RADEON_REGSIZE;
|
|
2249 if (noaccel)
|
|
2250 fix->accel = FB_ACCEL_NONE;
|
|
2251 else
|
|
2252 fix->accel = 40; /* XXX */
|
|
2253
|
|
2254 return 0;
|
|
2255 }
|
|
2256
|
|
2257
|
|
2258
|
|
2259 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
2260 struct fb_info *info)
|
|
2261 {
|
|
2262 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2263
|
|
2264 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
|
|
2265
|
|
2266 return 0;
|
|
2267 }
|
|
2268
|
|
2269
|
|
2270
|
|
2271 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
2272 struct fb_info *info)
|
|
2273 {
|
|
2274 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2275 struct display *disp;
|
|
2276 struct fb_var_screeninfo v;
|
2132
|
2277 int nom, den, accel, err;
|
1911
|
2278 unsigned chgvar = 0;
|
|
2279
|
|
2280 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2281
|
|
2282 accel = var->accel_flags & FB_ACCELF_TEXT;
|
|
2283
|
|
2284 if (con >= 0) {
|
|
2285 chgvar = ((disp->var.xres != var->xres) ||
|
|
2286 (disp->var.yres != var->yres) ||
|
|
2287 (disp->var.xres_virtual != var->xres_virtual) ||
|
|
2288 (disp->var.yres_virtual != var->yres_virtual) ||
|
1914
|
2289 (disp->var.bits_per_pixel != var->bits_per_pixel) ||
|
1911
|
2290 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
|
|
2291 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
|
|
2292 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
|
|
2293 }
|
|
2294
|
|
2295 memcpy (&v, var, sizeof (v));
|
|
2296
|
|
2297 switch (v.bits_per_pixel) {
|
|
2298 #ifdef FBCON_HAS_CFB8
|
|
2299 case 8:
|
|
2300 nom = den = 1;
|
|
2301 disp->line_length = v.xres_virtual;
|
|
2302 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
2303 v.red.offset = v.green.offset = v.blue.offset = 0;
|
|
2304 v.red.length = v.green.length = v.blue.length = 8;
|
1914
|
2305 v.transp.offset = v.transp.length = 0;
|
1911
|
2306 break;
|
|
2307 #endif
|
|
2308
|
|
2309 #ifdef FBCON_HAS_CFB16
|
|
2310 case 16:
|
|
2311 nom = 2;
|
|
2312 den = 1;
|
|
2313 disp->line_length = v.xres_virtual * 2;
|
|
2314 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2315 v.red.offset = 11;
|
|
2316 v.green.offset = 5;
|
|
2317 v.blue.offset = 0;
|
|
2318 v.red.length = 5;
|
|
2319 v.green.length = 6;
|
|
2320 v.blue.length = 5;
|
1914
|
2321 v.transp.offset = v.transp.length = 0;
|
1911
|
2322 break;
|
|
2323 #endif
|
|
2324
|
1914
|
2325 #ifdef FBCON_HAS_CFB24
|
|
2326 case 24:
|
|
2327 nom = 4;
|
|
2328 den = 1;
|
|
2329 disp->line_length = v.xres_virtual * 3;
|
|
2330 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2331 v.red.offset = 16;
|
|
2332 v.green.offset = 8;
|
|
2333 v.blue.offset = 0;
|
|
2334 v.red.length = v.blue.length = v.green.length = 8;
|
|
2335 v.transp.offset = v.transp.length = 0;
|
|
2336 break;
|
|
2337 #endif
|
1911
|
2338 #ifdef FBCON_HAS_CFB32
|
|
2339 case 32:
|
|
2340 nom = 4;
|
|
2341 den = 1;
|
|
2342 disp->line_length = v.xres_virtual * 4;
|
|
2343 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2344 v.red.offset = 16;
|
|
2345 v.green.offset = 8;
|
|
2346 v.blue.offset = 0;
|
|
2347 v.red.length = v.blue.length = v.green.length = 8;
|
1914
|
2348 v.transp.offset = 24;
|
|
2349 v.transp.length = 8;
|
1911
|
2350 break;
|
|
2351 #endif
|
|
2352 default:
|
|
2353 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
|
|
2354 var->xres, var->yres, var->bits_per_pixel);
|
|
2355 return -EINVAL;
|
|
2356 }
|
|
2357
|
1914
|
2358 if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
|
|
2359 return -EINVAL;
|
1911
|
2360
|
|
2361 if (v.xoffset < 0)
|
|
2362 v.xoffset = 0;
|
|
2363 if (v.yoffset < 0)
|
|
2364 v.yoffset = 0;
|
|
2365
|
|
2366 if (v.xoffset > v.xres_virtual - v.xres)
|
|
2367 v.xoffset = v.xres_virtual - v.xres - 1;
|
|
2368
|
|
2369 if (v.yoffset > v.yres_virtual - v.yres)
|
|
2370 v.yoffset = v.yres_virtual - v.yres - 1;
|
|
2371
|
|
2372 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
|
|
2373 v.transp.offset = v.transp.length =
|
|
2374 v.transp.msb_right = 0;
|
|
2375
|
|
2376 switch (v.activate & FB_ACTIVATE_MASK) {
|
|
2377 case FB_ACTIVATE_TEST:
|
|
2378 return 0;
|
|
2379 case FB_ACTIVATE_NXTOPEN:
|
|
2380 case FB_ACTIVATE_NOW:
|
|
2381 break;
|
|
2382 default:
|
|
2383 return -EINVAL;
|
|
2384 }
|
|
2385
|
|
2386 memcpy (&disp->var, &v, sizeof (v));
|
|
2387
|
1914
|
2388 if (chgvar) {
|
|
2389 radeon_set_dispsw(rinfo, disp);
|
|
2390
|
|
2391 if (noaccel)
|
|
2392 disp->scrollmode = SCROLL_YREDRAW;
|
|
2393 else
|
|
2394 disp->scrollmode = 0;
|
|
2395
|
|
2396 if (info && info->changevar)
|
|
2397 info->changevar(con);
|
|
2398 }
|
|
2399
|
2132
|
2400 err = radeon_load_video_mode (rinfo, &v);
|
|
2401 if(err) return err;
|
1914
|
2402 do_install_cmap(con, info);
|
|
2403
|
1911
|
2404 return 0;
|
|
2405 }
|
|
2406
|
|
2407
|
|
2408
|
|
2409 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
2410 struct fb_info *info)
|
|
2411 {
|
|
2412 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2413 struct display *disp;
|
|
2414
|
|
2415 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2416
|
|
2417 if (con == rinfo->currcon) {
|
|
2418 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
|
|
2419 return rc;
|
|
2420 } else if (disp->cmap.len)
|
|
2421 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
|
|
2422 else
|
|
2423 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
|
|
2424 cmap, kspc ? 0 : 2);
|
|
2425
|
|
2426 return 0;
|
|
2427 }
|
|
2428
|
|
2429
|
|
2430
|
|
2431 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
2432 struct fb_info *info)
|
|
2433 {
|
|
2434 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2435 struct display *disp;
|
|
2436 unsigned int cmap_len;
|
|
2437
|
|
2438 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2439
|
|
2440 cmap_len = radeon_get_cmap_len (&disp->var);
|
|
2441 if (disp->cmap.len != cmap_len) {
|
|
2442 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
|
|
2443 if (err)
|
|
2444 return err;
|
|
2445 }
|
|
2446
|
|
2447 if (con == rinfo->currcon) {
|
|
2448 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
|
|
2449 return rc;
|
|
2450 } else
|
|
2451 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
|
|
2452
|
|
2453 return 0;
|
|
2454 }
|
|
2455
|
|
2456
|
|
2457
|
|
2458 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
2459 struct fb_info *info)
|
|
2460 {
|
|
2461 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
2462 u32 offset, xoffset, yoffset;
|
|
2463
|
|
2464 xoffset = (var->xoffset + 7) & ~7;
|
|
2465 yoffset = var->yoffset;
|
1911
|
2466
|
1914
|
2467 if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
|
|
2468 var->yres_virtual))
|
|
2469 return -EINVAL;
|
1911
|
2470
|
1914
|
2471 offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
|
|
2472
|
|
2473 OUTREG(CRTC_OFFSET, offset);
|
1911
|
2474
|
|
2475 return 0;
|
|
2476 }
|
|
2477
|
|
2478
|
1914
|
2479 static void do_install_cmap(int con, struct fb_info *info)
|
|
2480 {
|
|
2481 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2482
|
|
2483 if (con != rinfo->currcon)
|
|
2484 return;
|
|
2485
|
|
2486 if (fb_display[con].cmap.len)
|
|
2487 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
|
|
2488 else {
|
|
2489 int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
|
|
2490 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
|
|
2491 }
|
|
2492 }
|
|
2493
|
|
2494
|
|
2495 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
2496 struct fb_var_screeninfo *var,
|
|
2497 struct fb_var_screeninfo *v,
|
|
2498 int nom, int den)
|
|
2499 {
|
|
2500 static struct {
|
|
2501 int xres, yres;
|
|
2502 } modes[] = {
|
|
2503 {1600, 1280},
|
|
2504 {1280, 1024},
|
|
2505 {1024, 768},
|
|
2506 {800, 600},
|
|
2507 {640, 480},
|
|
2508 {-1, -1}
|
|
2509 };
|
|
2510 int i;
|
|
2511
|
|
2512 /* use highest possible virtual resolution */
|
|
2513 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
|
|
2514 printk("radeonfb: using max availabe virtual resolution\n");
|
|
2515 for (i=0; modes[i].xres != -1; i++) {
|
|
2516 if (modes[i].xres * nom / den * modes[i].yres <
|
|
2517 rinfo->video_ram / 2)
|
|
2518 break;
|
|
2519 }
|
|
2520 if (modes[i].xres == -1) {
|
|
2521 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
|
|
2522 return -EINVAL;
|
|
2523 }
|
|
2524 v->xres_virtual = modes[i].xres;
|
|
2525 v->yres_virtual = modes[i].yres;
|
|
2526
|
|
2527 printk("radeonfb: virtual resolution set to max of %dx%d\n",
|
|
2528 v->xres_virtual, v->yres_virtual);
|
|
2529 } else if (v->xres_virtual == -1) {
|
|
2530 v->xres_virtual = (rinfo->video_ram * den /
|
|
2531 (nom * v->yres_virtual * 2)) & ~15;
|
|
2532 } else if (v->yres_virtual == -1) {
|
|
2533 v->xres_virtual = (v->xres_virtual + 15) & ~15;
|
|
2534 v->yres_virtual = rinfo->video_ram * den /
|
|
2535 (nom * v->xres_virtual *2);
|
|
2536 } else {
|
|
2537 if (v->xres_virtual * nom / den * v->yres_virtual >
|
|
2538 rinfo->video_ram) {
|
|
2539 return -EINVAL;
|
|
2540 }
|
|
2541 }
|
|
2542
|
|
2543 if (v->xres_virtual * nom / den >= 8192) {
|
|
2544 v->xres_virtual = 8192 * den / nom - 16;
|
|
2545 }
|
|
2546
|
|
2547 if (v->xres_virtual < v->xres)
|
|
2548 return -EINVAL;
|
|
2549
|
|
2550 if (v->yres_virtual < v->yres)
|
|
2551 return -EINVAL;
|
|
2552
|
|
2553 return 0;
|
|
2554 }
|
|
2555
|
1911
|
2556
|
|
2557 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
2558 unsigned long arg, int con, struct fb_info *info)
|
|
2559 {
|
|
2560 return -EINVAL;
|
|
2561 }
|
|
2562
|
|
2563
|
|
2564
|
|
2565 static int radeonfb_switch (int con, struct fb_info *info)
|
|
2566 {
|
|
2567 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2568 struct display *disp;
|
|
2569 struct fb_cmap *cmap;
|
|
2570 int switchcon = 0;
|
1914
|
2571
|
1911
|
2572 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2573
|
|
2574 if (rinfo->currcon >= 0) {
|
|
2575 cmap = &(rinfo->currcon_display->cmap);
|
|
2576 if (cmap->len)
|
|
2577 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
|
|
2578 }
|
|
2579
|
|
2580 if ((disp->var.xres != rinfo->xres) ||
|
|
2581 (disp->var.yres != rinfo->yres) ||
|
|
2582 (disp->var.pixclock != rinfo->pixclock) ||
|
|
2583 (disp->var.bits_per_pixel != rinfo->depth))
|
|
2584 switchcon = 1;
|
|
2585
|
|
2586 if (switchcon) {
|
|
2587 rinfo->currcon = con;
|
|
2588 rinfo->currcon_display = disp;
|
|
2589 disp->var.activate = FB_ACTIVATE_NOW;
|
|
2590
|
|
2591 radeonfb_set_var (&disp->var, con, info);
|
1914
|
2592 radeon_set_dispsw (rinfo, disp);
|
|
2593 do_install_cmap(con, info);
|
1911
|
2594 }
|
|
2595 return 0;
|
|
2596 }
|
|
2597
|
|
2598
|
|
2599
|
|
2600 static int radeonfb_updatevar (int con, struct fb_info *info)
|
|
2601 {
|
|
2602 int rc;
|
|
2603
|
|
2604 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
|
|
2605 con, info);
|
|
2606
|
|
2607 return rc;
|
|
2608 }
|
|
2609
|
|
2610 static void radeonfb_blank (int blank, struct fb_info *info)
|
|
2611 {
|
|
2612 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
2613 u32 val = INREG(CRTC_EXT_CNTL);
|
|
2614
|
|
2615 /* reset it */
|
|
2616 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
|
|
2617 CRTC_VSYNC_DIS);
|
1911
|
2618
|
|
2619 switch (blank) {
|
1914
|
2620 case VESA_NO_BLANKING:
|
2142
|
2621 if(DUAL_MONITOR(rinfo)) {
|
|
2622 OUTREGP(CRTC2_GEN_CNTL,
|
|
2623 0,
|
|
2624 ~(CRTC2_DISP_DIS |
|
|
2625 CRTC2_VSYNC_DIS |
|
|
2626 CRTC2_HSYNC_DIS));
|
|
2627 }
|
|
2628 switch(PRIMARY_MONITOR(rinfo)) {
|
|
2629 case MT_LCD:
|
|
2630 OUTREGP(LVDS_GEN_CNTL, 0,
|
|
2631 ~LVDS_DISPLAY_DIS);
|
|
2632 case MT_CRT:
|
|
2633 case MT_DFP:
|
|
2634 OUTREGP(CRTC_EXT_CNTL,
|
|
2635 CRTC_CRT_ON,
|
|
2636 ~(CRTC_DISPLAY_DIS |
|
|
2637 CRTC_VSYNC_DIS |
|
|
2638 CRTC_HSYNC_DIS));
|
|
2639 break;
|
|
2640 case MT_NONE:
|
|
2641 default:
|
|
2642 break;
|
|
2643
|
|
2644 }
|
1914
|
2645 break;
|
|
2646 case VESA_VSYNC_SUSPEND:
|
|
2647 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
|
1911
|
2648 break;
|
1914
|
2649 case VESA_HSYNC_SUSPEND:
|
|
2650 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
|
1911
|
2651 break;
|
1914
|
2652 case VESA_POWERDOWN:
|
|
2653 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
|
|
2654 CRTC_HSYNC_DIS);
|
1911
|
2655 break;
|
|
2656 }
|
2142
|
2657 if(blank != VESA_NO_BLANKING) OUTREG(CRTC_EXT_CNTL, val);
|
1911
|
2658 }
|
|
2659
|
|
2660
|
|
2661
|
|
2662 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
|
|
2663 {
|
|
2664 int rc = 16; /* reasonable default */
|
|
2665
|
|
2666 switch (var->bits_per_pixel) {
|
|
2667 case 8:
|
|
2668 rc = 256;
|
|
2669 break;
|
|
2670 case 16:
|
|
2671 rc = 64;
|
|
2672 break;
|
|
2673 default:
|
|
2674 rc = 32;
|
|
2675 break;
|
|
2676 }
|
|
2677
|
|
2678 return rc;
|
|
2679 }
|
|
2680
|
|
2681
|
|
2682
|
|
2683 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
2684 unsigned *blue, unsigned *transp,
|
|
2685 struct fb_info *info)
|
|
2686 {
|
|
2687 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2688
|
|
2689 if (regno > 255)
|
|
2690 return 1;
|
|
2691
|
|
2692 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
|
|
2693 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
|
|
2694 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
|
|
2695 *transp = 0;
|
|
2696
|
|
2697 return 0;
|
|
2698 }
|
|
2699
|
|
2700
|
|
2701
|
|
2702 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
2703 unsigned blue, unsigned transp, struct fb_info *info)
|
|
2704 {
|
|
2705 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
2706 u32 pindex;
|
1911
|
2707
|
|
2708 if (regno > 255)
|
|
2709 return 1;
|
|
2710
|
|
2711 red >>= 8;
|
|
2712 green >>= 8;
|
|
2713 blue >>= 8;
|
|
2714 rinfo->palette[regno].red = red;
|
|
2715 rinfo->palette[regno].green = green;
|
|
2716 rinfo->palette[regno].blue = blue;
|
|
2717
|
|
2718 /* init gamma for hicolor */
|
|
2719 if ((rinfo->depth > 8) && (regno == 0)) {
|
|
2720 int i;
|
|
2721
|
|
2722 for (i=0; i<255; i++) {
|
|
2723 OUTREG(PALETTE_INDEX, i);
|
1914
|
2724 OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
|
1911
|
2725 }
|
|
2726 }
|
|
2727
|
|
2728 /* default */
|
|
2729 pindex = regno;
|
1914
|
2730
|
|
2731 /* XXX actually bpp, fixme */
|
|
2732 if (rinfo->depth == 16)
|
|
2733 pindex = regno * 8;
|
|
2734
|
|
2735 if (rinfo->depth == 16) {
|
|
2736 OUTREG(PALETTE_INDEX, pindex/2);
|
|
2737 OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
|
|
2738 (green << 8) | (rinfo->palette[regno/2].blue));
|
|
2739 green = rinfo->palette[regno/2].green;
|
|
2740 }
|
|
2741
|
|
2742 if ((rinfo->depth == 8) || (regno < 32)) {
|
|
2743 OUTREG(PALETTE_INDEX, pindex);
|
|
2744 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
|
|
2745 }
|
|
2746
|
|
2747 #if 0
|
1911
|
2748 col = (red << 16) | (green << 8) | blue;
|
|
2749
|
|
2750 if (rinfo->depth == 16) {
|
|
2751 pindex = regno << 3;
|
|
2752
|
|
2753 if ((rinfo->depth == 16) && (regno >= 32)) {
|
|
2754 pindex -= 252;
|
|
2755
|
|
2756 col = (rinfo->palette[regno >> 1].red << 16) |
|
|
2757 (green << 8) |
|
|
2758 (rinfo->palette[regno >> 1].blue);
|
|
2759 } else {
|
|
2760 col = (red << 16) | (green << 8) | blue;
|
|
2761 }
|
|
2762 }
|
|
2763
|
|
2764 OUTREG8(PALETTE_INDEX, pindex);
|
|
2765 radeon_fifo_wait(32);
|
|
2766 OUTREG(PALETTE_DATA, col);
|
1914
|
2767 #endif
|
1911
|
2768
|
|
2769 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
2770 if (regno < 32) {
|
|
2771 switch (rinfo->depth) {
|
|
2772 #ifdef FBCON_HAS_CFB16
|
|
2773 case 16:
|
1914
|
2774 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
|
1911
|
2775 regno;
|
|
2776 break;
|
|
2777 #endif
|
1914
|
2778 #ifdef FBCON_HAS_CFB24
|
|
2779 case 24:
|
|
2780 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
|
|
2781 break;
|
|
2782 #endif
|
1911
|
2783 #ifdef FBCON_HAS_CFB32
|
|
2784 case 32: {
|
|
2785 u32 i;
|
|
2786
|
|
2787 i = (regno << 8) | regno;
|
|
2788 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
|
|
2789 break;
|
|
2790 }
|
|
2791 #endif
|
|
2792 }
|
|
2793 }
|
|
2794 #endif
|
|
2795 return 0;
|
|
2796 }
|
|
2797
|
2132
|
2798 static void radeon_save_common_regs(struct radeonfb_info *rinfo,
|
|
2799 struct radeon_regs *save)
|
|
2800 {
|
|
2801 RTRACE("radeonfb: radeon_save_common_regs is called\n");
|
|
2802 save->ovr_clr = INREG(OVR_CLR);
|
|
2803 save->ovr_wid_left_right= INREG(OVR_WID_LEFT_RIGHT);
|
|
2804 save->ovr_wid_top_bottom= INREG(OVR_WID_TOP_BOTTOM);
|
|
2805 save->ov0_scale_cntl = INREG(OV0_SCALE_CNTL);
|
|
2806 save->mpp_tb_config = INREG(MPP_TB_CONFIG);
|
|
2807 save->mpp_gp_config = INREG(MPP_GP_CONFIG);
|
|
2808 save->subpic_cntl = INREG(SUBPIC_CNTL);
|
|
2809 save->viph_control = INREG(VIPH_CONTROL);
|
|
2810 save->i2c_cntl_1 = INREG(I2C_CNTL_1);
|
|
2811 save->gen_int_cntl = INREG(GEN_INT_CNTL);
|
|
2812 save->cap0_trig_cntl = INREG(CAP0_TRIG_CNTL);
|
|
2813 save->cap1_trig_cntl = INREG(CAP1_TRIG_CNTL);
|
|
2814 save->bus_cntl = INREG(BUS_CNTL);
|
|
2815 }
|
|
2816
|
|
2817 static void radeon_save_crtc_regs(struct radeonfb_info *rinfo,
|
|
2818 struct radeon_regs *save)
|
|
2819 {
|
|
2820 RTRACE("radeonfb: radeon_save_crtc_regs is called\n");
|
|
2821 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
|
|
2822 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
|
|
2823 save->dac_cntl = INREG(DAC_CNTL);
|
|
2824 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
|
|
2825 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
|
|
2826 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
|
|
2827 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
|
|
2828 save->crtc_offset = INREG(CRTC_OFFSET);
|
|
2829 save->crtc_offset_cntl = INREG(CRTC_OFFSET_CNTL);
|
|
2830 save->crtc_pitch = INREG(CRTC_PITCH);
|
|
2831 }
|
|
2832
|
|
2833 static void radeon_save_crtc2_regs(struct radeonfb_info *rinfo,
|
|
2834 struct radeon_regs *save)
|
|
2835 {
|
|
2836 RTRACE("radeonfb: radeon_save_crtc2_regs is called\n");
|
|
2837 save->dac2_cntl = INREG(DAC_CNTL2);
|
|
2838 save->disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
|
|
2839
|
|
2840 save->crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
|
|
2841 save->crtc2_h_total_disp = INREG(CRTC2_H_TOTAL_DISP);
|
|
2842 save->crtc2_h_sync_strt_wid = INREG(CRTC2_H_SYNC_STRT_WID);
|
|
2843 save->crtc2_v_total_disp = INREG(CRTC2_V_TOTAL_DISP);
|
|
2844 save->crtc2_v_sync_strt_wid = INREG(CRTC2_V_SYNC_STRT_WID);
|
|
2845 save->crtc2_offset = INREG(CRTC2_OFFSET);
|
|
2846 save->crtc2_offset_cntl = INREG(CRTC2_OFFSET_CNTL);
|
|
2847 save->crtc2_pitch = INREG(CRTC2_PITCH);
|
|
2848 }
|
|
2849
|
|
2850 static void radeon_save_fp_regs(struct radeonfb_info *rinfo,
|
|
2851 struct radeon_regs *save)
|
|
2852 {
|
|
2853 RTRACE("radeonfb: radeon_save_fp_regs is called\n");
|
|
2854 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
|
|
2855 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
|
|
2856 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
|
|
2857 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
|
|
2858 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
|
|
2859 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
|
|
2860 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
|
|
2861 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
|
|
2862 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
|
|
2863 save->tmds_crc = INREG(TMDS_CRC);
|
|
2864 }
|
|
2865
|
|
2866 static void radeon_save_pll_regs(struct radeonfb_info *rinfo,
|
|
2867 struct radeon_regs *save)
|
|
2868 {
|
|
2869 RTRACE("radeonfb: radeon_save_pll_regs is called\n");
|
|
2870 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
|
|
2871 save->ppll_div_3 = INPLL(PPLL_DIV_3);
|
|
2872 save->htotal_cntl = INPLL(HTOTAL_CNTL);
|
|
2873 }
|
|
2874
|
|
2875 static void radeon_save_pll2_regs(struct radeonfb_info *rinfo,
|
|
2876 struct radeon_regs *save)
|
|
2877 {
|
|
2878 RTRACE("radeonfb: radeon_save_pll2_regs is called\n");
|
|
2879 save->p2pll_ref_div = INPLL(P2PLL_REF_DIV);
|
|
2880 save->p2pll_div_0 = INPLL(P2PLL_DIV_0);
|
|
2881 save->htotal_cntl2 = INPLL(HTOTAL2_CNTL);
|
|
2882 }
|
|
2883
|
|
2884 static void radeon_save_dda_regs(struct radeonfb_info *rinfo,
|
|
2885 struct radeon_regs *save)
|
|
2886 {
|
|
2887 RTRACE("radeonfb: radeon_save_dda_regs is called\n");
|
|
2888 save->dda_config = INREG(DDA_CONFIG);
|
|
2889 save->dda_on_off = INREG(DDA_ON_OFF);
|
|
2890 }
|
|
2891
|
|
2892 #if 0
|
|
2893 static void radeon_save_palette(struct radeonfb_info *rinfo,
|
1911
|
2894 struct radeon_regs *save)
|
|
2895 {
|
2132
|
2896 int i;
|
|
2897 RTRACE("radeonfb: radeon_save_palette is called\n");
|
|
2898 PAL_SELECT(1);
|
|
2899 INPAL_START(0);
|
|
2900 for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT();
|
|
2901 PAL_SELECT(0);
|
|
2902 INPAL_START(0);
|
|
2903 for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT();
|
|
2904 }
|
|
2905 #endif
|
|
2906
|
|
2907 static void radeon_write_common_regs(struct radeonfb_info *rinfo,
|
|
2908 struct radeon_regs *restore)
|
|
2909 {
|
|
2910 RTRACE("radeonfb: radeon_write_common_regs is called\n");
|
|
2911 OUTREG(OVR_CLR, restore->ovr_clr);
|
|
2912 OUTREG(OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
|
|
2913 OUTREG(OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
|
|
2914 OUTREG(OV0_SCALE_CNTL, restore->ov0_scale_cntl);
|
|
2915 OUTREG(MPP_TB_CONFIG, restore->mpp_tb_config );
|
|
2916 OUTREG(MPP_GP_CONFIG, restore->mpp_gp_config );
|
|
2917 OUTREG(SUBPIC_CNTL, restore->subpic_cntl);
|
|
2918 OUTREG(VIPH_CONTROL, restore->viph_control);
|
|
2919 OUTREG(I2C_CNTL_1, restore->i2c_cntl_1);
|
|
2920 OUTREG(GEN_INT_CNTL, restore->gen_int_cntl);
|
|
2921 OUTREG(CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
|
|
2922 OUTREG(CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
|
|
2923 OUTREG(BUS_CNTL, restore->bus_cntl);
|
|
2924 }
|
|
2925
|
|
2926 static void radeon_write_crtc_regs(struct radeonfb_info *rinfo,
|
|
2927 struct radeon_regs *restore)
|
|
2928 {
|
|
2929 RTRACE("radeonfb: radeon_write_crtc_regs is called\n");
|
|
2930 OUTREG(CRTC_GEN_CNTL, restore->crtc_gen_cntl);
|
|
2931
|
|
2932 OUTREGP(CRTC_EXT_CNTL, restore->crtc_ext_cntl,
|
|
2933 CRTC_VSYNC_DIS |
|
|
2934 CRTC_HSYNC_DIS |
|
|
2935 CRTC_DISPLAY_DIS);
|
|
2936
|
|
2937 OUTREGP(DAC_CNTL, restore->dac_cntl,
|
|
2938 DAC_RANGE_CNTL |
|
|
2939 DAC_BLANKING);
|
|
2940
|
|
2941 OUTREG(CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
|
|
2942 OUTREG(CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
|
|
2943 OUTREG(CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
|
|
2944 OUTREG(CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
|
|
2945 OUTREG(CRTC_OFFSET, restore->crtc_offset);
|
|
2946 OUTREG(CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
|
|
2947 OUTREG(CRTC_PITCH, restore->crtc_pitch);
|
|
2948 }
|
|
2949
|
|
2950 static void radeon_write_crtc2_regs(struct radeonfb_info *rinfo,
|
|
2951 struct radeon_regs *restore)
|
|
2952 {
|
|
2953 RTRACE("radeonfb: radeon_write_crtc2_regs is called\n");
|
|
2954 /* OUTREG(CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);*/
|
|
2955 OUTREGP(CRTC2_GEN_CNTL, restore->crtc2_gen_cntl,
|
|
2956 CRTC2_VSYNC_DIS |
|
|
2957 CRTC2_HSYNC_DIS |
|
|
2958 CRTC2_DISP_DIS);
|
|
2959
|
|
2960 OUTREG(DAC_CNTL2, restore->dac2_cntl);
|
|
2961 OUTREG(DISP_OUTPUT_CNTL, restore->disp_output_cntl);
|
|
2962
|
|
2963 OUTREG(CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
|
|
2964 OUTREG(CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
|
|
2965 OUTREG(CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
|
|
2966 OUTREG(CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
|
|
2967 OUTREG(CRTC2_OFFSET, restore->crtc2_offset);
|
|
2968 OUTREG(CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
|
|
2969 OUTREG(CRTC2_PITCH, restore->crtc2_pitch);
|
|
2970 }
|
|
2971
|
|
2972 static void radeon_write_fp_regs(struct radeonfb_info *rinfo,
|
|
2973 struct radeon_regs *restore)
|
|
2974 {
|
|
2975 int prim_mon;
|
|
2976 u32 tmp;
|
|
2977 RTRACE("radeonfb: radeon_write_fp_regs is called\n");
|
|
2978 OUTREG(FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
|
|
2979 OUTREG(FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
|
|
2980 OUTREG(FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
|
|
2981 OUTREG(FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
|
|
2982 OUTREG(TMDS_CRC, restore->tmds_crc);
|
|
2983 OUTREG(FP_HORZ_STRETCH, restore->fp_horz_stretch);
|
|
2984 OUTREG(FP_VERT_STRETCH, restore->fp_vert_stretch);
|
|
2985 OUTREG(FP_GEN_CNTL, restore->fp_gen_cntl);
|
|
2986 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
2987 if(prim_mon == MT_LCD) {
|
|
2988 tmp = INREG(LVDS_GEN_CNTL);
|
|
2989 if((tmp & (LVDS_ON | LVDS_BLON)) ==
|
|
2990 (restore->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
|
|
2991 OUTREG(LVDS_GEN_CNTL, restore->lvds_gen_cntl);
|
|
2992 }
|
|
2993 }
|
|
2994 else {
|
|
2995 if (restore->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
|
2142
|
2996 udelay(rinfo->PanelPwrDly * 1000);
|
2132
|
2997 OUTREG(LVDS_GEN_CNTL, restore->lvds_gen_cntl);
|
|
2998 }
|
|
2999 else {
|
|
3000 OUTREG(LVDS_GEN_CNTL,
|
|
3001 restore->lvds_gen_cntl | LVDS_BLON);
|
2142
|
3002 udelay(rinfo->PanelPwrDly * 1000);
|
2132
|
3003 OUTREG(LVDS_GEN_CNTL, restore->lvds_gen_cntl);
|
|
3004 }
|
|
3005 }
|
1911
|
3006 }
|
|
3007
|
2132
|
3008 static void radeon_write_pll_regs(struct radeonfb_info *rinfo,
|
|
3009 struct radeon_regs *restore)
|
|
3010 {
|
|
3011 RTRACE("radeonfb: radeon_write_pll_regs is called\n");
|
|
3012 OUTPLLP(0x08, 0x00, ~(0x03));
|
|
3013 while ( (INREG(CLOCK_CNTL_INDEX) & PLL_DIV_SEL) != PLL_DIV_SEL) {
|
|
3014 OUTREGP(CLOCK_CNTL_INDEX, PLL_DIV_SEL, 0xffff);
|
|
3015 }
|
|
3016 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
|
|
3017 while ( (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
|
|
3018 (restore->ppll_ref_div & PPLL_REF_DIV_MASK)) {
|
|
3019 OUTPLLP(PPLL_REF_DIV,
|
|
3020 restore->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
|
3021 }
|
|
3022 while ( (INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
|
|
3023 (restore->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
|
|
3024 OUTPLLP(PPLL_DIV_3,restore->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
|
3025 }
|
|
3026 while ( (INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
|
|
3027 (restore->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
|
|
3028 OUTPLLP(PPLL_DIV_3,restore->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
|
3029 }
|
|
3030 OUTPLL(HTOTAL_CNTL, restore->htotal_cntl);
|
|
3031 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
|
|
3032 OUTPLLP(0x08, 0x03, ~(0x03));
|
|
3033 }
|
|
3034
|
|
3035
|
|
3036 static void radeon_write_pll2_regs(struct radeonfb_info *rinfo,
|
|
3037 struct radeon_regs *restore)
|
|
3038 {
|
|
3039 RTRACE("radeonfb: radeon_write_pll2_regs is called\n");
|
|
3040 OUTPLLP(0x2d, 0x00, ~(0x03));
|
|
3041 while (INREG(CLOCK_CNTL_INDEX) & ~(PLL2_DIV_SEL_MASK)) {
|
|
3042 OUTREGP(CLOCK_CNTL_INDEX, 0, PLL2_DIV_SEL_MASK);
|
|
3043 }
|
|
3044 OUTPLLP(P2PLL_CNTL,P2PLL_RESET,0xffff);
|
|
3045 while ( (INPLL(P2PLL_REF_DIV) & P2PLL_REF_DIV_MASK) !=
|
|
3046 (restore->p2pll_ref_div & P2PLL_REF_DIV_MASK)) {
|
|
3047 OUTPLLP(P2PLL_REF_DIV, restore->p2pll_ref_div, ~P2PLL_REF_DIV_MASK);
|
|
3048 }
|
|
3049 while ( (INPLL(P2PLL_DIV_0) & P2PLL_FB0_DIV_MASK) !=
|
|
3050 (restore->p2pll_div_0 & P2PLL_FB0_DIV_MASK)) {
|
|
3051 OUTPLLP(P2PLL_DIV_0, restore->p2pll_div_0, ~P2PLL_FB0_DIV_MASK);
|
|
3052 }
|
|
3053 while ( (INPLL(P2PLL_DIV_0) & P2PLL_POST0_DIV_MASK) !=
|
|
3054 (restore->p2pll_div_0 & P2PLL_POST0_DIV_MASK)) {
|
|
3055 OUTPLLP(P2PLL_DIV_0,restore->p2pll_div_0, ~P2PLL_POST0_DIV_MASK);
|
|
3056 }
|
|
3057 OUTPLL(HTOTAL2_CNTL, restore->htotal_cntl2);
|
|
3058 OUTPLLP(P2PLL_CNTL, 0, ~(P2PLL_RESET | P2PLL_SLEEP));
|
|
3059 OUTPLLP(0x2d, 0x03, ~(0x03));
|
|
3060 }
|
|
3061
|
|
3062 static void radeon_write_dda_regs(struct radeonfb_info *rinfo,
|
|
3063 struct radeon_regs *restore)
|
|
3064 {
|
|
3065 RTRACE("radeonfb: radeon_write_dda_regs is called\n");
|
|
3066 OUTREG(DDA_CONFIG, restore->dda_config);
|
|
3067 OUTREG(DDA_ON_OFF, restore->dda_on_off);
|
|
3068 }
|
|
3069
|
|
3070 #if 0
|
|
3071 static void radeon_write_palette(struct radeonfb_info *rinfo,
|
|
3072 struct radeon_regs *restore)
|
|
3073 {
|
|
3074 int i;
|
|
3075
|
|
3076 RTRACE("radeonfb: radeon_write_palette is called\n");
|
|
3077 PAL_SELECT(1);
|
|
3078 OUTPAL_START(0);
|
|
3079 for (i = 0; i < 256; i++) {
|
|
3080 RADEONWaitForFifo(32); /* delay */
|
|
3081 OUTPAL_NEXT_CARD32(restore->palette2[i]);
|
|
3082 }
|
|
3083
|
|
3084 PAL_SELECT(0);
|
|
3085 OUTPAL_START(0);
|
|
3086 for (i = 0; i < 256; i++) {
|
|
3087 RADEONWaitForFifo(32); /* delay */
|
|
3088 OUTPAL_NEXT_CARD32(restore->palette[i]);
|
|
3089 }
|
|
3090 }
|
|
3091 #endif
|
|
3092
|
|
3093 static void radeon_save_mode (struct radeonfb_info *rinfo,
|
|
3094 struct radeon_regs *save)
|
|
3095 {
|
|
3096 int prim_mon;
|
|
3097 RTRACE("radeonfb: radeon_save_mode is called\n");
|
|
3098 if(DUAL_MONITOR(rinfo)) {
|
|
3099 radeon_save_crtc2_regs(rinfo,save);
|
|
3100 radeon_save_pll2_regs(rinfo,save);
|
|
3101 }
|
|
3102 radeon_save_common_regs(rinfo,save);
|
|
3103 radeon_save_crtc_regs(rinfo,save);
|
|
3104 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
3105 if(prim_mon == MT_LCD || prim_mon == MT_DFP) radeon_save_fp_regs(rinfo,save);
|
|
3106 radeon_save_pll_regs(rinfo,save);
|
|
3107 radeon_save_dda_regs(rinfo,save);
|
|
3108 /*radeon_save_palette(rinfo,save);*/
|
|
3109 }
|
|
3110
|
|
3111 static void radeon_save_state(struct radeonfb_info *rinfo,
|
|
3112 struct radeon_regs *save)
|
|
3113 {
|
|
3114 RTRACE("radeonfb: radeon_save_state is called\n");
|
|
3115 save->dp_datatype = INREG(DP_DATATYPE);
|
|
3116 save->rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
|
|
3117 save->clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
|
3118 save->amcgpio_en_reg = INREG(AMCGPIO_EN_REG);
|
|
3119 save->amcgpio_mask = INREG(AMCGPIO_MASK);
|
|
3120 radeon_save_mode(rinfo,save);
|
|
3121 }
|
|
3122
|
|
3123 static int radeon_load_video_mode (struct radeonfb_info *rinfo,
|
1911
|
3124 struct fb_var_screeninfo *mode)
|
|
3125 {
|
2134
|
3126
|
1911
|
3127 struct radeon_regs newmode;
|
2132
|
3128
|
|
3129 RTRACE("radeonfb: radeon_load_video_mode is called\n");
|
|
3130 if(!radeon_init_mode(rinfo, &newmode, mode)) return -1;
|
|
3131
|
|
3132 radeonfb_blank(VESA_POWERDOWN,&rinfo->info);
|
|
3133 radeon_write_mode(rinfo, &newmode);
|
|
3134 radeonfb_blank(VESA_NO_BLANKING,&rinfo->info);
|
|
3135 return 0;
|
1911
|
3136 }
|
|
3137
|
|
3138 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
3139 struct radeon_regs *mode)
|
|
3140 {
|
2132
|
3141 /*****
|
|
3142 When changing mode with Dual-head card (VE/M6), care must
|
|
3143 be taken for the special order in setting registers. CRTC2 has
|
|
3144 to be set before changing CRTC_EXT register.
|
|
3145 Otherwise we may get a blank screen.
|
|
3146 *****/
|
2136
|
3147 int prim_mon;
|
2132
|
3148 RTRACE("radeonfb: radeon_write_mode is called\n");
|
|
3149 if(DUAL_MONITOR(rinfo)) {
|
|
3150 radeon_write_crtc2_regs(rinfo,mode);
|
|
3151 radeon_write_pll2_regs(rinfo,mode);
|
|
3152 }
|
|
3153 radeon_write_common_regs(rinfo,mode);
|
|
3154 radeon_write_dda_regs(rinfo,mode);
|
|
3155 radeon_write_crtc_regs(rinfo,mode);
|
2136
|
3156 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
3157 if(prim_mon == MT_DFP || prim_mon == MT_LCD) {
|
2132
|
3158 radeon_write_fp_regs(rinfo,mode);
|
1911
|
3159 }
|
2132
|
3160 radeon_write_pll_regs(rinfo,mode);
|
|
3161 }
|
|
3162
|
|
3163 static void radeon_write_state (struct radeonfb_info *rinfo,
|
|
3164 struct radeon_regs *restore)
|
|
3165 {
|
|
3166 RTRACE("radeonfb: radeon_write_state is called\n");
|
|
3167 radeonfb_blank(VESA_POWERDOWN,&rinfo->info);
|
|
3168 OUTREG(AMCGPIO_MASK, restore->amcgpio_mask);
|
|
3169 OUTREG(AMCGPIO_EN_REG, restore->amcgpio_en_reg);
|
|
3170 OUTREG(CLOCK_CNTL_INDEX,restore->clock_cntl_index);
|
|
3171 OUTREG(RBBM_SOFT_RESET, restore->rbbm_soft_reset);
|
|
3172 OUTREG(DP_DATATYPE, restore->dp_datatype);
|
|
3173 /* M6 card has trouble restoring text mode for its CRT.
|
|
3174 Needs this workaround.*/
|
|
3175 if(rinfo->isM6) OUTREG(DAC_CNTL2, restore->dac2_cntl);
|
|
3176 radeon_write_mode(rinfo,restore);
|
|
3177 radeonfb_blank(VESA_NO_BLANKING,&rinfo->info);
|
1911
|
3178 }
|
|
3179
|
1914
|
3180 #if 0
|
1911
|
3181
|
|
3182 /*
|
|
3183 * text console acceleration
|
|
3184 */
|
|
3185
|
|
3186
|
|
3187 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
|
|
3188 int dsty, int dstx, int height, int width)
|
|
3189 {
|
|
3190 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
3191 u32 dp_cntl = DST_LAST_PEL;
|
|
3192
|
|
3193 srcx *= fontwidth(p);
|
|
3194 srcy *= fontheight(p);
|
|
3195 dstx *= fontwidth(p);
|
|
3196 dsty *= fontheight(p);
|
|
3197 width *= fontwidth(p);
|
|
3198 height *= fontheight(p);
|
|
3199
|
|
3200 if (srcy < dsty) {
|
|
3201 srcy += height - 1;
|
|
3202 dsty += height - 1;
|
|
3203 } else
|
|
3204 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
|
|
3205
|
|
3206 if (srcx < dstx) {
|
|
3207 srcx += width - 1;
|
|
3208 dstx += width - 1;
|
|
3209 } else
|
|
3210 dp_cntl |= DST_X_LEFT_TO_RIGHT;
|
|
3211
|
|
3212 radeon_fifo_wait(6);
|
|
3213 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
3214 GMC_BRUSH_NONE |
|
|
3215 GMC_SRC_DATATYPE_COLOR |
|
|
3216 ROP3_S |
|
|
3217 DP_SRC_SOURCE_MEMORY));
|
|
3218 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
3219 OUTREG(DP_CNTL, dp_cntl);
|
|
3220 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
|
|
3221 OUTREG(DST_Y_X, (dsty << 16) | dstx);
|
|
3222 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
|
|
3223 }
|
|
3224
|
|
3225
|
|
3226
|
|
3227 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|
3228 int srcy, int srcx, int height, int width)
|
|
3229 {
|
|
3230 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
3231 u32 clr;
|
|
3232
|
|
3233 clr = attr_bgcol_ec(p, conp);
|
|
3234 clr |= (clr << 8);
|
|
3235 clr |= (clr << 16);
|
|
3236
|
|
3237 srcx *= fontwidth(p);
|
|
3238 srcy *= fontheight(p);
|
|
3239 width *= fontwidth(p);
|
|
3240 height *= fontheight(p);
|
|
3241
|
|
3242 radeon_fifo_wait(6);
|
|
3243 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
3244 GMC_BRUSH_SOLID_COLOR |
|
|
3245 GMC_SRC_DATATYPE_COLOR |
|
|
3246 ROP3_P));
|
|
3247 OUTREG(DP_BRUSH_FRGD_CLR, clr);
|
|
3248 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
3249 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
|
|
3250 OUTREG(DST_Y_X, (srcy << 16) | srcx);
|
|
3251 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
|
|
3252 }
|
|
3253
|
|
3254
|
|
3255
|
|
3256
|
|
3257 #ifdef FBCON_HAS_CFB8
|
|
3258 static struct display_switch fbcon_radeon8 = {
|
|
3259 setup: fbcon_cfb8_setup,
|
|
3260 bmove: fbcon_radeon_bmove,
|
|
3261 clear: fbcon_cfb8_clear,
|
|
3262 putc: fbcon_cfb8_putc,
|
|
3263 putcs: fbcon_cfb8_putcs,
|
|
3264 revc: fbcon_cfb8_revc,
|
|
3265 clear_margins: fbcon_cfb8_clear_margins,
|
|
3266 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
|
3267 };
|
|
3268 #endif
|
1914
|
3269
|
|
3270 #endif /* 0 */
|