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1 /*
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2 * drivers/video/radeonfb.c
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3 * framebuffer driver for ATI Radeon chipset video boards
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4 *
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5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
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6 *
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7 *
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8 * ChangeLog:
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9 * 2000-08-03 initial version 0.0.1
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10 * 2000-09-10 more bug fixes, public release 0.0.5
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11 * 2001-02-19 mode bug fixes, 0.0.7
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12 * 2001-07-05 fixed scrolling issues, engine initialization,
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13 * and minor mode tweaking, 0.0.9
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14 *
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1912
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15 * 2001-09-07 Radeon VE support
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1913
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16 * 2001-09-10 Radeon VE QZ support by Nick Kurshev <nickols_k@mail.ru>
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17 * (limitations: on dualhead Radeons (VE, M6, M7)
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18 * driver works only on second head (DVI port).
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19 * TVout is not supported too. M6 & M7 chips
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20 * currently are not supported. Driver has a lot
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21 * of other bugs. Probably they can be solved by
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22 * importing XFree86 code, which has ATI's support).,
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23 * 0.0.11
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24 * 2001-09-13 merge Ani Joshi radeonfb-0.1.0:
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25 * console switching fixes, blanking fixes,
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26 * 0.1.0-ve.0
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27 * 2001-09-18 Radeon VE, M6 support (by Nick Kurshev <nickols_k@mail.ru>),
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28 * Fixed bug of rom bios detection on VE (by NK),
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29 * Minor code cleanup (by NK),
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30 * Enable CRT port on VE (by NK),
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31 * Disable SURFACE_CNTL because mplayer doesn't work
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32 * propertly (by NK)
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33 * 0.1.0-ve.1
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34 * 2001-09-25 MTRR support (by NK)
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35 * 0.1.0-ve.2
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36 * Special thanks to ATI DevRel team for their hardware donations.
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37 *
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38 * LIMITATIONS: on dualhead Radeons (VE, M6, M7) driver doesn't work in
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39 * dual monitor configuration. TVout is not supported too.
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40 * Probably these problems can be solved by importing XFree86 code, which
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41 * has ATI's support.
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42 *
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43 * Mini-HOWTO: This driver doesn't accept any options. It only switches your
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44 * video card to graphics mode. Standard way to change video modes and other
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45 * video attributes is using 'fbset' utility.
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46 * Sample:
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47 *
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48 * #!/bin/sh
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49 * fbset -fb /dev/fb0 -xres 640 -yres 480 -depth 32 -vxres 640 -vyres 480 -left 70 -right 50 -upper 70 -lower 70 -laced false -pixclock 39767
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50 *
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51 */
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52
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1966
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53 #define RADEON_VERSION "0.1.0-ve.2"
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54
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55 #include <linux/config.h>
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56 #include <linux/module.h>
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57 #include <linux/kernel.h>
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58 #include <linux/errno.h>
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59 #include <linux/string.h>
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60 #include <linux/mm.h>
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61 #include <linux/tty.h>
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1966
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62 #include <linux/slab.h>
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63 #include <linux/delay.h>
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64 #include <linux/fb.h>
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65 #include <linux/console.h>
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66 #include <linux/selection.h>
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67 #include <linux/ioport.h>
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68 #include <linux/init.h>
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69 #include <linux/pci.h>
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70
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71 #include <asm/io.h>
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72
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73 #include <video/fbcon.h>
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74 #include <video/fbcon-cfb8.h>
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75 #include <video/fbcon-cfb16.h>
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76 #include <video/fbcon-cfb24.h>
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77 #include <video/fbcon-cfb32.h>
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78
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79 #ifdef CONFIG_MTRR
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80 #include <asm/mtrr.h>
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81 #endif
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82
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83 #include "radeon.h"
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84
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85
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86 #define DEBUG 0
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87
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88 #if DEBUG
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89 #define RTRACE printk
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90 #else
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91 #define RTRACE(...) ((void)0)
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92 #endif
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93
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94
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95
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96 enum radeon_chips {
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97 RADEON_QD,
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98 RADEON_QE,
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99 RADEON_QF,
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100 RADEON_QG,
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101 RADEON_QY,
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102 RADEON_QZ,
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103 RADEON_LY,
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104 RADEON_LZ,
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105 RADEON_LW,
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106 R200_QL,
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107 RV200_QW
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108 };
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109
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110 enum radeon_montype
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111 {
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112 MT_NONE,
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113 MT_CRT, /* CRT-(cathode ray tube) analog monitor. (15-pin VGA connector) */
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114 MT_LCD, /* Liquid Crystal Display */
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115 MT_DFP, /* DFP-digital flat panel monitor. (24-pin DVI-I connector) */
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116 MT_CTV, /* Composite TV out (not in VE) */
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117 MT_STV /* S-Video TV out (probably in VE only) */
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118 };
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119
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120 enum radeon_ddctype
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121 {
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122 DDC_NONE_DETECTED,
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123 DDC_MONID,
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124 DDC_DVI,
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125 DDC_VGA,
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126 DDC_CRT2
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127 };
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128
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129 enum radeon_connectortype
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130 {
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131 CONNECTOR_NONE,
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132 CONNECTOR_PROPRIETARY,
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133 CONNECTOR_CRT,
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134 CONNECTOR_DVI_I,
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135 CONNECTOR_DVI_D
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136 };
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137
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138 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
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139 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
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140 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
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141 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
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142 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
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1913
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143 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
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144 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
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145 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
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146 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
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147 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
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148 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_R200_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, R200_QL},
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149 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RV200_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RV200_QW},
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150 { 0, }
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151 };
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152 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
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153
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154
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155 typedef struct {
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156 u16 reg;
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157 u32 val;
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158 } reg_val;
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159
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160
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161 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
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162
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163 typedef struct {
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164 u8 clock_chip_type;
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165 u8 struct_size;
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166 u8 accelerator_entry;
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167 u8 VGA_entry;
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168 u16 VGA_table_offset;
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169 u16 POST_table_offset;
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170 u16 XCLK;
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171 u16 MCLK;
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172 u8 num_PLL_blocks;
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173 u8 size_PLL_blocks;
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174 u16 PCLK_ref_freq;
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175 u16 PCLK_ref_divider;
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176 u32 PCLK_min_freq;
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177 u32 PCLK_max_freq;
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178 u16 MCLK_ref_freq;
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179 u16 MCLK_ref_divider;
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180 u32 MCLK_min_freq;
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181 u32 MCLK_max_freq;
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182 u16 XCLK_ref_freq;
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183 u16 XCLK_ref_divider;
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184 u32 XCLK_min_freq;
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185 u32 XCLK_max_freq;
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186 } __attribute__ ((packed)) PLL_BLOCK;
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187
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188
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189 struct pll_info {
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190 int ppll_max;
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191 int ppll_min;
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192 int xclk;
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193 int ref_div;
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194 int ref_clk;
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195 };
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196
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197
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198 struct ram_info {
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199 int ml;
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200 int mb;
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201 int trcd;
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202 int trp;
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203 int twr;
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204 int cl;
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205 int tr2w;
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206 int loop_latency;
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207 int rloop;
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208 };
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209
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210
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211 struct radeon_regs {
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212 /* Common registers */
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213 u32 ovr_clr;
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214 u32 ovr_wid_left_right;
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215 u32 ovr_wid_top_bottom;
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216 u32 ov0_scale_cntl;
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217 u32 mpp_tb_config;
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218 u32 mpp_gp_config;
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219 u32 subpic_cntl;
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220 u32 viph_control;
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221 u32 i2c_cntl_1;
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222 u32 gen_int_cntl;
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223 u32 cap0_trig_cntl;
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224 u32 cap1_trig_cntl;
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225 u32 bus_cntl;
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226 /* Other registers to save for VT switches */
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227 u32 dp_datatype;
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228 u32 rbbm_soft_reset;
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229 u32 clock_cntl_index;
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230 u32 amcgpio_en_reg;
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231 u32 amcgpio_mask;
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232 /* CRTC registers */
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233 u32 crtc_gen_cntl;
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234 u32 crtc_ext_cntl;
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235 u32 dac_cntl;
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236 u32 crtc_h_total_disp;
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237 u32 crtc_h_sync_strt_wid;
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238 u32 crtc_v_total_disp;
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239 u32 crtc_v_sync_strt_wid;
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240 u32 crtc_offset;
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241 u32 crtc_offset_cntl;
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242 u32 crtc_pitch;
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243 /* CRTC2 registers */
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244 u32 crtc2_gen_cntl;
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245 u32 dac2_cntl;
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246 u32 disp_output_cntl;
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247 u32 crtc2_h_total_disp;
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248 u32 crtc2_h_sync_strt_wid;
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249 u32 crtc2_v_total_disp;
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250 u32 crtc2_v_sync_strt_wid;
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251 u32 crtc2_offset;
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252 u32 crtc2_offset_cntl;
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253 u32 crtc2_pitch;
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254 /* Flat panel registers */
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255 u32 fp_crtc_h_total_disp;
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256 u32 fp_crtc_v_total_disp;
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257 u32 fp_gen_cntl;
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258 u32 fp_h_sync_strt_wid;
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259 u32 fp_horz_stretch;
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260 u32 fp_panel_cntl;
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261 u32 fp_v_sync_strt_wid;
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262 u32 fp_vert_stretch;
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263 u32 lvds_gen_cntl;
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264 u32 lvds_pll_cntl;
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265 u32 tmds_crc;
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266 /* DDA registers */
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267 u32 dda_config;
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268 u32 dda_on_off;
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269
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270 /* Computed values for PLL */
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271 u32 dot_clock_freq;
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272 u32 pll_output_freq;
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273 int feedback_div;
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274 int post_div;
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275 /* PLL registers */
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276 u32 ppll_ref_div;
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277 u32 ppll_div_3;
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278 u32 htotal_cntl;
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279 /* Computed values for PLL2 */
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280 u32 dot_clock_freq_2;
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281 u32 pll_output_freq_2;
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282 int feedback_div_2;
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283 int post_div_2;
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284 /* PLL2 registers */
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285 u32 p2pll_ref_div;
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286 u32 p2pll_div_0;
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287 u32 htotal_cntl2;
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288 /* Pallet */
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289 int palette_valid;
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290 u32 palette[256];
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291 u32 palette2[256];
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292
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293 u32 flags;
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294 u32 pix_clock;
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295 int xres, yres;
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296 int bpp;
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297 #if defined(__BIG_ENDIAN)
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298 u32 surface_cntl;
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299 #endif
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300 };
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301
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302
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303 struct radeonfb_info {
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304 struct fb_info info;
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305
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306 struct radeon_regs state;
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307 struct radeon_regs init_state;
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308
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309 char name[17];
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310 char ram_type[12];
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311
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312 int hasCRTC2;
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313 int crtDispType;
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314 int dviDispType;
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315 int hasTVout;
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316 int isM7;
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317 int isM6;
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318 int isR200;
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319 int theatre_num;
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320 /* Computed values for FPs */
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321 int PanelXRes;
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322 int PanelYRes;
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323 int HOverPlus;
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324 int HSyncWidth;
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325 int HBlank;
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326 int VOverPlus;
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327 int VSyncWidth;
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328 int VBlank;
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329 int PanelPwrDly;
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330
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331 u32 mmio_base_phys;
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332 u32 fb_base_phys;
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333
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334 u32 mmio_base;
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335 u32 fb_base;
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336
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337 u32 MemCntl;
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338 u32 BusCntl;
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339
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340 struct pci_dev *pdev;
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341
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342 struct display disp;
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343 int currcon;
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344 struct display *currcon_display;
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345
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346 struct { u8 red, green, blue, pad; } palette[256];
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347
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348 int chipset;
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349 int video_ram;
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350 u8 rev;
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351 int pitch, bpp, depth;
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352 int xres, yres, pixclock;
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353
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354 u32 dp_gui_master_cntl;
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355
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356 struct pll_info pll;
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357 int pll_output_freq, post_div, fb_div;
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358
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359 struct ram_info ram;
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360
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361 #ifdef CONFIG_MTRR
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362 struct { int vram; int vram_valid; } mtrr;
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363 #endif
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364 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
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365 union {
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366 #if defined(FBCON_HAS_CFB16)
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367 u_int16_t cfb16[16];
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368 #endif
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369 #if defined(FBCON_HAS_CFB24)
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370 u_int32_t cfb24[16];
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371 #endif
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372 #if defined(FBCON_HAS_CFB32)
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373 u_int32_t cfb32[16];
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374 #endif
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375 } con_cmap;
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376 #endif
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377 };
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378
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379 #define SINGLE_MONITOR(rinfo) (rinfo->crtDispType == MT_NONE || rinfo->dviDispType == MT_NONE)
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380 /*#define DUAL_MONITOR(rinfo) (rinfo->crtDispType != MT_NONE && rinfo->dviDispType != MT_NONE)*/
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381 /* Disable DUAL monitor support for now */
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382 #define DUAL_MONITOR(rinfo) (0)
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383 #define PRIMARY_MONITOR(rinfo) (rinfo->dviDispType != MT_NONE && rinfo->dviDispType != MT_STV && rinfo->dviDispType != MT_CTV ? rinfo->dviDispType : rinfo->crtDispType)
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384
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385 static struct fb_var_screeninfo radeonfb_default_var = {
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386 640, 480, 640, 480, 0, 0, 8, 0,
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387 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
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388 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
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389 0, FB_VMODE_NONINTERLACED
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390 };
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391
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392
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393 /*
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394 * IO macros
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395 */
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396
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397 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
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398 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
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399 #define INREG(addr) readl((rinfo->mmio_base)+addr)
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400 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
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401
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402 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
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403 OUTREG(CLOCK_CNTL_DATA, val)
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404 #define OUTPLLP(addr,val,mask) \
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405 do { \
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406 unsigned int _tmp = INPLL(addr); \
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407 _tmp &= (mask); \
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408 _tmp |= (val); \
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409 OUTPLL(addr, _tmp); \
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410 } while (0)
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411
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412 #define OUTREGP(addr,val,mask) \
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413 do { \
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414 unsigned int _tmp = INREG(addr); \
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415 _tmp &= (mask); \
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416 _tmp |= (val); \
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417 OUTREG(addr, _tmp); \
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418 } while (0)
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419
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420
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421 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
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422 {
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423 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
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424 return (INREG(CLOCK_CNTL_DATA));
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425 }
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426
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427 #define INPLL(addr) _INPLL(rinfo, addr)
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428
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429 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
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430 {
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431 switch (post_div) {
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432 case 1:
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433 return 0x00;
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434 case 2:
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435 return 0x01;
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436 case 3:
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437 return 0x04;
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438 case 4:
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439 return 0x02;
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440 case 6:
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441 return 0x06;
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442 case 8:
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443 return 0x03;
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444 case 12:
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445 return 0x07;
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446 default:
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447 return 0x02;
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448 }
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449 }
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450
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451
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452
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453 static __inline__ int round_div(int num, int den)
|
|
454 {
|
|
455 return (num + (den / 2)) / den;
|
|
456 }
|
|
457
|
|
458
|
|
459
|
|
460 static __inline__ int min_bits_req(int val)
|
|
461 {
|
|
462 int bits_req = 0;
|
|
463
|
|
464 if (val == 0)
|
|
465 bits_req = 1;
|
|
466
|
|
467 while (val) {
|
|
468 val >>= 1;
|
|
469 bits_req++;
|
|
470 }
|
|
471
|
|
472 return (bits_req);
|
|
473 }
|
|
474
|
|
475
|
|
476 static __inline__ int _max(int val1, int val2)
|
|
477 {
|
|
478 if (val1 >= val2)
|
|
479 return val1;
|
|
480 else
|
|
481 return val2;
|
|
482 }
|
|
483
|
1911
|
484
|
|
485 /*
|
|
486 * 2D engine routines
|
|
487 */
|
|
488
|
|
489 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
|
|
490 {
|
|
491 int i;
|
|
492
|
|
493 /* initiate flush */
|
|
494 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
|
|
495 ~RB2D_DC_FLUSH_ALL);
|
|
496
|
|
497 for (i=0; i < 2000000; i++) {
|
|
498 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
|
|
499 break;
|
|
500 }
|
|
501 }
|
|
502
|
|
503
|
|
504 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
|
|
505 {
|
|
506 int i;
|
|
507
|
|
508 for (i=0; i<2000000; i++)
|
|
509 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
|
|
510 return;
|
|
511 }
|
|
512
|
|
513
|
|
514 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
|
|
515 {
|
|
516 int i;
|
|
517
|
|
518 /* ensure FIFO is empty before waiting for idle */
|
|
519 _radeon_fifo_wait (rinfo, 64);
|
|
520
|
|
521 for (i=0; i<2000000; i++) {
|
|
522 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
|
|
523 radeon_engine_flush (rinfo);
|
|
524 return;
|
|
525 }
|
|
526 }
|
|
527 }
|
|
528
|
|
529
|
2037
|
530
|
1911
|
531 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
|
|
532 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
|
|
533
|
|
534
|
|
535
|
|
536 /*
|
|
537 * helper routines
|
|
538 */
|
|
539
|
|
540 static __inline__ u32 radeon_get_dstbpp(u16 depth)
|
|
541 {
|
|
542 switch (depth) {
|
|
543 case 8:
|
|
544 return DST_8BPP;
|
|
545 case 15:
|
|
546 return DST_15BPP;
|
|
547 case 16:
|
|
548 return DST_16BPP;
|
1914
|
549 case 24:
|
|
550 return DST_24BPP;
|
1911
|
551 case 32:
|
|
552 return DST_32BPP;
|
|
553 default:
|
|
554 return 0;
|
|
555 }
|
|
556 }
|
|
557
|
|
558
|
|
559 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
|
|
560 {
|
|
561 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
|
|
562
|
|
563 radeon_engine_flush (rinfo);
|
|
564
|
|
565 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
|
566 mclk_cntl = INPLL(MCLK_CNTL);
|
|
567
|
|
568 OUTPLL(MCLK_CNTL, (mclk_cntl |
|
|
569 FORCEON_MCLKA |
|
|
570 FORCEON_MCLKB |
|
|
571 FORCEON_YCLKA |
|
|
572 FORCEON_YCLKB |
|
|
573 FORCEON_MC |
|
|
574 FORCEON_AIC));
|
|
575 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
|
|
576
|
|
577 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
|
|
578 SOFT_RESET_CP |
|
|
579 SOFT_RESET_HI |
|
|
580 SOFT_RESET_SE |
|
|
581 SOFT_RESET_RE |
|
|
582 SOFT_RESET_PP |
|
|
583 SOFT_RESET_E2 |
|
|
584 SOFT_RESET_RB |
|
|
585 SOFT_RESET_HDP);
|
|
586 INREG(RBBM_SOFT_RESET);
|
|
587 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
|
|
588 ~(SOFT_RESET_CP |
|
|
589 SOFT_RESET_HI |
|
|
590 SOFT_RESET_SE |
|
|
591 SOFT_RESET_RE |
|
|
592 SOFT_RESET_PP |
|
|
593 SOFT_RESET_E2 |
|
|
594 SOFT_RESET_RB |
|
|
595 SOFT_RESET_HDP));
|
|
596 INREG(RBBM_SOFT_RESET);
|
|
597
|
|
598 OUTPLL(MCLK_CNTL, mclk_cntl);
|
|
599 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
|
|
600 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
|
|
601
|
|
602 return;
|
|
603 }
|
|
604
|
|
605 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
|
|
606
|
|
607 /*
|
|
608 * globals
|
|
609 */
|
|
610
|
|
611 static char fontname[40] __initdata;
|
|
612 static char *mode_option __initdata;
|
|
613 static char noaccel __initdata = 0;
|
1951
|
614 static int nomtrr __initdata = 0;
|
1911
|
615
|
1914
|
616 #if 0
|
1911
|
617 #ifdef FBCON_HAS_CFB8
|
|
618 static struct display_switch fbcon_radeon8;
|
|
619 #endif
|
1914
|
620 #endif
|
1911
|
621
|
1951
|
622 #ifdef CONFIG_MTRR
|
|
623 static int mtrr = 1;
|
|
624 #endif
|
|
625
|
1911
|
626 /*
|
|
627 * prototypes
|
|
628 */
|
|
629
|
|
630 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
631 struct fb_info *info);
|
|
632 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
633 struct fb_info *info);
|
|
634 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
635 struct fb_info *info);
|
|
636 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
637 struct fb_info *info);
|
|
638 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
639 struct fb_info *info);
|
|
640 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
641 struct fb_info *info);
|
|
642 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
643 unsigned long arg, int con, struct fb_info *info);
|
|
644 static int radeonfb_switch (int con, struct fb_info *info);
|
|
645 static int radeonfb_updatevar (int con, struct fb_info *info);
|
|
646 static void radeonfb_blank (int blank, struct fb_info *info);
|
|
647 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
|
|
648 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
649 unsigned *blue, unsigned *transp,
|
|
650 struct fb_info *info);
|
|
651 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
652 unsigned blue, unsigned transp, struct fb_info *info);
|
1914
|
653 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
|
2132
|
654 static void radeon_save_mode (struct radeonfb_info *rinfo,
|
|
655 struct radeon_regs *save);
|
1911
|
656 static void radeon_save_state (struct radeonfb_info *rinfo,
|
|
657 struct radeon_regs *save);
|
|
658 static void radeon_engine_init (struct radeonfb_info *rinfo);
|
2132
|
659 static int radeon_load_video_mode (struct radeonfb_info *rinfo,
|
1911
|
660 struct fb_var_screeninfo *mode);
|
|
661 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
662 struct radeon_regs *mode);
|
2132
|
663 static void radeon_write_state (struct radeonfb_info *rinfo,
|
|
664 struct radeon_regs *mode);
|
1911
|
665 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
|
|
666 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
|
|
667 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
|
|
668 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
669 const struct pci_device_id *ent);
|
|
670 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
|
|
671 static char *radeon_find_rom(struct radeonfb_info *rinfo);
|
|
672 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
|
1914
|
673 static void do_install_cmap(int con, struct fb_info *info);
|
|
674 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
675 struct fb_var_screeninfo *var,
|
|
676 struct fb_var_screeninfo *v,
|
|
677 int nom, int den);
|
1911
|
678
|
|
679 static struct fb_ops radeon_fb_ops = {
|
|
680 fb_get_fix: radeonfb_get_fix,
|
|
681 fb_get_var: radeonfb_get_var,
|
|
682 fb_set_var: radeonfb_set_var,
|
|
683 fb_get_cmap: radeonfb_get_cmap,
|
|
684 fb_set_cmap: radeonfb_set_cmap,
|
|
685 fb_pan_display: radeonfb_pan_display,
|
|
686 fb_ioctl: radeonfb_ioctl,
|
|
687 };
|
|
688
|
|
689
|
|
690 static struct pci_driver radeonfb_driver = {
|
|
691 name: "radeonfb",
|
|
692 id_table: radeonfb_pci_table,
|
|
693 probe: radeonfb_pci_register,
|
|
694 remove: radeonfb_pci_unregister,
|
|
695 };
|
|
696
|
2037
|
697 static void _radeon_wait_for_idle(struct radeonfb_info *rinfo);
|
|
698 /* Restore the acceleration hardware to its previous state. */
|
|
699 static void _radeon_engine_restore(struct radeonfb_info *rinfo)
|
|
700 {
|
|
701 int pitch64;
|
|
702
|
|
703 radeon_fifo_wait(1);
|
|
704 /* turn of all automatic flushing - we'll do it all */
|
|
705 OUTREG(RB2D_DSTCACHE_MODE, 0);
|
|
706
|
|
707 pitch64 = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6;
|
|
708
|
|
709 radeon_fifo_wait(1);
|
|
710 OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) |
|
|
711 (pitch64 << 22));
|
|
712
|
|
713 radeon_fifo_wait(1);
|
|
714 #if defined(__BIG_ENDIAN)
|
|
715 OUTREGP(DP_DATATYPE,
|
|
716 HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN);
|
|
717 #else
|
|
718 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
719 #endif
|
|
720
|
|
721 radeon_fifo_wait(1);
|
|
722 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX
|
|
723 | DEFAULT_SC_BOTTOM_MAX));
|
|
724 radeon_fifo_wait(1);
|
|
725 OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL)
|
|
726 | GMC_BRUSH_SOLID_COLOR
|
|
727 | GMC_SRC_DATATYPE_COLOR));
|
|
728
|
|
729 radeon_fifo_wait(7);
|
|
730 OUTREG(DST_LINE_START, 0);
|
|
731 OUTREG(DST_LINE_END, 0);
|
|
732 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
733 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
734 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
735 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
736 OUTREG(DP_WRITE_MASK, 0xffffffff);
|
|
737
|
|
738 _radeon_wait_for_idle(rinfo);
|
|
739 }
|
|
740
|
|
741 /* The FIFO has 64 slots. This routines waits until at least `entries' of
|
|
742 these slots are empty. */
|
|
743 #define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
|
|
744 static void _radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int entries)
|
|
745 {
|
|
746 int i;
|
|
747
|
|
748 for (;;) {
|
|
749 for (i = 0; i < RADEON_TIMEOUT; i++) {
|
|
750 if((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) return;
|
|
751 }
|
|
752 radeon_engine_reset();
|
|
753 _radeon_engine_restore(rinfo);
|
|
754 /* it might be that DRI has been compiled in, but corresponding
|
|
755 library was not loaded.. */
|
|
756 }
|
|
757 }
|
|
758 /* Wait for the graphics engine to be completely idle: the FIFO has
|
|
759 drained, the Pixel Cache is flushed, and the engine is idle. This is a
|
|
760 standard "sync" function that will make the hardware "quiescent". */
|
|
761 static void _radeon_wait_for_idle(struct radeonfb_info *rinfo)
|
|
762 {
|
|
763 int i;
|
|
764
|
|
765 _radeon_wait_for_fifo_function(rinfo, 64);
|
|
766
|
|
767 for (;;) {
|
|
768 for (i = 0; i < RADEON_TIMEOUT; i++) {
|
|
769 if (!(INREG(RBBM_STATUS) & RBBM_ACTIVE)) {
|
|
770 radeon_engine_flush(rinfo);
|
|
771 return;
|
|
772 }
|
|
773 }
|
|
774 _radeon_engine_reset(rinfo);
|
|
775 _radeon_engine_restore(rinfo);
|
|
776 }
|
|
777 }
|
|
778
|
|
779
|
|
780 static u32 RADEONVIP_idle(struct radeonfb_info *rinfo)
|
|
781 {
|
|
782 u32 timeout;
|
|
783
|
|
784 _radeon_wait_for_idle(rinfo);
|
|
785 timeout = INREG(VIPH_TIMEOUT_STAT);
|
|
786 if(timeout & VIPH_TIMEOUT_STAT__VIPH_REG_STAT) /* lockup ?? */
|
|
787 {
|
|
788 radeon_fifo_wait(2);
|
|
789 OUTREG(VIPH_TIMEOUT_STAT, (timeout & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REG_AK);
|
|
790 _radeon_wait_for_idle(rinfo);
|
|
791 return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_RESET;
|
|
792 }
|
|
793 _radeon_wait_for_idle(rinfo);
|
|
794 return (INREG(VIPH_CONTROL) & 0x2000) ? VIP_BUSY : VIP_IDLE ;
|
|
795 }
|
|
796
|
1911
|
797
|
|
798 int __init radeonfb_init (void)
|
|
799 {
|
1951
|
800 #ifdef CONFIG_MTRR
|
|
801 if (nomtrr) {
|
|
802 mtrr = 0;
|
|
803 printk("radeonfb: Parameter NOMTRR set\n");
|
|
804 }
|
|
805 #endif
|
|
806 return pci_module_init (&radeonfb_driver);
|
1911
|
807 }
|
|
808
|
|
809
|
|
810 void __exit radeonfb_exit (void)
|
|
811 {
|
|
812 pci_unregister_driver (&radeonfb_driver);
|
|
813 }
|
|
814
|
|
815
|
|
816 int __init radeonfb_setup (char *options)
|
|
817 {
|
|
818 char *this_opt;
|
|
819
|
|
820 if (!options || !*options)
|
|
821 return 0;
|
|
822
|
|
823 for (this_opt = strtok (options, ","); this_opt;
|
|
824 this_opt = strtok (NULL, ",")) {
|
|
825 if (!strncmp (this_opt, "font:", 5)) {
|
|
826 char *p;
|
|
827 int i;
|
|
828
|
|
829 p = this_opt + 5;
|
|
830 for (i=0; i<sizeof (fontname) - 1; i++)
|
|
831 if (!*p || *p == ' ' || *p == ',')
|
|
832 break;
|
|
833 memcpy(fontname, this_opt + 5, i);
|
|
834 } else if (!strncmp(this_opt, "noaccel", 7)) {
|
|
835 noaccel = 1;
|
|
836 }
|
1951
|
837 #ifdef CONFIG_MTRR
|
|
838 else if(!strncmp(this_opt, "nomtrr", 6)) {
|
|
839 mtrr = 0;
|
|
840 }
|
|
841 #endif
|
1911
|
842 else mode_option = this_opt;
|
|
843 }
|
|
844
|
|
845 return 0;
|
|
846 }
|
|
847
|
|
848 #ifdef MODULE
|
|
849 module_init(radeonfb_init);
|
|
850 module_exit(radeonfb_exit);
|
|
851 #endif
|
|
852
|
|
853
|
1915
|
854 MODULE_AUTHOR("Ani Joshi. (Radeon VE extensions by Nick Kurshev)");
|
|
855 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset. Ver: "RADEON_VERSION);
|
1951
|
856 #ifdef CONFIG_MTRR
|
|
857 MODULE_PARM(nomtrr, "i");
|
|
858 MODULE_PARM_DESC(nomtrr, "Don't touch MTRR (touch=0(default))");
|
|
859 #endif
|
1911
|
860
|
2037
|
861 /* address format:
|
|
862 ((device & 0x3)<<14) | (fifo << 12) | (addr)
|
|
863 */
|
|
864
|
|
865 static int RADEONVIP_read(struct radeonfb_info *rinfo, u32 address, u32 count, u8 *buffer)
|
|
866 {
|
|
867 u32 status,tmp;
|
|
868
|
|
869 if((count!=1) && (count!=2) && (count!=4))
|
|
870 {
|
|
871 printk("radeonfb: Attempt to access VIP bus with non-stadard transaction length\n");
|
|
872 return 0;
|
|
873 }
|
|
874
|
|
875 radeon_fifo_wait(2);
|
|
876 OUTREG(VIPH_REG_ADDR, address | 0x2000);
|
|
877 while(VIP_BUSY == (status = RADEONVIP_idle(rinfo)));
|
|
878 if(VIP_IDLE != status) return 0;
|
|
879
|
|
880 /*
|
|
881 disable VIPH_REGR_DIS to enable VIP cycle.
|
|
882 The LSB of VIPH_TIMEOUT_STAT are set to 0
|
|
883 because 1 would have acknowledged various VIP
|
|
884 interrupts unexpectedly
|
|
885 */
|
|
886 radeon_fifo_wait(2);
|
|
887 OUTREG(VIPH_TIMEOUT_STAT, INREG(VIPH_TIMEOUT_STAT) & (0xffffff00 & ~VIPH_TIMEOUT_STAT__VIPH_REGR_DIS) );
|
|
888 /*
|
|
889 the value returned here is garbage. The read merely initiates
|
|
890 a register cycle
|
|
891 */
|
|
892 _radeon_wait_for_idle(rinfo);
|
|
893 INREG(VIPH_REG_DATA);
|
|
894
|
|
895 while(VIP_BUSY == (status = RADEONVIP_idle(rinfo)));
|
|
896 if(VIP_IDLE != status) return 0;
|
|
897 /*
|
|
898 set VIPH_REGR_DIS so that the read won't take too long.
|
|
899 */
|
|
900 _radeon_wait_for_idle(rinfo);
|
|
901 tmp=INREG(VIPH_TIMEOUT_STAT);
|
|
902 OUTREG(VIPH_TIMEOUT_STAT, (tmp & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
|
|
903 _radeon_wait_for_idle(rinfo);
|
|
904 switch(count){
|
|
905 case 1:
|
|
906 *buffer=(u8)(INREG(VIPH_REG_DATA) & 0xff);
|
|
907 break;
|
|
908 case 2:
|
|
909 *(u16 *)buffer=(u16) (INREG(VIPH_REG_DATA) & 0xffff);
|
|
910 break;
|
|
911 case 4:
|
|
912 *(u32 *)buffer=(u32) ( INREG(VIPH_REG_DATA) & 0xffffffff);
|
|
913 break;
|
|
914 }
|
|
915 while(VIP_BUSY == (status = RADEONVIP_idle(rinfo)));
|
|
916 if(VIP_IDLE != status) return 0;
|
|
917 /*
|
|
918 so that reading VIPH_REG_DATA would not trigger unnecessary vip cycles.
|
|
919 */
|
|
920 OUTREG(VIPH_TIMEOUT_STAT, (INREG(VIPH_TIMEOUT_STAT) & 0xffffff00) | VIPH_TIMEOUT_STAT__VIPH_REGR_DIS);
|
|
921 return 1;
|
|
922 }
|
|
923
|
|
924 static int theatre_read(struct radeonfb_info *rinfo,u32 reg, u32 *data)
|
|
925 {
|
|
926 if(rinfo->theatre_num<0) return 0;
|
|
927 return RADEONVIP_read(rinfo, ((rinfo->theatre_num & 0x3)<<14) | reg,4, (u8 *) data);
|
|
928 }
|
|
929
|
1915
|
930 static char * GET_MON_NAME(int type)
|
|
931 {
|
|
932 char *pret;
|
|
933 switch(type)
|
|
934 {
|
|
935 case MT_NONE: pret = "no"; break;
|
|
936 case MT_CRT: pret = "CRT"; break;
|
|
937 case MT_DFP: pret = "DFP"; break;
|
|
938 case MT_LCD: pret = "LCD"; break;
|
|
939 case MT_CTV: pret = "CTV"; break;
|
|
940 case MT_STV: pret = "STV"; break;
|
|
941 default: pret = "Unknown";
|
|
942 }
|
|
943 return pret;
|
|
944 }
|
1911
|
945
|
|
946
|
|
947 static int radeonfb_pci_register (struct pci_dev *pdev,
|
|
948 const struct pci_device_id *ent)
|
|
949 {
|
|
950 struct radeonfb_info *rinfo;
|
|
951 u32 tmp;
|
|
952 int i, j;
|
|
953 char *bios_seg = NULL;
|
|
954
|
|
955 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
|
|
956 if (!rinfo) {
|
|
957 printk ("radeonfb: could not allocate memory\n");
|
|
958 return -ENODEV;
|
|
959 }
|
|
960
|
|
961 memset (rinfo, 0, sizeof (struct radeonfb_info));
|
|
962
|
|
963 /* enable device */
|
|
964 {
|
|
965 int err;
|
|
966
|
|
967 if ((err = pci_enable_device(pdev))) {
|
|
968 printk("radeonfb: cannot enable device\n");
|
|
969 kfree (rinfo);
|
|
970 return -ENODEV;
|
|
971 }
|
|
972 }
|
|
973
|
|
974 /* set base addrs */
|
|
975 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
|
|
976 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
|
|
977
|
|
978 /* request the mem regions */
|
|
979 if (!request_mem_region (rinfo->fb_base_phys,
|
|
980 pci_resource_len(pdev, 0), "radeonfb")) {
|
|
981 printk ("radeonfb: cannot reserve FB region\n");
|
|
982 kfree (rinfo);
|
|
983 return -ENODEV;
|
|
984 }
|
|
985
|
|
986 if (!request_mem_region (rinfo->mmio_base_phys,
|
|
987 pci_resource_len(pdev, 2), "radeonfb")) {
|
|
988 printk ("radeonfb: cannot reserve MMIO region\n");
|
|
989 release_mem_region (rinfo->fb_base_phys,
|
|
990 pci_resource_len(pdev, 0));
|
|
991 kfree (rinfo);
|
|
992 return -ENODEV;
|
|
993 }
|
|
994
|
|
995 /* map the regions */
|
|
996 rinfo->mmio_base = (u32) ioremap (rinfo->mmio_base_phys,
|
|
997 RADEON_REGSIZE);
|
|
998 if (!rinfo->mmio_base) {
|
|
999 printk ("radeonfb: cannot map MMIO\n");
|
|
1000 release_mem_region (rinfo->mmio_base_phys,
|
|
1001 pci_resource_len(pdev, 2));
|
|
1002 release_mem_region (rinfo->fb_base_phys,
|
|
1003 pci_resource_len(pdev, 0));
|
|
1004 kfree (rinfo);
|
|
1005 return -ENODEV;
|
|
1006 }
|
|
1007
|
|
1008 /* chipset */
|
|
1009 switch (pdev->device) {
|
|
1010 case PCI_DEVICE_ID_RADEON_QD:
|
|
1011 strcpy(rinfo->name, "Radeon QD ");
|
|
1012 break;
|
|
1013 case PCI_DEVICE_ID_RADEON_QE:
|
|
1014 strcpy(rinfo->name, "Radeon QE ");
|
|
1015 break;
|
|
1016 case PCI_DEVICE_ID_RADEON_QF:
|
|
1017 strcpy(rinfo->name, "Radeon QF ");
|
|
1018 break;
|
|
1019 case PCI_DEVICE_ID_RADEON_QG:
|
|
1020 strcpy(rinfo->name, "Radeon QG ");
|
|
1021 break;
|
1913
|
1022 case PCI_DEVICE_ID_RADEON_QY:
|
1915
|
1023 rinfo->hasCRTC2 = 1;
|
|
1024 strcpy(rinfo->name, "Radeon VE QY ");
|
1913
|
1025 break;
|
|
1026 case PCI_DEVICE_ID_RADEON_QZ:
|
1915
|
1027 rinfo->hasCRTC2 = 1;
|
|
1028 strcpy(rinfo->name, "Radeon VE QZ ");
|
|
1029 break;
|
|
1030 case PCI_DEVICE_ID_RADEON_LY:
|
|
1031 rinfo->hasCRTC2 = 1;
|
2132
|
1032 rinfo->isM6 = 1;
|
1915
|
1033 strcpy(rinfo->name, "Radeon M6 LY ");
|
|
1034 break;
|
|
1035 case PCI_DEVICE_ID_RADEON_LZ:
|
|
1036 rinfo->hasCRTC2 = 1;
|
2132
|
1037 rinfo->isM6 = 1;
|
1915
|
1038 strcpy(rinfo->name, "Radeon M6 LZ ");
|
|
1039 break;
|
|
1040 case PCI_DEVICE_ID_RADEON_LW:
|
|
1041 /* Note: Only difference between VE,M6 and M7 is initialization CRTC2
|
|
1042 registers in dual monitor configuration!!! */
|
|
1043 rinfo->hasCRTC2 = 1;
|
|
1044 rinfo->isM7 = 1;
|
|
1045 strcpy(rinfo->name, "Radeon M7 LW ");
|
1912
|
1046 break;
|
1967
|
1047 case PCI_DEVICE_ID_R200_QL:
|
|
1048 rinfo->hasCRTC2 = 1;
|
|
1049 rinfo->isR200 = 1;
|
1969
|
1050 strcpy(rinfo->name, "Radeon2 8500 QL ");
|
1967
|
1051 break;
|
|
1052 case PCI_DEVICE_ID_RV200_QW:
|
|
1053 rinfo->hasCRTC2 = 1;
|
|
1054 rinfo->isM7 = 1;
|
|
1055 strcpy(rinfo->name, "Radeon2 7500 QW ");
|
|
1056 break;
|
1911
|
1057 default:
|
1915
|
1058 release_mem_region (rinfo->mmio_base_phys,
|
|
1059 pci_resource_len(pdev, 2));
|
|
1060 release_mem_region (rinfo->fb_base_phys,
|
|
1061 pci_resource_len(pdev, 0));
|
|
1062 kfree (rinfo);
|
1911
|
1063 return -ENODEV;
|
|
1064 }
|
|
1065
|
|
1066 /* framebuffer size */
|
|
1067 tmp = INREG(CONFIG_MEMSIZE);
|
|
1068
|
|
1069 /* mem size is bits [28:0], mask off the rest */
|
|
1070 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
|
|
1071
|
|
1072 /* ram type */
|
2132
|
1073 rinfo->MemCntl = INREG(MEM_SDRAM_MODE_REG);
|
|
1074 switch ((MEM_CFG_TYPE & rinfo->MemCntl) >> 30) {
|
1911
|
1075 case 0:
|
|
1076 /* SDR SGRAM (2:1) */
|
|
1077 strcpy(rinfo->ram_type, "SDR SGRAM");
|
|
1078 rinfo->ram.ml = 4;
|
|
1079 rinfo->ram.mb = 4;
|
|
1080 rinfo->ram.trcd = 1;
|
|
1081 rinfo->ram.trp = 2;
|
|
1082 rinfo->ram.twr = 1;
|
|
1083 rinfo->ram.cl = 2;
|
|
1084 rinfo->ram.loop_latency = 16;
|
|
1085 rinfo->ram.rloop = 16;
|
|
1086
|
|
1087 break;
|
|
1088 case 1:
|
|
1089 /* DDR SGRAM */
|
|
1090 strcpy(rinfo->ram_type, "DDR SGRAM");
|
|
1091 rinfo->ram.ml = 4;
|
|
1092 rinfo->ram.mb = 4;
|
|
1093 rinfo->ram.trcd = 3;
|
|
1094 rinfo->ram.trp = 3;
|
|
1095 rinfo->ram.twr = 2;
|
|
1096 rinfo->ram.cl = 3;
|
|
1097 rinfo->ram.tr2w = 1;
|
|
1098 rinfo->ram.loop_latency = 16;
|
|
1099 rinfo->ram.rloop = 16;
|
|
1100
|
|
1101 break;
|
|
1102 default:
|
|
1103 /* 64-bit SDR SGRAM */
|
|
1104 strcpy(rinfo->ram_type, "SDR SGRAM 64");
|
|
1105 rinfo->ram.ml = 4;
|
|
1106 rinfo->ram.mb = 8;
|
|
1107 rinfo->ram.trcd = 3;
|
|
1108 rinfo->ram.trp = 3;
|
|
1109 rinfo->ram.twr = 1;
|
|
1110 rinfo->ram.cl = 3;
|
|
1111 rinfo->ram.tr2w = 1;
|
|
1112 rinfo->ram.loop_latency = 17;
|
|
1113 rinfo->ram.rloop = 17;
|
|
1114
|
|
1115 break;
|
|
1116 }
|
2132
|
1117 /* Bus type */
|
|
1118 rinfo->BusCntl = INREG(BUS_CNTL);
|
1911
|
1119
|
|
1120 bios_seg = radeon_find_rom(rinfo);
|
|
1121 radeon_get_pllinfo(rinfo, bios_seg);
|
|
1122
|
|
1123 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d\n",
|
|
1124 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
|
|
1125
|
|
1126 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
|
|
1127
|
1915
|
1128 /*****
|
|
1129 VE and M6 have both DVI and CRT ports (for M6 DVI port can be switch to
|
|
1130 DFP port). The DVI port can also be conneted to a CRT with an adapter.
|
|
1131 Here is the definition of ports for this driver---
|
|
1132 (1) If both port are connected, DVI port will be treated as the Primary
|
|
1133 port (uses CRTC1) and CRT port will be treated as the Secondary port
|
|
1134 (uses CRTC2)
|
|
1135 (2) If only one port is connected, it will treated as the Primary port
|
|
1136 (??? uses CRTC1 ???)
|
|
1137 *****/
|
|
1138 if(rinfo->hasCRTC2) {
|
|
1139 /* Using BIOS scratch registers works with for VE/M6,
|
|
1140 no such registers in regular RADEON!!!*/
|
|
1141 tmp = INREG(RADEON_BIOS_4_SCRATCH);
|
|
1142 /*check Primary (DVI/DFP port)*/
|
|
1143 if(tmp & 0x08) rinfo->dviDispType = MT_DFP;
|
|
1144 else if(tmp & 0x04) rinfo->dviDispType = MT_LCD;
|
|
1145 else if(tmp & 0x0200) rinfo->dviDispType = MT_CRT;
|
|
1146 else if(tmp & 0x10) rinfo->dviDispType = MT_CTV;
|
|
1147 else if(tmp & 0x20) rinfo->dviDispType = MT_STV;
|
|
1148 /*check Secondary (CRT port).*/
|
|
1149 if(tmp & 0x02) rinfo->crtDispType = MT_CRT;
|
|
1150 else if(tmp & 0x800) rinfo->crtDispType = MT_DFP;
|
|
1151 else if(tmp & 0x400) rinfo->crtDispType = MT_LCD;
|
|
1152 else if(tmp & 0x1000) rinfo->crtDispType = MT_CTV;
|
|
1153 else if(tmp & 0x2000) rinfo->crtDispType = MT_STV;
|
|
1154 if(rinfo->dviDispType == MT_NONE &&
|
|
1155 rinfo->crtDispType == MT_NONE) {
|
|
1156 printk("radeonfb: No monitor detected!!!\n");
|
|
1157 release_mem_region (rinfo->mmio_base_phys,
|
|
1158 pci_resource_len(pdev, 2));
|
|
1159 release_mem_region (rinfo->fb_base_phys,
|
|
1160 pci_resource_len(pdev, 0));
|
|
1161 kfree (rinfo);
|
|
1162 return -ENODEV;
|
|
1163 }
|
|
1164 }
|
|
1165 else {
|
|
1166 /*Regular Radeon ASIC, only one CRTC, but it could be
|
|
1167 used for DFP with a DVI output, like AIW board*/
|
|
1168 rinfo->dviDispType = MT_NONE;
|
|
1169 tmp = INREG(FP_GEN_CNTL);
|
|
1170 if(tmp & FP_EN_TMDS) rinfo->crtDispType = MT_DFP;
|
|
1171 else rinfo->crtDispType = MT_CRT;
|
|
1172 }
|
|
1173
|
|
1174 if(bios_seg) {
|
|
1175 /*
|
|
1176 FIXME!!! TVout support currently is incomplete
|
|
1177 On Radeon VE TVout is recognized as STV monitor on DVI port.
|
|
1178 */
|
|
1179 char * bios_ptr = bios_seg + 0x48L;
|
|
1180 rinfo->hasTVout = readw(bios_ptr+0x32);
|
|
1181 }
|
|
1182
|
1911
|
1183 rinfo->fb_base = (u32) ioremap (rinfo->fb_base_phys,
|
|
1184 rinfo->video_ram);
|
|
1185 if (!rinfo->fb_base) {
|
|
1186 printk ("radeonfb: cannot map FB\n");
|
|
1187 iounmap ((void*)rinfo->mmio_base);
|
|
1188 release_mem_region (rinfo->mmio_base_phys,
|
|
1189 pci_resource_len(pdev, 2));
|
|
1190 release_mem_region (rinfo->fb_base_phys,
|
|
1191 pci_resource_len(pdev, 0));
|
|
1192 kfree (rinfo);
|
|
1193 return -ENODEV;
|
|
1194 }
|
|
1195
|
|
1196 /* XXX turn off accel for now, blts aren't working right */
|
|
1197 noaccel = 1;
|
|
1198
|
|
1199 /* set all the vital stuff */
|
|
1200 radeon_set_fbinfo (rinfo);
|
|
1201
|
|
1202 /* save current mode regs before we switch into the new one
|
|
1203 * so we can restore this upon __exit
|
|
1204 */
|
|
1205 radeon_save_state (rinfo, &rinfo->init_state);
|
|
1206
|
|
1207 /* init palette */
|
|
1208 for (i=0; i<16; i++) {
|
|
1209 j = color_table[i];
|
|
1210 rinfo->palette[i].red = default_red[j];
|
|
1211 rinfo->palette[i].green = default_grn[j];
|
|
1212 rinfo->palette[i].blue = default_blu[j];
|
|
1213 }
|
|
1214
|
|
1215 pdev->driver_data = rinfo;
|
|
1216
|
|
1217 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
|
|
1218 printk ("radeonfb: could not register framebuffer\n");
|
|
1219 iounmap ((void*)rinfo->fb_base);
|
|
1220 iounmap ((void*)rinfo->mmio_base);
|
|
1221 release_mem_region (rinfo->mmio_base_phys,
|
|
1222 pci_resource_len(pdev, 2));
|
|
1223 release_mem_region (rinfo->fb_base_phys,
|
|
1224 pci_resource_len(pdev, 0));
|
|
1225 kfree (rinfo);
|
|
1226 return -ENODEV;
|
|
1227 }
|
|
1228
|
|
1229 if (!noaccel) {
|
|
1230 /* initialize the engine */
|
|
1231 radeon_engine_init (rinfo);
|
|
1232 }
|
|
1233
|
1915
|
1234 printk ("radeonfb: ATI %s %s %d MB\n",rinfo->name,rinfo->ram_type,
|
1911
|
1235 (rinfo->video_ram/(1024*1024)));
|
1915
|
1236 if(rinfo->hasCRTC2) {
|
|
1237 printk("radeonfb: DVI port has %s monitor connected\n",GET_MON_NAME(rinfo->dviDispType));
|
|
1238 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
1239 }
|
|
1240 else
|
|
1241 printk("radeonfb: CRT port has %s monitor connected\n",GET_MON_NAME(rinfo->crtDispType));
|
|
1242 printk("radeonfb: This card has %sTVout\n",rinfo->hasTVout ? "" : "no ");
|
1951
|
1243 #ifdef CONFIG_MTRR
|
|
1244 if (mtrr) {
|
|
1245 rinfo->mtrr.vram = mtrr_add(rinfo->fb_base_phys,
|
|
1246 rinfo->video_ram, MTRR_TYPE_WRCOMB, 1);
|
|
1247 rinfo->mtrr.vram_valid = 1;
|
|
1248 /* let there be speed */
|
|
1249 printk("radeonfb: MTRR set to ON\n");
|
|
1250 }
|
|
1251 #endif /* CONFIG_MTRR */
|
2037
|
1252 rinfo->theatre_num = -1;
|
|
1253 for(i=0;i<4;i++)
|
|
1254 {
|
|
1255 if(RADEONVIP_read(rinfo, ((i & 0x03)<<14) | VIP_VIP_VENDOR_DEVICE_ID, 4, (u8 *)&tmp) &&
|
|
1256 (tmp==RT_ATI_ID))
|
|
1257 {
|
|
1258 rinfo->theatre_num=i;
|
|
1259 break;
|
|
1260 }
|
|
1261 }
|
|
1262 if(rinfo->theatre_num >= 0) {
|
|
1263 printk("radeonfb: Device %d on VIP bus ids as %x\n",i,tmp);
|
|
1264 theatre_read(rinfo,VIP_VIP_REVISION_ID, &tmp);
|
|
1265 printk("radeonfb: Detected Rage Theatre revision %8.8X\n", tmp);
|
|
1266 }
|
2046
|
1267 else printk("radeonfb: Rage Theatre was not detected\n");
|
2037
|
1268 return 0;
|
1911
|
1269 }
|
|
1270
|
|
1271
|
|
1272
|
|
1273 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
|
|
1274 {
|
|
1275 struct radeonfb_info *rinfo = pdev->driver_data;
|
|
1276
|
|
1277 if (!rinfo)
|
|
1278 return;
|
|
1279
|
|
1280 /* restore original state */
|
2132
|
1281 radeon_write_state (rinfo, &rinfo->init_state);
|
1911
|
1282
|
|
1283 unregister_framebuffer ((struct fb_info *) rinfo);
|
1951
|
1284 #ifdef CONFIG_MTRR
|
|
1285 if (rinfo->mtrr.vram_valid)
|
|
1286 mtrr_del(rinfo->mtrr.vram, rinfo->fb_base_phys,
|
|
1287 rinfo->video_ram);
|
|
1288 #endif /* CONFIG_MTRR */
|
1911
|
1289 iounmap ((void*)rinfo->mmio_base);
|
|
1290 iounmap ((void*)rinfo->fb_base);
|
|
1291
|
|
1292 release_mem_region (rinfo->mmio_base_phys,
|
|
1293 pci_resource_len(pdev, 2));
|
|
1294 release_mem_region (rinfo->fb_base_phys,
|
|
1295 pci_resource_len(pdev, 0));
|
|
1296
|
|
1297 kfree (rinfo);
|
|
1298 }
|
|
1299
|
|
1300
|
|
1301
|
|
1302 static char *radeon_find_rom(struct radeonfb_info *rinfo)
|
|
1303 {
|
1914
|
1304 #if defined(__i386__)
|
1911
|
1305 u32 segstart;
|
|
1306 char *rom_base;
|
|
1307 char *rom;
|
|
1308 int stage;
|
1915
|
1309 int i,j;
|
1911
|
1310 char aty_rom_sig[] = "761295520";
|
1915
|
1311 char *radeon_sig[] = {
|
|
1312 "RG6",
|
|
1313 "RADEON"
|
|
1314 };
|
1911
|
1315
|
|
1316 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
|
|
1317 stage = 1;
|
|
1318
|
|
1319 rom_base = (char *)ioremap(segstart, 0x1000);
|
|
1320
|
|
1321 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
|
|
1322 stage = 2;
|
|
1323
|
|
1324
|
|
1325 if (stage != 2) {
|
|
1326 iounmap(rom_base);
|
|
1327 continue;
|
|
1328 }
|
|
1329
|
|
1330 rom = rom_base;
|
|
1331
|
|
1332 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
|
|
1333 if (aty_rom_sig[0] == *rom)
|
|
1334 if (strncmp(aty_rom_sig, rom,
|
|
1335 strlen(aty_rom_sig)) == 0)
|
|
1336 stage = 3;
|
|
1337 rom++;
|
|
1338 }
|
|
1339 if (stage != 3) {
|
|
1340 iounmap(rom_base);
|
|
1341 continue;
|
|
1342 }
|
|
1343 rom = rom_base;
|
|
1344
|
|
1345 for (i = 0; (i < 512) && (stage != 4); i++) {
|
1915
|
1346 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
|
|
1347 if (radeon_sig[j][0] == *rom)
|
|
1348 if (strncmp(radeon_sig[j], rom,
|
|
1349 strlen(radeon_sig[j])) == 0) {
|
|
1350 stage = 4;
|
|
1351 break;
|
|
1352 }
|
|
1353 }
|
1911
|
1354 rom++;
|
|
1355 }
|
|
1356 if (stage != 4) {
|
|
1357 iounmap(rom_base);
|
|
1358 continue;
|
|
1359 }
|
|
1360
|
|
1361 return rom_base;
|
|
1362 }
|
|
1363 #endif
|
|
1364 return NULL;
|
|
1365 }
|
|
1366
|
|
1367
|
|
1368
|
|
1369 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
|
|
1370 {
|
|
1371 void *bios_header;
|
|
1372 void *header_ptr;
|
|
1373 u16 bios_header_offset, pll_info_offset;
|
|
1374 PLL_BLOCK pll;
|
|
1375
|
|
1376 if (bios_seg) {
|
|
1377 bios_header = bios_seg + 0x48L;
|
|
1378 header_ptr = bios_header;
|
|
1379
|
|
1380 bios_header_offset = readw(header_ptr);
|
|
1381 bios_header = bios_seg + bios_header_offset;
|
|
1382 bios_header += 0x30;
|
|
1383
|
|
1384 header_ptr = bios_header;
|
|
1385 pll_info_offset = readw(header_ptr);
|
|
1386 header_ptr = bios_seg + pll_info_offset;
|
|
1387
|
|
1388 memcpy_fromio(&pll, header_ptr, 50);
|
|
1389
|
|
1390 rinfo->pll.xclk = (u32)pll.XCLK;
|
|
1391 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
|
|
1392 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
|
|
1393 rinfo->pll.ppll_min = pll.PCLK_min_freq;
|
|
1394 rinfo->pll.ppll_max = pll.PCLK_max_freq;
|
|
1395 } else {
|
|
1396 /* no BIOS or BIOS not found, use defaults */
|
|
1397
|
|
1398 rinfo->pll.ppll_max = 35000;
|
|
1399 rinfo->pll.ppll_min = 12000;
|
|
1400 rinfo->pll.xclk = 16600;
|
|
1401 rinfo->pll.ref_div = 67;
|
|
1402 rinfo->pll.ref_clk = 2700;
|
|
1403 }
|
|
1404 }
|
|
1405
|
2132
|
1406 static void radeon_init_common_regs(struct radeonfb_info *rinfo,
|
|
1407 struct radeon_regs *save)
|
|
1408 {
|
|
1409 RTRACE("radeonfb: radeon_init_common_regs is called\n");
|
|
1410 save->ovr_clr = 0;
|
|
1411 save->ovr_wid_left_right= 0;
|
|
1412 save->ovr_wid_top_bottom= 0;
|
|
1413 save->ov0_scale_cntl = 0;
|
|
1414 save->mpp_tb_config = 0;
|
|
1415 save->mpp_gp_config = 0;
|
|
1416 save->subpic_cntl = 0;
|
|
1417 save->viph_control = 0;
|
|
1418 save->i2c_cntl_1 = 0;
|
|
1419 save->rbbm_soft_reset = 0;
|
|
1420 save->cap0_trig_cntl = 0;
|
|
1421 save->cap1_trig_cntl = 0;
|
|
1422 save->bus_cntl = rinfo->BusCntl;
|
|
1423 /*
|
|
1424 * If bursts are enabled, turn on discards
|
|
1425 * Radeon doesn't have write bursts
|
|
1426
|
|
1427 * XXX: Disabled by NK since on Radeon VE it causes
|
|
1428 * mode corruption.
|
|
1429 if (save->bus_cntl & (BUS_READ_BURST))
|
|
1430 save->bus_cntl |= BUS_RD_DISCARD_EN;
|
|
1431 */
|
|
1432 }
|
|
1433 #if 0
|
|
1434 static int radeon_init_crtc_regs(struct radeonfb_info *rinfo,
|
|
1435 struct radeon_regs *save,
|
|
1436 struct fb_var_screeninfo *mode)
|
|
1437 {
|
|
1438 int format;
|
|
1439 int hsync_start;
|
|
1440 int hsync_wid;
|
|
1441 int hsync_fudge;
|
|
1442 int vsync_wid;
|
|
1443 int bytpp;
|
|
1444 int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
|
|
1445 int hsync_fudge_fp[] = { 0x02, 0x02, 0x00, 0x00, 0x05, 0x05 };
|
|
1446 int prim_mon;
|
|
1447 int hTotal, vTotal, hSyncStart, hSyncEnd;
|
|
1448 int vSyncStart, vSyncEnd;
|
|
1449 RTRACE("radeonfb: radeon_init_crtc_regs is called\n");
|
|
1450
|
|
1451 switch (mode->bits_per_pixel) {
|
|
1452 case 8: format = 2; bytpp = 1; break;
|
|
1453 case 16: format = 4; bytpp = 2; break; /* 565 */
|
|
1454 case 24: format = 5; bytpp = 3; break; /* RGB */
|
|
1455 case 32: format = 6; bytpp = 4; break; /* xRGB */
|
|
1456 default:
|
|
1457 printk("radeonfb: Unsupported pixel depth (%d)\n", mode->bits_per_pixel);
|
|
1458 return 0;
|
|
1459 }
|
|
1460 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
1461 if ((prim_mon == MT_DFP) || (prim_mon == MT_LCD))
|
|
1462 hsync_fudge = hsync_fudge_fp[format-1];
|
|
1463 else
|
|
1464 hsync_fudge = hsync_fudge_default[format-1];
|
|
1465
|
|
1466 save->crtc_gen_cntl = (CRTC_EXT_DISP_EN
|
|
1467 | CRTC_EN
|
|
1468 | (format << 8)
|
|
1469 /* | CRTC_DBL_SCAN_EN*/);
|
|
1470
|
|
1471 if((prim_mon == MT_DFP) || (prim_mon == MT_LCD))
|
|
1472 {
|
|
1473 save->crtc_ext_cntl = VGA_ATI_LINEAR |
|
|
1474 XCRT_CNT_EN;
|
|
1475 save->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
|
|
1476 CRTC_INTERLACE_EN);
|
|
1477 }
|
|
1478 else
|
|
1479 save->crtc_ext_cntl = VGA_ATI_LINEAR |
|
|
1480 XCRT_CNT_EN |
|
|
1481 CRTC_CRT_ON;
|
|
1482
|
|
1483 save->dac_cntl = (DAC_MASK_ALL
|
|
1484 | DAC_VGA_ADR_EN
|
|
1485 | DAC_8BIT_EN);
|
|
1486
|
|
1487 rinfo->xres = mode->xres;
|
|
1488 rinfo->yres = mode->yres;
|
|
1489 rinfo->pixclock = mode->pixclock;
|
|
1490
|
|
1491 hSyncStart = mode->xres + mode->right_margin;
|
|
1492 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1493 hTotal = hSyncEnd + mode->left_margin;
|
|
1494
|
|
1495 vSyncStart = mode->yres + mode->lower_margin;
|
|
1496 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1497 vTotal = vSyncEnd + mode->upper_margin;
|
|
1498
|
|
1499 if(((prim_mon == MT_DFP) || (prim_mon == MT_LCD)))
|
|
1500 {
|
|
1501 if(rinfo->PanelXRes < mode->xres)
|
|
1502 rinfo->xres = mode->xres = rinfo->PanelXRes;
|
|
1503 if(rinfo->PanelYRes < mode->yres)
|
|
1504 rinfo->yres = mode->yres = rinfo->PanelYRes;
|
|
1505 hTotal = mode->xres + rinfo->HBlank + mode->left_margin;
|
|
1506 hSyncStart = mode->xres + rinfo->HOverPlus + mode->right_margin;
|
|
1507 hSyncEnd = hSyncStart + rinfo->HSyncWidth + mode->hsync_len;
|
|
1508 vTotal = mode->yres + rinfo->VBlank + mode->upper_margin;
|
|
1509 vSyncStart = mode->yres + rinfo->VOverPlus + mode->lower_margin;
|
|
1510 vSyncEnd = vSyncStart + rinfo->VSyncWidth + mode->vsync_len;
|
|
1511 }
|
|
1512
|
|
1513 save->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff)
|
|
1514 | ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
|
1515
|
|
1516 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1517 if (!hsync_wid) hsync_wid = 1;
|
|
1518 if (hsync_wid > 0x3f) hsync_wid = 0x3f;
|
|
1519 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1520
|
|
1521 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
|
|
1522 | (hsync_wid << 16)
|
|
1523 | ((mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
|
1524 ? 0
|
|
1525 : CRTC_H_SYNC_POL));
|
|
1526
|
|
1527 /* This works for double scan mode. */
|
|
1528 save->crtc_v_total_disp = (((vTotal - 1) & 0xffff)
|
|
1529 | ((mode->yres - 1) << 16));
|
|
1530
|
|
1531 vsync_wid = vSyncEnd - vSyncStart;
|
|
1532 if (!vsync_wid) vsync_wid = 1;
|
|
1533 if (vsync_wid > 0x1f) vsync_wid = 0x1f;
|
|
1534
|
|
1535 save->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff)
|
|
1536 | (vsync_wid << 16)
|
|
1537 | ((mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
|
1538 ? 0
|
|
1539 : CRTC_V_SYNC_POL));
|
|
1540
|
|
1541 save->crtc_offset = 0;
|
|
1542 save->crtc_offset_cntl = 0;
|
|
1543
|
|
1544 save->crtc_pitch = ((mode->xres * bytpp) +
|
|
1545 ((mode->bits_per_pixel) - 1)) /
|
|
1546 (mode->bits_per_pixel);
|
|
1547 save->crtc_pitch |= save->crtc_pitch << 16;
|
|
1548
|
|
1549 save->xres = mode->xres;
|
|
1550 save->yres = mode->yres;
|
|
1551
|
|
1552 RTRACE("radeonfb: radeon_init_crtc_regs returns SUCCESS\n");
|
|
1553 return 1;
|
|
1554 }
|
|
1555 #endif
|
|
1556 static int radeon_init_crtc_regs(struct radeonfb_info *rinfo,
|
|
1557 struct radeon_regs *save,
|
|
1558 struct fb_var_screeninfo *mode)
|
|
1559 {
|
|
1560 int hTotal, vTotal, hSyncStart, hSyncEnd,
|
|
1561 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
|
|
1562 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
|
|
1563 u8 hsync_fudge_fp[] = { 2, 2, 0, 0, 5, 5 };
|
|
1564 u32 sync, h_sync_pol, v_sync_pol;
|
|
1565 int format = 0;
|
|
1566 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
|
|
1567 int prim_mon;
|
|
1568
|
|
1569 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
1570
|
|
1571 rinfo->xres = mode->xres;
|
|
1572 rinfo->yres = mode->yres;
|
|
1573 rinfo->pixclock = mode->pixclock;
|
|
1574
|
|
1575 hSyncStart = mode->xres + mode->right_margin;
|
|
1576 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1577 hTotal = hSyncEnd + mode->left_margin;
|
|
1578
|
|
1579 vSyncStart = mode->yres + mode->lower_margin;
|
|
1580 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1581 vTotal = vSyncEnd + mode->upper_margin;
|
|
1582
|
|
1583 sync = mode->sync;
|
|
1584 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1585 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
|
1586
|
|
1587 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
|
|
1588 hSyncStart, hSyncEnd, hTotal);
|
|
1589 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
|
|
1590 vSyncStart, vSyncEnd, vTotal);
|
|
1591
|
|
1592 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1593 vsync_wid = vSyncEnd - vSyncStart;
|
|
1594 if (hsync_wid == 0)
|
|
1595 hsync_wid = 1;
|
|
1596 else if (hsync_wid > 0x3f) /* max */
|
|
1597 hsync_wid = 0x3f;
|
|
1598 vsync_wid = mode->vsync_len;
|
|
1599 if (vsync_wid == 0)
|
|
1600 vsync_wid = 1;
|
|
1601 else if (vsync_wid > 0x1f) /* max */
|
|
1602 vsync_wid = 0x1f;
|
|
1603
|
|
1604 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
|
|
1605 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
|
|
1606
|
|
1607 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
|
|
1608
|
|
1609 switch (mode->bits_per_pixel) {
|
|
1610 case 8:
|
|
1611 format = DST_8BPP;
|
|
1612 bytpp = 1;
|
|
1613 break;
|
|
1614 case 16:
|
|
1615 format = DST_16BPP;
|
|
1616 bytpp = 2;
|
|
1617 break;
|
|
1618 case 24:
|
|
1619 format = DST_24BPP;
|
|
1620 bytpp = 3;
|
|
1621 break;
|
|
1622 case 32:
|
|
1623 format = DST_32BPP;
|
|
1624 bytpp = 4;
|
|
1625 break;
|
|
1626 }
|
|
1627
|
|
1628 if ((prim_mon == MT_DFP) || (prim_mon == MT_LCD))
|
|
1629 hsync_fudge = hsync_fudge_fp[format-1];
|
|
1630 else
|
|
1631 hsync_fudge = hsync_adj_tab[format-1];
|
|
1632
|
|
1633 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1634 save->crtc_gen_cntl = (CRTC_EXT_DISP_EN
|
|
1635 | CRTC_EN
|
|
1636 | (format << 8)
|
|
1637 /* | CRTC_DBL_SCAN_EN*/);
|
|
1638
|
|
1639 if((prim_mon == MT_DFP) || (prim_mon == MT_LCD))
|
|
1640 {
|
|
1641 save->crtc_ext_cntl = VGA_ATI_LINEAR |
|
|
1642 XCRT_CNT_EN;
|
|
1643 save->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
|
|
1644 CRTC_INTERLACE_EN);
|
|
1645 }
|
|
1646 else
|
|
1647 save->crtc_ext_cntl = VGA_ATI_LINEAR |
|
|
1648 XCRT_CNT_EN |
|
|
1649 CRTC_CRT_ON;
|
|
1650
|
|
1651 save->dac_cntl = (DAC_MASK_ALL
|
|
1652 | DAC_VGA_ADR_EN
|
|
1653 | DAC_8BIT_EN);
|
|
1654
|
|
1655 save->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
|
|
1656 ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
|
1657
|
|
1658 save->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
|
|
1659 (hsync_wid << 16) | (h_sync_pol << 23));
|
|
1660
|
|
1661 save->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
|
|
1662 ((mode->yres - 1) << 16);
|
|
1663
|
|
1664 save->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
|
|
1665 (vsync_wid << 16) | (v_sync_pol << 23));
|
|
1666
|
|
1667 save->crtc_pitch = (mode->xres >> 3);
|
|
1668
|
|
1669 #if defined(__BIG_ENDIAN)
|
|
1670 save->surface_cntl = SURF_TRANSLATION_DIS;
|
|
1671 switch (mode->bits_per_pixel) {
|
|
1672 case 16:
|
|
1673 save->surface_cntl |= NONSURF_AP0_SWP_16BPP;
|
|
1674 break;
|
|
1675 case 24:
|
|
1676 case 32:
|
|
1677 save->surface_cntl |= NONSURF_AP0_SWP_32BPP;
|
|
1678 break;
|
|
1679 }
|
|
1680 #endif
|
|
1681
|
|
1682 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
|
|
1683 & ~(0x3f)) / 64;
|
|
1684
|
|
1685 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
|
|
1686 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
|
|
1687 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
|
|
1688 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
|
|
1689
|
|
1690 save->xres = mode->xres;
|
|
1691 save->yres = mode->yres;
|
|
1692
|
|
1693 save->crtc_offset = 0;
|
|
1694 save->crtc_offset_cntl = 0;
|
|
1695
|
|
1696 rinfo->bpp = mode->bits_per_pixel;
|
|
1697 return 0;
|
|
1698 }
|
|
1699
|
|
1700 static int radeon_init_crtc2_regs(struct radeonfb_info *rinfo,
|
|
1701 struct radeon_regs *save,
|
|
1702 struct fb_var_screeninfo *mode)
|
|
1703 {
|
|
1704 int format;
|
|
1705 int hsync_start;
|
|
1706 int hsync_wid;
|
|
1707 int hsync_fudge;
|
|
1708 int vsync_wid;
|
|
1709 int bytpp;
|
|
1710 int hsync_fudge_default[] = { 0x00, 0x12, 0x09, 0x09, 0x06, 0x05 };
|
|
1711 int hTotal, vTotal, hSyncStart, hSyncEnd;
|
|
1712 int vSyncStart, vSyncEnd;
|
|
1713 RTRACE("radeonfb: radeon_init_crtc2_regs is called\n");
|
|
1714
|
|
1715 switch (mode->bits_per_pixel) {
|
|
1716 case 8: format = 2; bytpp = 1; break;
|
|
1717 case 16: format = 4; bytpp = 2; break; /* 565 */
|
|
1718 case 24: format = 5; bytpp = 3; break; /* RGB */
|
|
1719 case 32: format = 6; bytpp = 4; break; /* xRGB */
|
|
1720 default:
|
|
1721 printk("radeonfb: Unsupported pixel depth (%d)\n", mode->bits_per_pixel);
|
|
1722 return 0;
|
|
1723 }
|
|
1724
|
|
1725 hsync_fudge = hsync_fudge_default[format-1];
|
|
1726
|
|
1727 save->crtc2_gen_cntl = (CRTC2_EN
|
|
1728 | CRTC2_CRT2_ON
|
|
1729 | (format << 8)
|
|
1730 /*| CRTC2_DBL_SCAN_EN*/);
|
|
1731
|
|
1732 if(!rinfo->isM7)
|
|
1733 save->dac2_cntl = rinfo->init_state.dac2_cntl
|
|
1734 /*| DAC2_DAC2_CLK_SEL*/
|
|
1735 | DAC2_DAC_CLK_SEL;
|
|
1736 else
|
|
1737 {
|
|
1738 save->disp_output_cntl =
|
|
1739 ((rinfo->init_state.disp_output_cntl &
|
|
1740 (u32)~DISP_DAC_SOURCE_MASK)
|
|
1741 | DISP_DAC_SOURCE_CRTC2);
|
|
1742 }
|
|
1743
|
|
1744 hSyncStart = mode->xres + mode->right_margin;
|
|
1745 hSyncEnd = hSyncStart + mode->hsync_len;
|
|
1746 hTotal = hSyncEnd + mode->left_margin;
|
|
1747
|
|
1748 vSyncStart = mode->yres + mode->lower_margin;
|
|
1749 vSyncEnd = vSyncStart + mode->vsync_len;
|
|
1750 vTotal = vSyncEnd + mode->upper_margin;
|
|
1751
|
|
1752 save->crtc2_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff)
|
|
1753 | ((((mode->xres / 8) - 1) & 0x1ff) << 16));
|
|
1754
|
|
1755 hsync_wid = (hSyncEnd - hSyncStart) / 8;
|
|
1756 if (!hsync_wid) hsync_wid = 1;
|
|
1757 if (hsync_wid > 0x3f) hsync_wid = 0x3f;
|
|
1758 hsync_start = hSyncStart - 8 + hsync_fudge;
|
|
1759
|
|
1760 save->crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
|
|
1761 | (hsync_wid << 16)
|
|
1762 | ((mode->sync & FB_SYNC_HOR_HIGH_ACT)
|
|
1763 ? 0
|
|
1764 : CRTC_H_SYNC_POL));
|
|
1765
|
|
1766 /* This works for double scan mode. */
|
|
1767 save->crtc2_v_total_disp = (((vTotal - 1) & 0xffff)
|
|
1768 | ((mode->yres - 1) << 16));
|
|
1769
|
|
1770 vsync_wid = vSyncEnd - vSyncStart;
|
|
1771 if (!vsync_wid) vsync_wid = 1;
|
|
1772 if (vsync_wid > 0x1f) vsync_wid = 0x1f;
|
|
1773
|
|
1774 save->crtc2_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff)
|
|
1775 | (vsync_wid << 16)
|
|
1776 | ((mode->sync & FB_SYNC_VERT_HIGH_ACT)
|
|
1777 ? 0
|
|
1778 : CRTC2_V_SYNC_POL));
|
|
1779
|
|
1780 save->crtc2_offset = 0;
|
|
1781 save->crtc2_offset_cntl = 0;
|
|
1782
|
|
1783 save->crtc2_pitch = ((mode->xres * bytpp) +
|
|
1784 ((mode->bits_per_pixel) -1)) /
|
|
1785 (mode->bits_per_pixel);
|
|
1786 save->crtc2_pitch |= save->crtc2_pitch << 16;
|
|
1787
|
|
1788 RTRACE("radeonfb: radeon_init_crtc2_regs returns SUCCESS\n");
|
|
1789 return 1;
|
|
1790 }
|
|
1791
|
|
1792 static void radeon_init_fp_regs(struct radeonfb_info *rinfo,
|
|
1793 struct radeon_regs *save,
|
|
1794 struct fb_var_screeninfo *mode)
|
|
1795 {
|
|
1796 float Hratio, Vratio;
|
|
1797 int prim_mon;
|
|
1798 RTRACE("radeonfb: radeon_init_fp_regs is called\n");
|
|
1799 if(rinfo->PanelXRes == 0 || rinfo->PanelYRes == 0)
|
|
1800 {
|
|
1801 Hratio = 1;
|
|
1802 Vratio = 1;
|
|
1803 }
|
|
1804 else
|
|
1805 {
|
|
1806 if (mode->xres > rinfo->PanelXRes) mode->xres = rinfo->PanelXRes;
|
|
1807 if (mode->yres > rinfo->PanelYRes) mode->yres = rinfo->PanelYRes;
|
|
1808
|
|
1809 Hratio = (float)mode->xres/(float)rinfo->PanelXRes;
|
|
1810 Vratio = (float)mode->yres/(float)rinfo->PanelYRes;
|
|
1811 }
|
|
1812
|
|
1813 if (Hratio == 1.0)
|
|
1814 {
|
|
1815 save->fp_horz_stretch = rinfo->init_state.fp_horz_stretch;
|
|
1816 save->fp_horz_stretch &= ~(HORZ_STRETCH_BLEND |
|
|
1817 HORZ_STRETCH_ENABLE);
|
|
1818 }
|
|
1819 else
|
|
1820 {
|
|
1821 save->fp_horz_stretch =
|
|
1822 ((((unsigned long)(Hratio * HORZ_STRETCH_RATIO_MAX +
|
|
1823 0.5)) & HORZ_STRETCH_RATIO_MASK)) |
|
|
1824 (rinfo->init_state.fp_horz_stretch & (HORZ_PANEL_SIZE |
|
|
1825 HORZ_FP_LOOP_STRETCH |
|
|
1826 HORZ_AUTO_RATIO_INC));
|
|
1827 save->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
|
|
1828 HORZ_STRETCH_ENABLE);
|
|
1829 }
|
|
1830 save->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
|
|
1831
|
|
1832 if (Vratio == 1.0)
|
|
1833 {
|
|
1834 save->fp_vert_stretch = rinfo->init_state.fp_vert_stretch;
|
|
1835 save->fp_vert_stretch &= ~(VERT_STRETCH_ENABLE|
|
|
1836 VERT_STRETCH_BLEND);
|
|
1837 }
|
|
1838 else
|
|
1839 {
|
|
1840 save->fp_vert_stretch =
|
|
1841 (((((unsigned long)(Vratio * VERT_STRETCH_RATIO_MAX +
|
|
1842 0.5)) & VERT_STRETCH_RATIO_MASK)) |
|
|
1843 (rinfo->init_state.fp_vert_stretch & (VERT_PANEL_SIZE |
|
|
1844 VERT_STRETCH_RESERVED)));
|
|
1845 save->fp_vert_stretch |= (VERT_STRETCH_ENABLE |
|
|
1846 VERT_STRETCH_BLEND);
|
|
1847 }
|
|
1848 save->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
|
|
1849
|
|
1850 save->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
|
|
1851 ~(FP_SEL_CRTC2 |
|
|
1852 FP_RMX_HVSYNC_CONTROL_EN |
|
|
1853 FP_DFP_SYNC_SEL |
|
|
1854 FP_CRT_SYNC_SEL |
|
|
1855 FP_CRTC_LOCK_8DOT |
|
|
1856 FP_USE_SHADOW_EN |
|
|
1857 FP_CRTC_USE_SHADOW_VEND |
|
|
1858 FP_CRT_SYNC_ALT));
|
|
1859 save->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
|
|
1860 FP_CRTC_DONT_SHADOW_HEND );
|
|
1861
|
|
1862 save->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
|
|
1863 save->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
|
|
1864 save->tmds_crc = rinfo->init_state.tmds_crc;
|
|
1865
|
|
1866 /* Disable CRT output by disabling CRT output for DFP*/
|
|
1867 save->crtc_ext_cntl &= ~CRTC_CRT_ON;
|
|
1868 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
1869 if(prim_mon == MT_LCD)
|
|
1870 {
|
|
1871 save->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
|
|
1872 save->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
|
|
1873 }
|
|
1874 else if(prim_mon == MT_DFP)
|
|
1875 save->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
|
|
1876
|
|
1877 save->fp_crtc_h_total_disp = rinfo->init_state.fp_crtc_h_total_disp;
|
|
1878 save->fp_crtc_v_total_disp = rinfo->init_state.fp_crtc_v_total_disp;
|
|
1879 save->fp_h_sync_strt_wid = rinfo->init_state.fp_h_sync_strt_wid;
|
|
1880 save->fp_v_sync_strt_wid = rinfo->init_state.fp_v_sync_strt_wid;
|
|
1881 }
|
|
1882
|
|
1883 static void radeon_init_pll_regs(struct radeonfb_info *rinfo,
|
|
1884 struct radeon_regs *save,
|
|
1885 struct fb_var_screeninfo *mode)
|
|
1886 {
|
|
1887 u32 dot_clock = 1000000000 / mode->pixclock;
|
|
1888 u32 freq = dot_clock / 10; /* x 100 */
|
|
1889 struct {
|
|
1890 int divider;
|
|
1891 int bitvalue;
|
|
1892 } *post_div, post_divs[] = {
|
|
1893 { 1, 0 },
|
|
1894 { 2, 1 },
|
|
1895 { 4, 2 },
|
|
1896 { 8, 3 },
|
|
1897 { 3, 4 },
|
|
1898 { 16, 5 },
|
|
1899 { 6, 6 },
|
|
1900 { 12, 7 },
|
|
1901 { 0, 0 },
|
|
1902 };
|
|
1903 if (freq > rinfo->pll.ppll_max) freq = rinfo->pll.ppll_max;
|
|
1904 if (freq*12 < rinfo->pll.ppll_min) freq = rinfo->pll.ppll_min / 12;
|
|
1905
|
|
1906 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
1907 rinfo->pll_output_freq = post_div->divider * freq;
|
|
1908 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
|
|
1909 rinfo->pll_output_freq <= rinfo->pll.ppll_max) break;
|
|
1910 }
|
|
1911
|
|
1912 rinfo->post_div = post_div->divider;
|
|
1913 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
|
|
1914 rinfo->pll.ref_clk);
|
|
1915 save->ppll_ref_div = rinfo->pll.ref_div;
|
|
1916 save->ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
|
|
1917 save->htotal_cntl = 0;
|
|
1918
|
|
1919 RTRACE("post div = 0x%x\n", rinfo->post_div);
|
|
1920 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
|
|
1921 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
|
|
1922 }
|
|
1923
|
|
1924 static void radeon_init_pll2_regs(struct radeonfb_info *rinfo,
|
|
1925 struct radeon_regs *save,
|
|
1926 struct fb_var_screeninfo *mode)
|
|
1927 {
|
|
1928 u32 dot_clock = 1000000000 / mode->pixclock;
|
|
1929 u32 freq = dot_clock * 100;
|
|
1930 struct {
|
|
1931 int divider;
|
|
1932 int bitvalue;
|
|
1933 } *post_div,
|
|
1934 post_divs[] = {
|
|
1935 /* From RAGE 128 VR/RAGE 128 GL Register
|
|
1936 Reference Manual (Technical Reference
|
|
1937 Manual P/N RRG-G04100-C Rev. 0.04), page
|
|
1938 3-17 (PLL_DIV_[3:0]). */
|
|
1939 { 1, 0 }, /* VCLK_SRC */
|
|
1940 { 2, 1 }, /* VCLK_SRC/2 */
|
|
1941 { 4, 2 }, /* VCLK_SRC/4 */
|
|
1942 { 8, 3 }, /* VCLK_SRC/8 */
|
|
1943 { 3, 4 }, /* VCLK_SRC/3 */
|
|
1944 { 16, 5 }, /* VCLK_SRC/16 */
|
|
1945 { 6, 6 }, /* VCLK_SRC/6 */
|
|
1946 { 12, 7 }, /* VCLK_SRC/12 */
|
|
1947 { 0, 0 }
|
|
1948 };
|
|
1949 RTRACE("radeonfb: radeon_init_pll2_regs is called\n");
|
|
1950
|
|
1951 if (freq > rinfo->pll.ppll_max) freq = rinfo->pll.ppll_max;
|
|
1952 if (freq*12 < rinfo->pll.ppll_min) freq = rinfo->pll.ppll_min/12;
|
|
1953
|
|
1954 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
|
|
1955 save->pll_output_freq_2 = post_div->divider * freq;
|
|
1956 if (save->pll_output_freq_2 >= rinfo->pll.ppll_min
|
|
1957 && save->pll_output_freq_2 <= rinfo->pll.ppll_max) break;
|
|
1958 }
|
|
1959
|
|
1960 save->dot_clock_freq_2 = freq;
|
|
1961 save->feedback_div_2 = round_div(rinfo->pll.ref_div
|
|
1962 * save->pll_output_freq_2,
|
|
1963 rinfo->pll.ref_clk);
|
|
1964 save->post_div_2 = post_div->divider;
|
|
1965
|
|
1966 save->p2pll_ref_div = rinfo->pll.ref_div;
|
|
1967 save->p2pll_div_0 = (save->feedback_div_2 | (post_div->bitvalue<<16));
|
|
1968 save->htotal_cntl2 = 0;
|
|
1969 }
|
|
1970
|
|
1971 static int radeon_init_dda_regs(struct radeonfb_info *rinfo,
|
|
1972 struct radeon_regs *save,
|
|
1973 struct fb_var_screeninfo *mode)
|
|
1974 {
|
|
1975 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
|
|
1976 int useable_precision, roff, ron;
|
|
1977 int min_bits;
|
|
1978 const int DispFifoWidth=128,DispFifoDepth=32;
|
|
1979 /* DDA */
|
|
1980 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
|
|
1981 rinfo->pll.ref_div * rinfo->post_div);
|
|
1982 xclk_freq = rinfo->pll.xclk;
|
|
1983
|
|
1984 xclk_per_trans = round_div(xclk_freq * DispFifoWidth,
|
|
1985 vclk_freq * mode->bits_per_pixel);
|
|
1986
|
|
1987 min_bits = min_bits_req(xclk_per_trans);
|
|
1988 useable_precision = min_bits + 1;
|
|
1989
|
|
1990 xclk_per_trans_precise = round_div((xclk_freq * DispFifoWidth)
|
|
1991 << (11 - useable_precision),
|
|
1992 vclk_freq * mode->bits_per_pixel);
|
|
1993
|
|
1994 ron = (4 * rinfo->ram.mb +
|
|
1995 3 * _max(rinfo->ram.trcd - 2, 0) +
|
|
1996 2 * rinfo->ram.trp +
|
|
1997 rinfo->ram.twr +
|
|
1998 rinfo->ram.cl +
|
|
1999 rinfo->ram.tr2w +
|
|
2000 xclk_per_trans) << (11 - useable_precision);
|
|
2001 roff = xclk_per_trans_precise * (DispFifoDepth - 4);
|
|
2002
|
|
2003 RTRACE("ron = %d, roff = %d\n", ron, roff);
|
|
2004 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
|
|
2005
|
|
2006 if ((ron + rinfo->ram.rloop) >= roff) {
|
|
2007 printk("radeonfb: error ron out of range\n");
|
|
2008 return -1;
|
|
2009 }
|
|
2010
|
|
2011 save->dda_config = (xclk_per_trans_precise |
|
|
2012 (useable_precision << 16) |
|
|
2013 (rinfo->ram.rloop << 20));
|
|
2014 save->dda_on_off = (ron << 16) | roff;
|
|
2015 return 0;
|
|
2016 }
|
|
2017
|
|
2018 /*
|
|
2019 static void radeon_init_palette(struct radeon_regs *save)
|
|
2020 {
|
|
2021 save->palette_valid = 0;
|
|
2022 }
|
|
2023 */
|
|
2024
|
|
2025 static int radeon_init_mode(struct radeonfb_info *rinfo,
|
|
2026 struct radeon_regs *save,
|
|
2027 struct fb_var_screeninfo *mode)
|
|
2028 {
|
|
2029 int prim_mon;
|
|
2030 RTRACE("radeonfb: radeon_init_mode is called\n");
|
|
2031 if(DUAL_MONITOR(rinfo))
|
|
2032 {
|
|
2033 if (!radeon_init_crtc2_regs(rinfo, save, mode))
|
|
2034 return 0;
|
|
2035 radeon_init_pll2_regs(rinfo, save, mode);
|
|
2036 }
|
|
2037 radeon_init_common_regs(rinfo, save);
|
|
2038 if(!radeon_init_crtc_regs(rinfo, save, mode))
|
|
2039 return 0;
|
|
2040 if(mode->pixclock)
|
|
2041 {
|
|
2042 radeon_init_pll_regs(rinfo, save, mode);
|
|
2043 if (!radeon_init_dda_regs(rinfo, save, mode))
|
|
2044 return 0;
|
|
2045 }
|
|
2046 else
|
|
2047 {
|
|
2048 save->ppll_ref_div = rinfo->init_state.ppll_ref_div;
|
|
2049 save->ppll_div_3 = rinfo->init_state.ppll_div_3;
|
|
2050 save->htotal_cntl = rinfo->init_state.htotal_cntl;
|
|
2051 save->dda_config = rinfo->init_state.dda_config;
|
|
2052 save->dda_on_off = rinfo->init_state.dda_on_off;
|
|
2053 }
|
|
2054 /* radeon_init_palete here */
|
|
2055 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
2056 if (((prim_mon == MT_DFP) || (prim_mon == MT_LCD)))
|
|
2057 {
|
|
2058 radeon_init_fp_regs(rinfo, save, mode);
|
|
2059 }
|
|
2060
|
|
2061 RTRACE("radeonfb: radeon_init_mode returns SUCCESS\n");
|
|
2062 return 1;
|
|
2063 }
|
|
2064
|
1911
|
2065 static void radeon_engine_init (struct radeonfb_info *rinfo)
|
|
2066 {
|
|
2067 u32 temp;
|
|
2068
|
|
2069 /* disable 3D engine */
|
|
2070 OUTREG(RB3D_CNTL, 0);
|
|
2071
|
|
2072 radeon_engine_reset ();
|
|
2073
|
|
2074 radeon_fifo_wait (1);
|
|
2075 OUTREG(DSTCACHE_MODE, 0);
|
|
2076
|
|
2077 /* XXX */
|
|
2078 rinfo->pitch = ((rinfo->xres * (rinfo->depth / 8) + 0x3f)) >> 6;
|
|
2079
|
|
2080 radeon_fifo_wait (1);
|
|
2081 temp = INREG(DEFAULT_PITCH_OFFSET);
|
|
2082 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
|
|
2083 (rinfo->pitch << 0x16)));
|
|
2084
|
|
2085 radeon_fifo_wait (1);
|
|
2086 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
|
|
2087
|
|
2088 radeon_fifo_wait (1);
|
|
2089 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
|
|
2090 DEFAULT_SC_BOTTOM_MAX));
|
|
2091
|
|
2092 temp = radeon_get_dstbpp(rinfo->depth);
|
|
2093 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
|
|
2094 radeon_fifo_wait (1);
|
|
2095 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
2096 GMC_BRUSH_SOLID_COLOR |
|
|
2097 GMC_SRC_DATATYPE_COLOR));
|
|
2098
|
|
2099 radeon_fifo_wait (7);
|
|
2100
|
|
2101 /* clear line drawing regs */
|
|
2102 OUTREG(DST_LINE_START, 0);
|
|
2103 OUTREG(DST_LINE_END, 0);
|
|
2104
|
|
2105 /* set brush color regs */
|
|
2106 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
|
|
2107 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
|
|
2108
|
|
2109 /* set source color regs */
|
|
2110 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
|
|
2111 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
|
|
2112
|
|
2113 /* default write mask */
|
|
2114 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
2115
|
|
2116 radeon_engine_idle ();
|
|
2117 }
|
|
2118
|
|
2119
|
|
2120
|
|
2121 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
|
|
2122 {
|
|
2123 struct fb_info *info;
|
|
2124
|
|
2125 info = &rinfo->info;
|
|
2126
|
|
2127 strcpy (info->modename, rinfo->name);
|
|
2128 info->node = -1;
|
|
2129 info->flags = FBINFO_FLAG_DEFAULT;
|
|
2130 info->fbops = &radeon_fb_ops;
|
|
2131 info->display_fg = NULL;
|
|
2132 strncpy (info->fontname, fontname, sizeof (info->fontname));
|
|
2133 info->fontname[sizeof (info->fontname) - 1] = 0;
|
|
2134 info->changevar = NULL;
|
|
2135 info->switch_con = radeonfb_switch;
|
|
2136 info->updatevar = radeonfb_updatevar;
|
|
2137 info->blank = radeonfb_blank;
|
|
2138
|
|
2139 if (radeon_init_disp (rinfo) < 0)
|
|
2140 return -1;
|
|
2141
|
|
2142 return 0;
|
|
2143 }
|
|
2144
|
|
2145
|
|
2146
|
|
2147 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
|
|
2148 {
|
|
2149 struct fb_info *info;
|
|
2150 struct display *disp;
|
|
2151
|
|
2152 info = &rinfo->info;
|
|
2153 disp = &rinfo->disp;
|
|
2154
|
|
2155 disp->var = radeonfb_default_var;
|
|
2156 info->disp = disp;
|
|
2157
|
1914
|
2158 radeon_set_dispsw (rinfo, disp);
|
1911
|
2159
|
|
2160 if (noaccel)
|
|
2161 disp->scrollmode = SCROLL_YREDRAW;
|
|
2162 else
|
|
2163 disp->scrollmode = 0;
|
|
2164
|
|
2165 rinfo->currcon_display = disp;
|
|
2166
|
|
2167 if ((radeon_init_disp_var (rinfo)) < 0)
|
|
2168 return -1;
|
|
2169
|
|
2170 return 0;
|
|
2171 }
|
|
2172
|
|
2173
|
|
2174
|
|
2175 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
|
|
2176 {
|
|
2177 #ifndef MODULE
|
|
2178 if (mode_option)
|
|
2179 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
|
|
2180 NULL, 0, NULL, 8);
|
|
2181 else
|
|
2182 #endif
|
|
2183 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
|
|
2184 NULL, 0, NULL, 0);
|
|
2185
|
|
2186 if (noaccel)
|
|
2187 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
|
|
2188 else
|
|
2189 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
|
|
2190
|
|
2191 return 0;
|
|
2192 }
|
|
2193
|
|
2194
|
1914
|
2195 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
|
1911
|
2196 {
|
|
2197 int accel;
|
|
2198
|
|
2199 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
|
|
2200
|
|
2201 disp->dispsw_data = NULL;
|
|
2202
|
|
2203 disp->screen_base = (char*)rinfo->fb_base;
|
|
2204 disp->type = FB_TYPE_PACKED_PIXELS;
|
|
2205 disp->type_aux = 0;
|
|
2206 disp->ypanstep = 1;
|
|
2207 disp->ywrapstep = 0;
|
|
2208 disp->can_soft_blank = 1;
|
|
2209 disp->inverse = 0;
|
|
2210
|
|
2211 rinfo->depth = disp->var.bits_per_pixel;
|
|
2212 switch (disp->var.bits_per_pixel) {
|
|
2213 #ifdef FBCON_HAS_CFB8
|
|
2214 case 8:
|
1914
|
2215 disp->dispsw = &fbcon_cfb8;
|
1911
|
2216 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
2217 disp->line_length = disp->var.xres_virtual;
|
|
2218 break;
|
|
2219 #endif
|
|
2220 #ifdef FBCON_HAS_CFB16
|
|
2221 case 16:
|
|
2222 disp->dispsw = &fbcon_cfb16;
|
|
2223 disp->dispsw_data = &rinfo->con_cmap.cfb16;
|
|
2224 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2225 disp->line_length = disp->var.xres_virtual * 2;
|
|
2226 break;
|
|
2227 #endif
|
|
2228 #ifdef FBCON_HAS_CFB32
|
1914
|
2229 case 24:
|
|
2230 disp->dispsw = &fbcon_cfb24;
|
|
2231 disp->dispsw_data = &rinfo->con_cmap.cfb24;
|
|
2232 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2233 disp->line_length = disp->var.xres_virtual * 4;
|
|
2234 break;
|
|
2235 #endif
|
|
2236 #ifdef FBCON_HAS_CFB32
|
1911
|
2237 case 32:
|
|
2238 disp->dispsw = &fbcon_cfb32;
|
|
2239 disp->dispsw_data = &rinfo->con_cmap.cfb32;
|
|
2240 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2241 disp->line_length = disp->var.xres_virtual * 4;
|
|
2242 break;
|
|
2243 #endif
|
|
2244 default:
|
|
2245 printk ("radeonfb: setting fbcon_dummy renderer\n");
|
|
2246 disp->dispsw = &fbcon_dummy;
|
|
2247 }
|
|
2248
|
|
2249 return;
|
|
2250 }
|
|
2251
|
|
2252
|
|
2253
|
|
2254 /*
|
|
2255 * fb ops
|
|
2256 */
|
|
2257
|
|
2258 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
|
|
2259 struct fb_info *info)
|
|
2260 {
|
|
2261 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2262 struct display *disp;
|
|
2263
|
|
2264 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2265
|
|
2266 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
|
|
2267 strcpy (fix->id, rinfo->name);
|
|
2268
|
|
2269 fix->smem_start = rinfo->fb_base_phys;
|
|
2270 fix->smem_len = rinfo->video_ram;
|
|
2271
|
|
2272 fix->type = disp->type;
|
|
2273 fix->type_aux = disp->type_aux;
|
|
2274 fix->visual = disp->visual;
|
|
2275
|
|
2276 fix->xpanstep = 1;
|
|
2277 fix->ypanstep = 1;
|
|
2278 fix->ywrapstep = 0;
|
|
2279
|
|
2280 fix->line_length = disp->line_length;
|
|
2281
|
|
2282 fix->mmio_start = rinfo->mmio_base_phys;
|
|
2283 fix->mmio_len = RADEON_REGSIZE;
|
|
2284 if (noaccel)
|
|
2285 fix->accel = FB_ACCEL_NONE;
|
|
2286 else
|
|
2287 fix->accel = 40; /* XXX */
|
|
2288
|
|
2289 return 0;
|
|
2290 }
|
|
2291
|
|
2292
|
|
2293
|
|
2294 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
|
|
2295 struct fb_info *info)
|
|
2296 {
|
|
2297 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2298
|
|
2299 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
|
|
2300
|
|
2301 return 0;
|
|
2302 }
|
|
2303
|
|
2304
|
|
2305
|
|
2306 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
|
|
2307 struct fb_info *info)
|
|
2308 {
|
|
2309 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2310 struct display *disp;
|
|
2311 struct fb_var_screeninfo v;
|
2132
|
2312 int nom, den, accel, err;
|
1911
|
2313 unsigned chgvar = 0;
|
|
2314
|
|
2315 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2316
|
|
2317 accel = var->accel_flags & FB_ACCELF_TEXT;
|
|
2318
|
|
2319 if (con >= 0) {
|
|
2320 chgvar = ((disp->var.xres != var->xres) ||
|
|
2321 (disp->var.yres != var->yres) ||
|
|
2322 (disp->var.xres_virtual != var->xres_virtual) ||
|
|
2323 (disp->var.yres_virtual != var->yres_virtual) ||
|
1914
|
2324 (disp->var.bits_per_pixel != var->bits_per_pixel) ||
|
1911
|
2325 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
|
|
2326 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
|
|
2327 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
|
|
2328 }
|
|
2329
|
|
2330 memcpy (&v, var, sizeof (v));
|
|
2331
|
|
2332 switch (v.bits_per_pixel) {
|
|
2333 #ifdef FBCON_HAS_CFB8
|
|
2334 case 8:
|
|
2335 nom = den = 1;
|
|
2336 disp->line_length = v.xres_virtual;
|
|
2337 disp->visual = FB_VISUAL_PSEUDOCOLOR;
|
|
2338 v.red.offset = v.green.offset = v.blue.offset = 0;
|
|
2339 v.red.length = v.green.length = v.blue.length = 8;
|
1914
|
2340 v.transp.offset = v.transp.length = 0;
|
1911
|
2341 break;
|
|
2342 #endif
|
|
2343
|
|
2344 #ifdef FBCON_HAS_CFB16
|
|
2345 case 16:
|
|
2346 nom = 2;
|
|
2347 den = 1;
|
|
2348 disp->line_length = v.xres_virtual * 2;
|
|
2349 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2350 v.red.offset = 11;
|
|
2351 v.green.offset = 5;
|
|
2352 v.blue.offset = 0;
|
|
2353 v.red.length = 5;
|
|
2354 v.green.length = 6;
|
|
2355 v.blue.length = 5;
|
1914
|
2356 v.transp.offset = v.transp.length = 0;
|
1911
|
2357 break;
|
|
2358 #endif
|
|
2359
|
1914
|
2360 #ifdef FBCON_HAS_CFB24
|
|
2361 case 24:
|
|
2362 nom = 4;
|
|
2363 den = 1;
|
|
2364 disp->line_length = v.xres_virtual * 3;
|
|
2365 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2366 v.red.offset = 16;
|
|
2367 v.green.offset = 8;
|
|
2368 v.blue.offset = 0;
|
|
2369 v.red.length = v.blue.length = v.green.length = 8;
|
|
2370 v.transp.offset = v.transp.length = 0;
|
|
2371 break;
|
|
2372 #endif
|
1911
|
2373 #ifdef FBCON_HAS_CFB32
|
|
2374 case 32:
|
|
2375 nom = 4;
|
|
2376 den = 1;
|
|
2377 disp->line_length = v.xres_virtual * 4;
|
|
2378 disp->visual = FB_VISUAL_DIRECTCOLOR;
|
|
2379 v.red.offset = 16;
|
|
2380 v.green.offset = 8;
|
|
2381 v.blue.offset = 0;
|
|
2382 v.red.length = v.blue.length = v.green.length = 8;
|
1914
|
2383 v.transp.offset = 24;
|
|
2384 v.transp.length = 8;
|
1911
|
2385 break;
|
|
2386 #endif
|
|
2387 default:
|
|
2388 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
|
|
2389 var->xres, var->yres, var->bits_per_pixel);
|
|
2390 return -EINVAL;
|
|
2391 }
|
|
2392
|
1914
|
2393 if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
|
|
2394 return -EINVAL;
|
1911
|
2395
|
|
2396 if (v.xoffset < 0)
|
|
2397 v.xoffset = 0;
|
|
2398 if (v.yoffset < 0)
|
|
2399 v.yoffset = 0;
|
|
2400
|
|
2401 if (v.xoffset > v.xres_virtual - v.xres)
|
|
2402 v.xoffset = v.xres_virtual - v.xres - 1;
|
|
2403
|
|
2404 if (v.yoffset > v.yres_virtual - v.yres)
|
|
2405 v.yoffset = v.yres_virtual - v.yres - 1;
|
|
2406
|
|
2407 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
|
|
2408 v.transp.offset = v.transp.length =
|
|
2409 v.transp.msb_right = 0;
|
|
2410
|
|
2411 switch (v.activate & FB_ACTIVATE_MASK) {
|
|
2412 case FB_ACTIVATE_TEST:
|
|
2413 return 0;
|
|
2414 case FB_ACTIVATE_NXTOPEN:
|
|
2415 case FB_ACTIVATE_NOW:
|
|
2416 break;
|
|
2417 default:
|
|
2418 return -EINVAL;
|
|
2419 }
|
|
2420
|
|
2421 memcpy (&disp->var, &v, sizeof (v));
|
|
2422
|
1914
|
2423 if (chgvar) {
|
|
2424 radeon_set_dispsw(rinfo, disp);
|
|
2425
|
|
2426 if (noaccel)
|
|
2427 disp->scrollmode = SCROLL_YREDRAW;
|
|
2428 else
|
|
2429 disp->scrollmode = 0;
|
|
2430
|
|
2431 if (info && info->changevar)
|
|
2432 info->changevar(con);
|
|
2433 }
|
|
2434
|
2132
|
2435 err = radeon_load_video_mode (rinfo, &v);
|
|
2436 if(err) return err;
|
1914
|
2437 do_install_cmap(con, info);
|
|
2438
|
1911
|
2439 return 0;
|
|
2440 }
|
|
2441
|
|
2442
|
|
2443
|
|
2444 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
2445 struct fb_info *info)
|
|
2446 {
|
|
2447 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2448 struct display *disp;
|
|
2449
|
|
2450 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2451
|
|
2452 if (con == rinfo->currcon) {
|
|
2453 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
|
|
2454 return rc;
|
|
2455 } else if (disp->cmap.len)
|
|
2456 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
|
|
2457 else
|
|
2458 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
|
|
2459 cmap, kspc ? 0 : 2);
|
|
2460
|
|
2461 return 0;
|
|
2462 }
|
|
2463
|
|
2464
|
|
2465
|
|
2466 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
|
|
2467 struct fb_info *info)
|
|
2468 {
|
|
2469 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2470 struct display *disp;
|
|
2471 unsigned int cmap_len;
|
|
2472
|
|
2473 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2474
|
|
2475 cmap_len = radeon_get_cmap_len (&disp->var);
|
|
2476 if (disp->cmap.len != cmap_len) {
|
|
2477 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
|
|
2478 if (err)
|
|
2479 return err;
|
|
2480 }
|
|
2481
|
|
2482 if (con == rinfo->currcon) {
|
|
2483 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
|
|
2484 return rc;
|
|
2485 } else
|
|
2486 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
|
|
2487
|
|
2488 return 0;
|
|
2489 }
|
|
2490
|
|
2491
|
|
2492
|
|
2493 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
|
|
2494 struct fb_info *info)
|
|
2495 {
|
|
2496 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
2497 u32 offset, xoffset, yoffset;
|
|
2498
|
|
2499 xoffset = (var->xoffset + 7) & ~7;
|
|
2500 yoffset = var->yoffset;
|
1911
|
2501
|
1914
|
2502 if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
|
|
2503 var->yres_virtual))
|
|
2504 return -EINVAL;
|
1911
|
2505
|
1914
|
2506 offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
|
|
2507
|
|
2508 OUTREG(CRTC_OFFSET, offset);
|
1911
|
2509
|
|
2510 return 0;
|
|
2511 }
|
|
2512
|
|
2513
|
1914
|
2514 static void do_install_cmap(int con, struct fb_info *info)
|
|
2515 {
|
|
2516 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2517
|
|
2518 if (con != rinfo->currcon)
|
|
2519 return;
|
|
2520
|
|
2521 if (fb_display[con].cmap.len)
|
|
2522 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
|
|
2523 else {
|
|
2524 int size = fb_display[con].var.bits_per_pixel == 8 ? 256 : 32;
|
|
2525 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
|
|
2526 }
|
|
2527 }
|
|
2528
|
|
2529
|
|
2530 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
|
|
2531 struct fb_var_screeninfo *var,
|
|
2532 struct fb_var_screeninfo *v,
|
|
2533 int nom, int den)
|
|
2534 {
|
|
2535 static struct {
|
|
2536 int xres, yres;
|
|
2537 } modes[] = {
|
|
2538 {1600, 1280},
|
|
2539 {1280, 1024},
|
|
2540 {1024, 768},
|
|
2541 {800, 600},
|
|
2542 {640, 480},
|
|
2543 {-1, -1}
|
|
2544 };
|
|
2545 int i;
|
|
2546
|
|
2547 /* use highest possible virtual resolution */
|
|
2548 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
|
|
2549 printk("radeonfb: using max availabe virtual resolution\n");
|
|
2550 for (i=0; modes[i].xres != -1; i++) {
|
|
2551 if (modes[i].xres * nom / den * modes[i].yres <
|
|
2552 rinfo->video_ram / 2)
|
|
2553 break;
|
|
2554 }
|
|
2555 if (modes[i].xres == -1) {
|
|
2556 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
|
|
2557 return -EINVAL;
|
|
2558 }
|
|
2559 v->xres_virtual = modes[i].xres;
|
|
2560 v->yres_virtual = modes[i].yres;
|
|
2561
|
|
2562 printk("radeonfb: virtual resolution set to max of %dx%d\n",
|
|
2563 v->xres_virtual, v->yres_virtual);
|
|
2564 } else if (v->xres_virtual == -1) {
|
|
2565 v->xres_virtual = (rinfo->video_ram * den /
|
|
2566 (nom * v->yres_virtual * 2)) & ~15;
|
|
2567 } else if (v->yres_virtual == -1) {
|
|
2568 v->xres_virtual = (v->xres_virtual + 15) & ~15;
|
|
2569 v->yres_virtual = rinfo->video_ram * den /
|
|
2570 (nom * v->xres_virtual *2);
|
|
2571 } else {
|
|
2572 if (v->xres_virtual * nom / den * v->yres_virtual >
|
|
2573 rinfo->video_ram) {
|
|
2574 return -EINVAL;
|
|
2575 }
|
|
2576 }
|
|
2577
|
|
2578 if (v->xres_virtual * nom / den >= 8192) {
|
|
2579 v->xres_virtual = 8192 * den / nom - 16;
|
|
2580 }
|
|
2581
|
|
2582 if (v->xres_virtual < v->xres)
|
|
2583 return -EINVAL;
|
|
2584
|
|
2585 if (v->yres_virtual < v->yres)
|
|
2586 return -EINVAL;
|
|
2587
|
|
2588 return 0;
|
|
2589 }
|
|
2590
|
1911
|
2591
|
|
2592 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
|
|
2593 unsigned long arg, int con, struct fb_info *info)
|
|
2594 {
|
|
2595 return -EINVAL;
|
|
2596 }
|
|
2597
|
|
2598
|
|
2599
|
|
2600 static int radeonfb_switch (int con, struct fb_info *info)
|
|
2601 {
|
|
2602 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2603 struct display *disp;
|
|
2604 struct fb_cmap *cmap;
|
|
2605 int switchcon = 0;
|
1914
|
2606
|
1911
|
2607 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
|
|
2608
|
|
2609 if (rinfo->currcon >= 0) {
|
|
2610 cmap = &(rinfo->currcon_display->cmap);
|
|
2611 if (cmap->len)
|
|
2612 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
|
|
2613 }
|
|
2614
|
|
2615 if ((disp->var.xres != rinfo->xres) ||
|
|
2616 (disp->var.yres != rinfo->yres) ||
|
|
2617 (disp->var.pixclock != rinfo->pixclock) ||
|
|
2618 (disp->var.bits_per_pixel != rinfo->depth))
|
|
2619 switchcon = 1;
|
|
2620
|
|
2621 if (switchcon) {
|
|
2622 rinfo->currcon = con;
|
|
2623 rinfo->currcon_display = disp;
|
|
2624 disp->var.activate = FB_ACTIVATE_NOW;
|
|
2625
|
|
2626 radeonfb_set_var (&disp->var, con, info);
|
1914
|
2627 radeon_set_dispsw (rinfo, disp);
|
|
2628 do_install_cmap(con, info);
|
1911
|
2629 }
|
|
2630 return 0;
|
|
2631 }
|
|
2632
|
|
2633
|
|
2634
|
|
2635 static int radeonfb_updatevar (int con, struct fb_info *info)
|
|
2636 {
|
|
2637 int rc;
|
|
2638
|
|
2639 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
|
|
2640 con, info);
|
|
2641
|
|
2642 return rc;
|
|
2643 }
|
|
2644
|
|
2645 static void radeonfb_blank (int blank, struct fb_info *info)
|
|
2646 {
|
|
2647 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
2648 u32 val = INREG(CRTC_EXT_CNTL);
|
|
2649
|
|
2650 /* reset it */
|
|
2651 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
|
|
2652 CRTC_VSYNC_DIS);
|
1911
|
2653
|
|
2654 switch (blank) {
|
1914
|
2655 case VESA_NO_BLANKING:
|
|
2656 break;
|
|
2657 case VESA_VSYNC_SUSPEND:
|
|
2658 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
|
1911
|
2659 break;
|
1914
|
2660 case VESA_HSYNC_SUSPEND:
|
|
2661 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
|
1911
|
2662 break;
|
1914
|
2663 case VESA_POWERDOWN:
|
|
2664 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
|
|
2665 CRTC_HSYNC_DIS);
|
1911
|
2666 break;
|
|
2667 }
|
1915
|
2668 if(blank == VESA_NO_BLANKING && rinfo->hasCRTC2)
|
|
2669 OUTREGP(CRTC_EXT_CNTL,CRTC_CRT_ON, val);
|
|
2670 else OUTREG(CRTC_EXT_CNTL, val);
|
1911
|
2671 }
|
|
2672
|
|
2673
|
|
2674
|
|
2675 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
|
|
2676 {
|
|
2677 int rc = 16; /* reasonable default */
|
|
2678
|
|
2679 switch (var->bits_per_pixel) {
|
|
2680 case 8:
|
|
2681 rc = 256;
|
|
2682 break;
|
|
2683 case 16:
|
|
2684 rc = 64;
|
|
2685 break;
|
|
2686 default:
|
|
2687 rc = 32;
|
|
2688 break;
|
|
2689 }
|
|
2690
|
|
2691 return rc;
|
|
2692 }
|
|
2693
|
|
2694
|
|
2695
|
|
2696 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
|
|
2697 unsigned *blue, unsigned *transp,
|
|
2698 struct fb_info *info)
|
|
2699 {
|
|
2700 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
|
2701
|
|
2702 if (regno > 255)
|
|
2703 return 1;
|
|
2704
|
|
2705 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
|
|
2706 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
|
|
2707 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
|
|
2708 *transp = 0;
|
|
2709
|
|
2710 return 0;
|
|
2711 }
|
|
2712
|
|
2713
|
|
2714
|
|
2715 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
|
|
2716 unsigned blue, unsigned transp, struct fb_info *info)
|
|
2717 {
|
|
2718 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
|
1914
|
2719 u32 pindex;
|
1911
|
2720
|
|
2721 if (regno > 255)
|
|
2722 return 1;
|
|
2723
|
|
2724 red >>= 8;
|
|
2725 green >>= 8;
|
|
2726 blue >>= 8;
|
|
2727 rinfo->palette[regno].red = red;
|
|
2728 rinfo->palette[regno].green = green;
|
|
2729 rinfo->palette[regno].blue = blue;
|
|
2730
|
|
2731 /* init gamma for hicolor */
|
|
2732 if ((rinfo->depth > 8) && (regno == 0)) {
|
|
2733 int i;
|
|
2734
|
|
2735 for (i=0; i<255; i++) {
|
|
2736 OUTREG(PALETTE_INDEX, i);
|
1914
|
2737 OUTREG(PALETTE_DATA, (i << 16) | (i << 8) | i);
|
1911
|
2738 }
|
|
2739 }
|
|
2740
|
|
2741 /* default */
|
|
2742 pindex = regno;
|
1914
|
2743
|
|
2744 /* XXX actually bpp, fixme */
|
|
2745 if (rinfo->depth == 16)
|
|
2746 pindex = regno * 8;
|
|
2747
|
|
2748 if (rinfo->depth == 16) {
|
|
2749 OUTREG(PALETTE_INDEX, pindex/2);
|
|
2750 OUTREG(PALETTE_DATA, (rinfo->palette[regno/2].red << 16) |
|
|
2751 (green << 8) | (rinfo->palette[regno/2].blue));
|
|
2752 green = rinfo->palette[regno/2].green;
|
|
2753 }
|
|
2754
|
|
2755 if ((rinfo->depth == 8) || (regno < 32)) {
|
|
2756 OUTREG(PALETTE_INDEX, pindex);
|
|
2757 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
|
|
2758 }
|
|
2759
|
|
2760 #if 0
|
1911
|
2761 col = (red << 16) | (green << 8) | blue;
|
|
2762
|
|
2763 if (rinfo->depth == 16) {
|
|
2764 pindex = regno << 3;
|
|
2765
|
|
2766 if ((rinfo->depth == 16) && (regno >= 32)) {
|
|
2767 pindex -= 252;
|
|
2768
|
|
2769 col = (rinfo->palette[regno >> 1].red << 16) |
|
|
2770 (green << 8) |
|
|
2771 (rinfo->palette[regno >> 1].blue);
|
|
2772 } else {
|
|
2773 col = (red << 16) | (green << 8) | blue;
|
|
2774 }
|
|
2775 }
|
|
2776
|
|
2777 OUTREG8(PALETTE_INDEX, pindex);
|
|
2778 radeon_fifo_wait(32);
|
|
2779 OUTREG(PALETTE_DATA, col);
|
1914
|
2780 #endif
|
1911
|
2781
|
|
2782 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
|
|
2783 if (regno < 32) {
|
|
2784 switch (rinfo->depth) {
|
|
2785 #ifdef FBCON_HAS_CFB16
|
|
2786 case 16:
|
1914
|
2787 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
|
1911
|
2788 regno;
|
|
2789 break;
|
|
2790 #endif
|
1914
|
2791 #ifdef FBCON_HAS_CFB24
|
|
2792 case 24:
|
|
2793 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
|
|
2794 break;
|
|
2795 #endif
|
1911
|
2796 #ifdef FBCON_HAS_CFB32
|
|
2797 case 32: {
|
|
2798 u32 i;
|
|
2799
|
|
2800 i = (regno << 8) | regno;
|
|
2801 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
|
|
2802 break;
|
|
2803 }
|
|
2804 #endif
|
|
2805 }
|
|
2806 }
|
|
2807 #endif
|
|
2808 return 0;
|
|
2809 }
|
|
2810
|
2132
|
2811 static void radeon_save_common_regs(struct radeonfb_info *rinfo,
|
|
2812 struct radeon_regs *save)
|
|
2813 {
|
|
2814 RTRACE("radeonfb: radeon_save_common_regs is called\n");
|
|
2815 save->ovr_clr = INREG(OVR_CLR);
|
|
2816 save->ovr_wid_left_right= INREG(OVR_WID_LEFT_RIGHT);
|
|
2817 save->ovr_wid_top_bottom= INREG(OVR_WID_TOP_BOTTOM);
|
|
2818 save->ov0_scale_cntl = INREG(OV0_SCALE_CNTL);
|
|
2819 save->mpp_tb_config = INREG(MPP_TB_CONFIG);
|
|
2820 save->mpp_gp_config = INREG(MPP_GP_CONFIG);
|
|
2821 save->subpic_cntl = INREG(SUBPIC_CNTL);
|
|
2822 save->viph_control = INREG(VIPH_CONTROL);
|
|
2823 save->i2c_cntl_1 = INREG(I2C_CNTL_1);
|
|
2824 save->gen_int_cntl = INREG(GEN_INT_CNTL);
|
|
2825 save->cap0_trig_cntl = INREG(CAP0_TRIG_CNTL);
|
|
2826 save->cap1_trig_cntl = INREG(CAP1_TRIG_CNTL);
|
|
2827 save->bus_cntl = INREG(BUS_CNTL);
|
|
2828 }
|
|
2829
|
|
2830 static void radeon_save_crtc_regs(struct radeonfb_info *rinfo,
|
|
2831 struct radeon_regs *save)
|
|
2832 {
|
|
2833 RTRACE("radeonfb: radeon_save_crtc_regs is called\n");
|
|
2834 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
|
|
2835 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
|
|
2836 save->dac_cntl = INREG(DAC_CNTL);
|
|
2837 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
|
|
2838 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
|
|
2839 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
|
|
2840 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
|
|
2841 save->crtc_offset = INREG(CRTC_OFFSET);
|
|
2842 save->crtc_offset_cntl = INREG(CRTC_OFFSET_CNTL);
|
|
2843 save->crtc_pitch = INREG(CRTC_PITCH);
|
|
2844 }
|
|
2845
|
|
2846 static void radeon_save_crtc2_regs(struct radeonfb_info *rinfo,
|
|
2847 struct radeon_regs *save)
|
|
2848 {
|
|
2849 RTRACE("radeonfb: radeon_save_crtc2_regs is called\n");
|
|
2850 save->dac2_cntl = INREG(DAC_CNTL2);
|
|
2851 save->disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
|
|
2852
|
|
2853 save->crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
|
|
2854 save->crtc2_h_total_disp = INREG(CRTC2_H_TOTAL_DISP);
|
|
2855 save->crtc2_h_sync_strt_wid = INREG(CRTC2_H_SYNC_STRT_WID);
|
|
2856 save->crtc2_v_total_disp = INREG(CRTC2_V_TOTAL_DISP);
|
|
2857 save->crtc2_v_sync_strt_wid = INREG(CRTC2_V_SYNC_STRT_WID);
|
|
2858 save->crtc2_offset = INREG(CRTC2_OFFSET);
|
|
2859 save->crtc2_offset_cntl = INREG(CRTC2_OFFSET_CNTL);
|
|
2860 save->crtc2_pitch = INREG(CRTC2_PITCH);
|
|
2861 }
|
|
2862
|
|
2863 static void radeon_save_fp_regs(struct radeonfb_info *rinfo,
|
|
2864 struct radeon_regs *save)
|
|
2865 {
|
|
2866 RTRACE("radeonfb: radeon_save_fp_regs is called\n");
|
|
2867 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
|
|
2868 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
|
|
2869 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
|
|
2870 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
|
|
2871 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
|
|
2872 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
|
|
2873 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
|
|
2874 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
|
|
2875 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
|
|
2876 save->tmds_crc = INREG(TMDS_CRC);
|
|
2877 }
|
|
2878
|
|
2879 static void radeon_save_pll_regs(struct radeonfb_info *rinfo,
|
|
2880 struct radeon_regs *save)
|
|
2881 {
|
|
2882 RTRACE("radeonfb: radeon_save_pll_regs is called\n");
|
|
2883 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
|
|
2884 save->ppll_div_3 = INPLL(PPLL_DIV_3);
|
|
2885 save->htotal_cntl = INPLL(HTOTAL_CNTL);
|
|
2886 }
|
|
2887
|
|
2888 static void radeon_save_pll2_regs(struct radeonfb_info *rinfo,
|
|
2889 struct radeon_regs *save)
|
|
2890 {
|
|
2891 RTRACE("radeonfb: radeon_save_pll2_regs is called\n");
|
|
2892 save->p2pll_ref_div = INPLL(P2PLL_REF_DIV);
|
|
2893 save->p2pll_div_0 = INPLL(P2PLL_DIV_0);
|
|
2894 save->htotal_cntl2 = INPLL(HTOTAL2_CNTL);
|
|
2895 }
|
|
2896
|
|
2897 static void radeon_save_dda_regs(struct radeonfb_info *rinfo,
|
|
2898 struct radeon_regs *save)
|
|
2899 {
|
|
2900 RTRACE("radeonfb: radeon_save_dda_regs is called\n");
|
|
2901 save->dda_config = INREG(DDA_CONFIG);
|
|
2902 save->dda_on_off = INREG(DDA_ON_OFF);
|
|
2903 }
|
|
2904
|
|
2905 #if 0
|
|
2906 static void radeon_save_palette(struct radeonfb_info *rinfo,
|
1911
|
2907 struct radeon_regs *save)
|
|
2908 {
|
2132
|
2909 int i;
|
|
2910 RTRACE("radeonfb: radeon_save_palette is called\n");
|
|
2911 PAL_SELECT(1);
|
|
2912 INPAL_START(0);
|
|
2913 for (i = 0; i < 256; i++) save->palette2[i] = INPAL_NEXT();
|
|
2914 PAL_SELECT(0);
|
|
2915 INPAL_START(0);
|
|
2916 for (i = 0; i < 256; i++) save->palette[i] = INPAL_NEXT();
|
|
2917 }
|
|
2918 #endif
|
|
2919
|
|
2920 static void radeon_write_common_regs(struct radeonfb_info *rinfo,
|
|
2921 struct radeon_regs *restore)
|
|
2922 {
|
|
2923 RTRACE("radeonfb: radeon_write_common_regs is called\n");
|
|
2924 OUTREG(OVR_CLR, restore->ovr_clr);
|
|
2925 OUTREG(OVR_WID_LEFT_RIGHT, restore->ovr_wid_left_right);
|
|
2926 OUTREG(OVR_WID_TOP_BOTTOM, restore->ovr_wid_top_bottom);
|
|
2927 OUTREG(OV0_SCALE_CNTL, restore->ov0_scale_cntl);
|
|
2928 OUTREG(MPP_TB_CONFIG, restore->mpp_tb_config );
|
|
2929 OUTREG(MPP_GP_CONFIG, restore->mpp_gp_config );
|
|
2930 OUTREG(SUBPIC_CNTL, restore->subpic_cntl);
|
|
2931 OUTREG(VIPH_CONTROL, restore->viph_control);
|
|
2932 OUTREG(I2C_CNTL_1, restore->i2c_cntl_1);
|
|
2933 OUTREG(GEN_INT_CNTL, restore->gen_int_cntl);
|
|
2934 OUTREG(CAP0_TRIG_CNTL, restore->cap0_trig_cntl);
|
|
2935 OUTREG(CAP1_TRIG_CNTL, restore->cap1_trig_cntl);
|
|
2936 OUTREG(BUS_CNTL, restore->bus_cntl);
|
|
2937 }
|
|
2938
|
|
2939 static void radeon_write_crtc_regs(struct radeonfb_info *rinfo,
|
|
2940 struct radeon_regs *restore)
|
|
2941 {
|
|
2942 RTRACE("radeonfb: radeon_write_crtc_regs is called\n");
|
|
2943 OUTREG(CRTC_GEN_CNTL, restore->crtc_gen_cntl);
|
|
2944
|
|
2945 OUTREGP(CRTC_EXT_CNTL, restore->crtc_ext_cntl,
|
|
2946 CRTC_VSYNC_DIS |
|
|
2947 CRTC_HSYNC_DIS |
|
|
2948 CRTC_DISPLAY_DIS);
|
|
2949
|
|
2950 OUTREGP(DAC_CNTL, restore->dac_cntl,
|
|
2951 DAC_RANGE_CNTL |
|
|
2952 DAC_BLANKING);
|
|
2953
|
|
2954 OUTREG(CRTC_H_TOTAL_DISP, restore->crtc_h_total_disp);
|
|
2955 OUTREG(CRTC_H_SYNC_STRT_WID, restore->crtc_h_sync_strt_wid);
|
|
2956 OUTREG(CRTC_V_TOTAL_DISP, restore->crtc_v_total_disp);
|
|
2957 OUTREG(CRTC_V_SYNC_STRT_WID, restore->crtc_v_sync_strt_wid);
|
|
2958 OUTREG(CRTC_OFFSET, restore->crtc_offset);
|
|
2959 OUTREG(CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
|
|
2960 OUTREG(CRTC_PITCH, restore->crtc_pitch);
|
|
2961 }
|
|
2962
|
|
2963 static void radeon_write_crtc2_regs(struct radeonfb_info *rinfo,
|
|
2964 struct radeon_regs *restore)
|
|
2965 {
|
|
2966 RTRACE("radeonfb: radeon_write_crtc2_regs is called\n");
|
|
2967 /* OUTREG(CRTC2_GEN_CNTL, restore->crtc2_gen_cntl);*/
|
|
2968 OUTREGP(CRTC2_GEN_CNTL, restore->crtc2_gen_cntl,
|
|
2969 CRTC2_VSYNC_DIS |
|
|
2970 CRTC2_HSYNC_DIS |
|
|
2971 CRTC2_DISP_DIS);
|
|
2972
|
|
2973 OUTREG(DAC_CNTL2, restore->dac2_cntl);
|
|
2974 OUTREG(DISP_OUTPUT_CNTL, restore->disp_output_cntl);
|
|
2975
|
|
2976 OUTREG(CRTC2_H_TOTAL_DISP, restore->crtc2_h_total_disp);
|
|
2977 OUTREG(CRTC2_H_SYNC_STRT_WID, restore->crtc2_h_sync_strt_wid);
|
|
2978 OUTREG(CRTC2_V_TOTAL_DISP, restore->crtc2_v_total_disp);
|
|
2979 OUTREG(CRTC2_V_SYNC_STRT_WID, restore->crtc2_v_sync_strt_wid);
|
|
2980 OUTREG(CRTC2_OFFSET, restore->crtc2_offset);
|
|
2981 OUTREG(CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
|
|
2982 OUTREG(CRTC2_PITCH, restore->crtc2_pitch);
|
|
2983 }
|
|
2984
|
|
2985 static void radeon_write_fp_regs(struct radeonfb_info *rinfo,
|
|
2986 struct radeon_regs *restore)
|
|
2987 {
|
|
2988 int prim_mon;
|
|
2989 u32 tmp;
|
|
2990 RTRACE("radeonfb: radeon_write_fp_regs is called\n");
|
|
2991 OUTREG(FP_CRTC_H_TOTAL_DISP, restore->fp_crtc_h_total_disp);
|
|
2992 OUTREG(FP_CRTC_V_TOTAL_DISP, restore->fp_crtc_v_total_disp);
|
|
2993 OUTREG(FP_H_SYNC_STRT_WID, restore->fp_h_sync_strt_wid);
|
|
2994 OUTREG(FP_V_SYNC_STRT_WID, restore->fp_v_sync_strt_wid);
|
|
2995 OUTREG(TMDS_CRC, restore->tmds_crc);
|
|
2996 OUTREG(FP_HORZ_STRETCH, restore->fp_horz_stretch);
|
|
2997 OUTREG(FP_VERT_STRETCH, restore->fp_vert_stretch);
|
|
2998 OUTREG(FP_GEN_CNTL, restore->fp_gen_cntl);
|
|
2999 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
3000 if(prim_mon == MT_LCD) {
|
|
3001 tmp = INREG(LVDS_GEN_CNTL);
|
|
3002 if((tmp & (LVDS_ON | LVDS_BLON)) ==
|
|
3003 (restore->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
|
|
3004 OUTREG(LVDS_GEN_CNTL, restore->lvds_gen_cntl);
|
|
3005 }
|
|
3006 }
|
|
3007 else {
|
|
3008 if (restore->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
|
|
3009 #if 0
|
|
3010 /* TODO it later */
|
|
3011 usleep(rinfo->PanelPwrDly * 1000);
|
|
3012 #endif
|
|
3013 OUTREG(LVDS_GEN_CNTL, restore->lvds_gen_cntl);
|
|
3014 }
|
|
3015 else {
|
|
3016 OUTREG(LVDS_GEN_CNTL,
|
|
3017 restore->lvds_gen_cntl | LVDS_BLON);
|
|
3018 #if 0
|
|
3019 /* TODO it later */
|
|
3020 usleep(rinfo->PanelPwrDly * 1000);
|
|
3021 #endif
|
|
3022 OUTREG(LVDS_GEN_CNTL, restore->lvds_gen_cntl);
|
|
3023 }
|
|
3024 }
|
1911
|
3025 }
|
|
3026
|
2132
|
3027 static void radeon_write_pll_regs(struct radeonfb_info *rinfo,
|
|
3028 struct radeon_regs *restore)
|
|
3029 {
|
|
3030 RTRACE("radeonfb: radeon_write_pll_regs is called\n");
|
|
3031 OUTPLLP(0x08, 0x00, ~(0x03));
|
|
3032 while ( (INREG(CLOCK_CNTL_INDEX) & PLL_DIV_SEL) != PLL_DIV_SEL) {
|
|
3033 OUTREGP(CLOCK_CNTL_INDEX, PLL_DIV_SEL, 0xffff);
|
|
3034 }
|
|
3035 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
|
|
3036 while ( (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
|
|
3037 (restore->ppll_ref_div & PPLL_REF_DIV_MASK)) {
|
|
3038 OUTPLLP(PPLL_REF_DIV,
|
|
3039 restore->ppll_ref_div, ~PPLL_REF_DIV_MASK);
|
|
3040 }
|
|
3041 while ( (INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
|
|
3042 (restore->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
|
|
3043 OUTPLLP(PPLL_DIV_3,restore->ppll_div_3, ~PPLL_FB3_DIV_MASK);
|
|
3044 }
|
|
3045 while ( (INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
|
|
3046 (restore->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
|
|
3047 OUTPLLP(PPLL_DIV_3,restore->ppll_div_3, ~PPLL_POST3_DIV_MASK);
|
|
3048 }
|
|
3049 OUTPLL(HTOTAL_CNTL, restore->htotal_cntl);
|
|
3050 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
|
|
3051 OUTPLLP(0x08, 0x03, ~(0x03));
|
|
3052 }
|
|
3053
|
|
3054
|
|
3055 static void radeon_write_pll2_regs(struct radeonfb_info *rinfo,
|
|
3056 struct radeon_regs *restore)
|
|
3057 {
|
|
3058 RTRACE("radeonfb: radeon_write_pll2_regs is called\n");
|
|
3059 OUTPLLP(0x2d, 0x00, ~(0x03));
|
|
3060 while (INREG(CLOCK_CNTL_INDEX) & ~(PLL2_DIV_SEL_MASK)) {
|
|
3061 OUTREGP(CLOCK_CNTL_INDEX, 0, PLL2_DIV_SEL_MASK);
|
|
3062 }
|
|
3063 OUTPLLP(P2PLL_CNTL,P2PLL_RESET,0xffff);
|
|
3064 while ( (INPLL(P2PLL_REF_DIV) & P2PLL_REF_DIV_MASK) !=
|
|
3065 (restore->p2pll_ref_div & P2PLL_REF_DIV_MASK)) {
|
|
3066 OUTPLLP(P2PLL_REF_DIV, restore->p2pll_ref_div, ~P2PLL_REF_DIV_MASK);
|
|
3067 }
|
|
3068 while ( (INPLL(P2PLL_DIV_0) & P2PLL_FB0_DIV_MASK) !=
|
|
3069 (restore->p2pll_div_0 & P2PLL_FB0_DIV_MASK)) {
|
|
3070 OUTPLLP(P2PLL_DIV_0, restore->p2pll_div_0, ~P2PLL_FB0_DIV_MASK);
|
|
3071 }
|
|
3072 while ( (INPLL(P2PLL_DIV_0) & P2PLL_POST0_DIV_MASK) !=
|
|
3073 (restore->p2pll_div_0 & P2PLL_POST0_DIV_MASK)) {
|
|
3074 OUTPLLP(P2PLL_DIV_0,restore->p2pll_div_0, ~P2PLL_POST0_DIV_MASK);
|
|
3075 }
|
|
3076 OUTPLL(HTOTAL2_CNTL, restore->htotal_cntl2);
|
|
3077 OUTPLLP(P2PLL_CNTL, 0, ~(P2PLL_RESET | P2PLL_SLEEP));
|
|
3078 OUTPLLP(0x2d, 0x03, ~(0x03));
|
|
3079 }
|
|
3080
|
|
3081 static void radeon_write_dda_regs(struct radeonfb_info *rinfo,
|
|
3082 struct radeon_regs *restore)
|
|
3083 {
|
|
3084 RTRACE("radeonfb: radeon_write_dda_regs is called\n");
|
|
3085 OUTREG(DDA_CONFIG, restore->dda_config);
|
|
3086 OUTREG(DDA_ON_OFF, restore->dda_on_off);
|
|
3087 }
|
|
3088
|
|
3089 #if 0
|
|
3090 static void radeon_write_palette(struct radeonfb_info *rinfo,
|
|
3091 struct radeon_regs *restore)
|
|
3092 {
|
|
3093 int i;
|
|
3094
|
|
3095 RTRACE("radeonfb: radeon_write_palette is called\n");
|
|
3096 PAL_SELECT(1);
|
|
3097 OUTPAL_START(0);
|
|
3098 for (i = 0; i < 256; i++) {
|
|
3099 RADEONWaitForFifo(32); /* delay */
|
|
3100 OUTPAL_NEXT_CARD32(restore->palette2[i]);
|
|
3101 }
|
|
3102
|
|
3103 PAL_SELECT(0);
|
|
3104 OUTPAL_START(0);
|
|
3105 for (i = 0; i < 256; i++) {
|
|
3106 RADEONWaitForFifo(32); /* delay */
|
|
3107 OUTPAL_NEXT_CARD32(restore->palette[i]);
|
|
3108 }
|
|
3109 }
|
|
3110 #endif
|
|
3111
|
|
3112 static void radeon_save_mode (struct radeonfb_info *rinfo,
|
|
3113 struct radeon_regs *save)
|
|
3114 {
|
|
3115 int prim_mon;
|
|
3116 RTRACE("radeonfb: radeon_save_mode is called\n");
|
|
3117 if(DUAL_MONITOR(rinfo)) {
|
|
3118 radeon_save_crtc2_regs(rinfo,save);
|
|
3119 radeon_save_pll2_regs(rinfo,save);
|
|
3120 }
|
|
3121 radeon_save_common_regs(rinfo,save);
|
|
3122 radeon_save_crtc_regs(rinfo,save);
|
|
3123 prim_mon = PRIMARY_MONITOR(rinfo);
|
|
3124 if(prim_mon == MT_LCD || prim_mon == MT_DFP) radeon_save_fp_regs(rinfo,save);
|
|
3125 radeon_save_pll_regs(rinfo,save);
|
|
3126 radeon_save_dda_regs(rinfo,save);
|
|
3127 /*radeon_save_palette(rinfo,save);*/
|
|
3128 }
|
|
3129
|
|
3130 static void radeon_save_state(struct radeonfb_info *rinfo,
|
|
3131 struct radeon_regs *save)
|
|
3132 {
|
|
3133 RTRACE("radeonfb: radeon_save_state is called\n");
|
|
3134 save->dp_datatype = INREG(DP_DATATYPE);
|
|
3135 save->rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
|
|
3136 save->clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
|
|
3137 save->amcgpio_en_reg = INREG(AMCGPIO_EN_REG);
|
|
3138 save->amcgpio_mask = INREG(AMCGPIO_MASK);
|
|
3139 radeon_save_mode(rinfo,save);
|
|
3140 }
|
|
3141
|
|
3142 static int radeon_load_video_mode (struct radeonfb_info *rinfo,
|
1911
|
3143 struct fb_var_screeninfo *mode)
|
|
3144 {
|
2132
|
3145 /*
|
1911
|
3146 struct radeon_regs newmode;
|
2132
|
3147
|
|
3148 RTRACE("radeonfb: radeon_load_video_mode is called\n");
|
|
3149 if(!radeon_init_mode(rinfo, &newmode, mode)) return -1;
|
|
3150
|
|
3151 radeonfb_blank(VESA_POWERDOWN,&rinfo->info);
|
|
3152 radeon_write_mode(rinfo, &newmode);
|
|
3153 radeonfb_blank(VESA_NO_BLANKING,&rinfo->info);
|
|
3154 return 0;
|
|
3155 */
|
|
3156 struct radeon_regs newmode;
|
|
3157
|
|
3158 radeon_init_common_regs(rinfo,&newmode);
|
|
3159 radeon_init_crtc_regs(rinfo,&newmode,mode);
|
|
3160 radeon_init_pll_regs(rinfo,&newmode,mode);
|
|
3161 radeon_init_dda_regs(rinfo,&newmode,mode);
|
1911
|
3162 /* do it! */
|
|
3163 radeon_write_mode (rinfo, &newmode);
|
2132
|
3164 return 0;
|
1911
|
3165 }
|
|
3166
|
|
3167 static void radeon_write_mode (struct radeonfb_info *rinfo,
|
|
3168 struct radeon_regs *mode)
|
|
3169 {
|
2132
|
3170 /*****
|
|
3171 When changing mode with Dual-head card (VE/M6), care must
|
|
3172 be taken for the special order in setting registers. CRTC2 has
|
|
3173 to be set before changing CRTC_EXT register.
|
|
3174 Otherwise we may get a blank screen.
|
|
3175 *****/
|
|
3176 RTRACE("radeonfb: radeon_write_mode is called\n");
|
|
3177 if(DUAL_MONITOR(rinfo)) {
|
|
3178 radeon_write_crtc2_regs(rinfo,mode);
|
|
3179 radeon_write_pll2_regs(rinfo,mode);
|
|
3180 }
|
|
3181 radeon_write_common_regs(rinfo,mode);
|
|
3182 radeon_write_dda_regs(rinfo,mode);
|
|
3183 radeon_write_crtc_regs(rinfo,mode);
|
|
3184 if(rinfo->crtDispType == MT_DFP || rinfo->crtDispType == MT_LCD) {
|
|
3185 radeon_write_fp_regs(rinfo,mode);
|
1911
|
3186 }
|
2132
|
3187 radeon_write_pll_regs(rinfo,mode);
|
|
3188 }
|
|
3189
|
|
3190 static void radeon_write_state (struct radeonfb_info *rinfo,
|
|
3191 struct radeon_regs *restore)
|
|
3192 {
|
|
3193 RTRACE("radeonfb: radeon_write_state is called\n");
|
|
3194 radeonfb_blank(VESA_POWERDOWN,&rinfo->info);
|
|
3195 OUTREG(AMCGPIO_MASK, restore->amcgpio_mask);
|
|
3196 OUTREG(AMCGPIO_EN_REG, restore->amcgpio_en_reg);
|
|
3197 OUTREG(CLOCK_CNTL_INDEX,restore->clock_cntl_index);
|
|
3198 OUTREG(RBBM_SOFT_RESET, restore->rbbm_soft_reset);
|
|
3199 OUTREG(DP_DATATYPE, restore->dp_datatype);
|
|
3200 /* M6 card has trouble restoring text mode for its CRT.
|
|
3201 Needs this workaround.*/
|
|
3202 if(rinfo->isM6) OUTREG(DAC_CNTL2, restore->dac2_cntl);
|
|
3203 radeon_write_mode(rinfo,restore);
|
|
3204 radeonfb_blank(VESA_NO_BLANKING,&rinfo->info);
|
1911
|
3205 }
|
|
3206
|
1914
|
3207 #if 0
|
1911
|
3208
|
|
3209 /*
|
|
3210 * text console acceleration
|
|
3211 */
|
|
3212
|
|
3213
|
|
3214 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
|
|
3215 int dsty, int dstx, int height, int width)
|
|
3216 {
|
|
3217 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
3218 u32 dp_cntl = DST_LAST_PEL;
|
|
3219
|
|
3220 srcx *= fontwidth(p);
|
|
3221 srcy *= fontheight(p);
|
|
3222 dstx *= fontwidth(p);
|
|
3223 dsty *= fontheight(p);
|
|
3224 width *= fontwidth(p);
|
|
3225 height *= fontheight(p);
|
|
3226
|
|
3227 if (srcy < dsty) {
|
|
3228 srcy += height - 1;
|
|
3229 dsty += height - 1;
|
|
3230 } else
|
|
3231 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
|
|
3232
|
|
3233 if (srcx < dstx) {
|
|
3234 srcx += width - 1;
|
|
3235 dstx += width - 1;
|
|
3236 } else
|
|
3237 dp_cntl |= DST_X_LEFT_TO_RIGHT;
|
|
3238
|
|
3239 radeon_fifo_wait(6);
|
|
3240 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
3241 GMC_BRUSH_NONE |
|
|
3242 GMC_SRC_DATATYPE_COLOR |
|
|
3243 ROP3_S |
|
|
3244 DP_SRC_SOURCE_MEMORY));
|
|
3245 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
3246 OUTREG(DP_CNTL, dp_cntl);
|
|
3247 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
|
|
3248 OUTREG(DST_Y_X, (dsty << 16) | dstx);
|
|
3249 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
|
|
3250 }
|
|
3251
|
|
3252
|
|
3253
|
|
3254 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
|
|
3255 int srcy, int srcx, int height, int width)
|
|
3256 {
|
|
3257 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
|
|
3258 u32 clr;
|
|
3259
|
|
3260 clr = attr_bgcol_ec(p, conp);
|
|
3261 clr |= (clr << 8);
|
|
3262 clr |= (clr << 16);
|
|
3263
|
|
3264 srcx *= fontwidth(p);
|
|
3265 srcy *= fontheight(p);
|
|
3266 width *= fontwidth(p);
|
|
3267 height *= fontheight(p);
|
|
3268
|
|
3269 radeon_fifo_wait(6);
|
|
3270 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
|
|
3271 GMC_BRUSH_SOLID_COLOR |
|
|
3272 GMC_SRC_DATATYPE_COLOR |
|
|
3273 ROP3_P));
|
|
3274 OUTREG(DP_BRUSH_FRGD_CLR, clr);
|
|
3275 OUTREG(DP_WRITE_MSK, 0xffffffff);
|
|
3276 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
|
|
3277 OUTREG(DST_Y_X, (srcy << 16) | srcx);
|
|
3278 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
|
|
3279 }
|
|
3280
|
|
3281
|
|
3282
|
|
3283
|
|
3284 #ifdef FBCON_HAS_CFB8
|
|
3285 static struct display_switch fbcon_radeon8 = {
|
|
3286 setup: fbcon_cfb8_setup,
|
|
3287 bmove: fbcon_radeon_bmove,
|
|
3288 clear: fbcon_cfb8_clear,
|
|
3289 putc: fbcon_cfb8_putc,
|
|
3290 putcs: fbcon_cfb8_putcs,
|
|
3291 revc: fbcon_cfb8_revc,
|
|
3292 clear_margins: fbcon_cfb8_clear_margins,
|
|
3293 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
|
|
3294 };
|
|
3295 #endif
|
1914
|
3296
|
|
3297 #endif /* 0 */
|