Mercurial > mplayer.hg
annotate cpudetect.c @ 27741:0401eef4408f
cosmetics: Move _def_fast_unaligned to the FFmpeg section of config.h.
author | diego |
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date | Tue, 14 Oct 2008 23:15:10 +0000 |
parents | 48c1ae64255b |
children | 08d18fe9da52 |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
20577 | 12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
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23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
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32 #if defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 33 #include <windows.h> |
34 #endif | |
35 | |
26061 | 36 #ifdef __OS2__ |
37 #define INCL_DOS | |
38 #include <os2.h> | |
39 #endif | |
40 | |
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41 #ifdef __AMIGAOS4__ |
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42 #include <proto/exec.h> |
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43 #endif |
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44 |
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45 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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46 * help understanding how to use it. Thanks to the Mesa |
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47 * team for SSE support detection and more cpu detect code. |
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48 */ |
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49 |
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50 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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51 |
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52 static void check_os_katmai_support( void ); |
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53 |
2272 | 54 // return TRUE if cpuid supported |
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55 static int has_cpuid(void) |
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56 { |
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57 long a, c; |
2272 | 58 |
59 // code from libavcodec: | |
60 __asm__ __volatile__ ( | |
61 /* See if CPUID instruction is supported ... */ | |
62 /* ... Get copies of EFLAGS into eax and ecx */ | |
63 "pushf\n\t" | |
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64 "pop %0\n\t" |
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65 "mov %0, %1\n\t" |
2272 | 66 |
67 /* ... Toggle the ID bit in one copy and store */ | |
68 /* to the EFLAGS reg */ | |
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69 "xor $0x200000, %0\n\t" |
2272 | 70 "push %0\n\t" |
71 "popf\n\t" | |
72 | |
73 /* ... Get the (hopefully modified) EFLAGS */ | |
74 "pushf\n\t" | |
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75 "pop %0\n\t" |
2272 | 76 : "=a" (a), "=c" (c) |
77 : | |
78 : "cc" | |
79 ); | |
80 | |
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81 return a != c; |
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82 } |
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83 |
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84 static void |
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85 do_cpuid(unsigned int ax, unsigned int *p) |
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86 { |
2272 | 87 #if 0 |
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88 __asm __volatile( |
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89 "cpuid;" |
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90 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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91 : "0" (ax) |
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92 ); |
2272 | 93 #else |
94 // code from libavcodec: | |
95 __asm __volatile | |
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96 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 97 "cpuid\n\t" |
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98 "xchg %%"REG_b", %%"REG_S |
3403 | 99 : "=a" (p[0]), "=S" (p[1]), |
2272 | 100 "=c" (p[2]), "=d" (p[3]) |
101 : "0" (ax)); | |
102 #endif | |
103 | |
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104 } |
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105 |
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106 void GetCpuCaps( CpuCaps *caps) |
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107 { |
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108 unsigned int regs[4]; |
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109 unsigned int regs2[4]; |
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110 |
8860 | 111 memset(caps, 0, sizeof(*caps)); |
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112 caps->isX86=1; |
8860 | 113 caps->cl_size=32; /* default */ |
2288 | 114 if (!has_cpuid()) { |
6134 | 115 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 116 return; |
117 } | |
118 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 119 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 120 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 121 if (regs[0]>=0x00000001) |
2280 | 122 { |
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123 char *tmpstr, *ptmpstr; |
8860 | 124 unsigned cl_size; |
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125 |
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126 do_cpuid(0x00000001, regs2); |
2301 | 127 |
2288 | 128 caps->cpuType=(regs2[0] >> 8)&0xf; |
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129 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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130 |
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131 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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132 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 133 if(caps->cpuType==0xf){ |
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134 // use extended family (P4, IA64, K8) |
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135 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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136 } |
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137 if(caps->cpuType==0xf || caps->cpuType==6) |
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138 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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139 |
3403 | 140 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 141 |
142 // general feature flags: | |
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143 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 144 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
145 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
146 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 147 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 148 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
149 if(cl_size) caps->cl_size = cl_size; | |
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150 |
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151 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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152 while(*ptmpstr == ' ') // strip leading spaces |
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153 ptmpstr++; |
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154 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
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155 free(tmpstr); |
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156 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
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157 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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158 |
2288 | 159 } |
160 do_cpuid(0x80000000, regs); | |
161 if (regs[0]>=0x80000001) { | |
6134 | 162 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 163 do_cpuid(0x80000001, regs2); |
3840 | 164 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
165 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 166 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
167 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
168 } | |
8860 | 169 if(regs[0]>=0x80000006) |
170 { | |
171 do_cpuid(0x80000006, regs2); | |
172 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
173 caps->cl_size = regs2[2] & 0xFF; | |
174 } | |
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175 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 176 #if 0 |
5937 | 177 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 178 gCpuCaps.hasMMX, |
179 gCpuCaps.hasMMX2, | |
180 gCpuCaps.hasSSE, | |
181 gCpuCaps.hasSSE2, | |
182 gCpuCaps.has3DNow, | |
183 gCpuCaps.has3DNowExt ); | |
184 #endif | |
185 | |
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186 /* FIXME: Does SSE2 need more OS support, too? */ |
26060 | 187 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
188 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \ | |
26061 | 189 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \ |
190 || defined(__OS2__) | |
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191 if (caps->hasSSE) |
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192 check_os_katmai_support(); |
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193 if (!caps->hasSSE) |
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194 caps->hasSSE2 = 0; |
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195 #else |
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196 caps->hasSSE=0; |
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197 caps->hasSSE2 = 0; |
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198 #endif |
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199 // caps->has3DNow=1; |
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200 // caps->hasMMX2 = 0; |
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201 // caps->hasMMX = 0; |
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202 |
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203 #ifndef RUNTIME_CPUDETECT |
4829 | 204 #ifndef HAVE_MMX |
6134 | 205 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 206 caps->hasMMX=0; |
207 #endif | |
208 #ifndef HAVE_MMX2 | |
6134 | 209 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 210 caps->hasMMX2=0; |
211 #endif | |
212 #ifndef HAVE_SSE | |
6134 | 213 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 214 caps->hasSSE=0; |
215 #endif | |
216 #ifndef HAVE_SSE2 | |
6134 | 217 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 218 caps->hasSSE2=0; |
219 #endif | |
220 #ifndef HAVE_3DNOW | |
6134 | 221 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 222 caps->has3DNow=0; |
223 #endif | |
224 #ifndef HAVE_3DNOWEX | |
6134 | 225 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 226 caps->has3DNowExt=0; |
227 #endif | |
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228 #endif // RUNTIME_CPUDETECT |
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229 } |
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230 |
2301 | 231 |
232 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
233 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
234 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
235 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
236 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
237 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
238 | |
239 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
240 #include "cputable.h" /* get cpuname and cpuvendors */ | |
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241 char vendor[13]; |
2303 | 242 char *retname; |
13628 | 243 int i; |
2301 | 244 |
18869 | 245 if (NULL==(retname=malloc(256))) { |
5937 | 246 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 247 exit(1); |
248 } | |
249 | |
3837 | 250 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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251 |
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252 do_cpuid(0x80000000,regs); |
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253 if (regs[0] >= 0x80000004) |
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254 { |
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255 // CPU has built-in namestring |
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256 retname[0] = '\0'; |
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257 for (i = 0x80000002; i <= 0x80000004; i++) |
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258 { |
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259 do_cpuid(i, regs); |
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260 strncat(retname, (char*)regs, 16); |
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261 } |
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262 return retname; |
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263 } |
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264 |
2301 | 265 for(i=0; i<MAX_VENDORS; i++){ |
266 if(!strcmp(cpuvendors[i].string,vendor)){ | |
267 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 268 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 269 } else { |
13628 | 270 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 271 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
272 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
273 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
274 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
275 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
276 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
277 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 278 "to the MPlayer-Developers, so we can add it to the list!\n"); |
279 } | |
280 } | |
281 } | |
14478 | 282 retname[255] = 0; |
2301 | 283 |
284 //printf("Detected CPU: %s\n", retname); | |
285 return retname; | |
286 } | |
287 | |
288 #undef CPUID_EXTFAMILY | |
289 #undef CPUID_EXTMODEL | |
290 #undef CPUID_TYPE | |
291 #undef CPUID_FAMILY | |
292 #undef CPUID_MODEL | |
293 #undef CPUID_STEPPING | |
294 | |
295 | |
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296 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64) |
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297 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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298 { |
6134 | 299 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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300 |
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301 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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302 * instructions are 3 bytes long. We must increment the instruction |
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303 * pointer manually to avoid repeated execution of the offending |
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304 * instruction. |
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305 * |
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306 * If the SIGILL is caused by a divide-by-zero when unmasked |
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307 * exceptions aren't supported, the SIMD FPU status and control |
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308 * word will be restored at the end of the test, so we don't need |
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309 * to worry about doing it here. Besides, we may not be able to... |
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310 */ |
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311 sc.eip += 3; |
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312 |
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313 gCpuCaps.hasSSE=0; |
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314 } |
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315 #endif /* __linux__ && _POSIX_SOURCE */ |
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316 |
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317 #if defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 318 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
319 { | |
320 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
321 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
322 ep->ContextRecord->Eip +=3; | |
323 gCpuCaps.hasSSE=0; | |
324 return EXCEPTION_CONTINUE_EXECUTION; | |
325 } | |
326 return EXCEPTION_CONTINUE_SEARCH; | |
327 } | |
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328 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 329 |
26061 | 330 #ifdef __OS2__ |
331 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
332 PEXCEPTIONREGISTRATIONRECORD p2, | |
333 PCONTEXTRECORD p3, | |
334 PVOID p4 ) | |
335 { | |
336 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
337 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
338 | |
339 p3->ctx_RegEip += 3; | |
340 gCpuCaps.hasSSE = 0; | |
341 | |
342 return XCPT_CONTINUE_EXECUTION; | |
343 } | |
344 return XCPT_CONTINUE_SEARCH; | |
345 } | |
346 #endif | |
347 | |
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348 /* If we're running on a processor that can do SSE, let's see if we |
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349 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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350 * haven't been configured for a Pentium III but are running on one, |
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351 * and RedHat patched 2.2 kernels that have broken exception handling |
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352 * support for user space apps that do SSE. |
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353 */ |
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354 |
21848 | 355 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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356 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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357 #elif defined(__APPLE__) |
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358 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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359 #endif |
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360 |
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361 static void check_os_katmai_support( void ) |
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362 { |
14455 | 363 #ifdef ARCH_X86_64 |
364 gCpuCaps.hasSSE=1; | |
365 gCpuCaps.hasSSE2=1; | |
21848 | 366 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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367 int has_sse=0, ret; |
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368 size_t len=sizeof(has_sse); |
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369 |
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370 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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371 if (ret || !has_sse) |
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372 gCpuCaps.hasSSE=0; |
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373 |
12143 | 374 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
375 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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376 int has_sse, has_sse2, ret, mib[2]; |
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377 size_t varlen; |
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378 |
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379 mib[0] = CTL_MACHDEP; |
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380 mib[1] = CPU_SSE; |
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381 varlen = sizeof(has_sse); |
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382 |
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383 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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384 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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385 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
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diff
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386 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
8401
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Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
387 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
388 mib[1] = CPU_SSE2; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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389 varlen = sizeof(has_sse2); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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390 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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391 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
27605
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
reimar
parents:
27459
diff
changeset
|
392 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
reimar
parents:
27459
diff
changeset
|
393 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
394 #else |
8533
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
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395 gCpuCaps.hasSSE = 0; |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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diff
changeset
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396 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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diff
changeset
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397 #endif |
27727
48c1ae64255b
Replace preprocessor check for WIN32 with checks for __MINGW32__ and __CYGWIN__.
diego
parents:
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diff
changeset
|
398 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 399 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
400 if ( gCpuCaps.hasSSE ) { | |
401 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
402 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
403 __asm __volatile ("xorps %xmm0, %xmm0"); | |
404 SetUnhandledExceptionFilter(exc_fil); | |
27605
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
reimar
parents:
27459
diff
changeset
|
405 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
10440 | 406 } |
26061 | 407 #elif defined(__OS2__) |
408 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
409 if ( gCpuCaps.hasSSE ) { | |
410 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
411 DosSetExceptionHandler( &RegRec ); | |
412 __asm __volatile ("xorps %xmm0, %xmm0"); | |
413 DosUnsetExceptionHandler( &RegRec ); | |
27605
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
reimar
parents:
27459
diff
changeset
|
414 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
26061 | 415 } |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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416 #elif defined(__linux__) |
24439
680bc9411ecf
Do not check for X86_FXSR_MAGIC define, it is missing in newer
reimar
parents:
24438
diff
changeset
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417 #if defined(_POSIX_SOURCE) |
2268
72ff2179d396
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arpi
parents:
diff
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418 struct sigaction saved_sigill; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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419 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff
changeset
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420 /* Save the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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421 */ |
72ff2179d396
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arpi
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422 sigaction( SIGILL, NULL, &saved_sigill ); |
72ff2179d396
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arpi
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423 |
72ff2179d396
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arpi
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diff
changeset
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424 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
72ff2179d396
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arpi
parents:
diff
changeset
|
425 |
72ff2179d396
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arpi
parents:
diff
changeset
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426 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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427 * supports the extended FPU save and restore required for SSE. If |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
428 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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429 * doesn't support Streaming SIMD Exceptions, even if the processor |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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430 * does. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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431 */ |
72ff2179d396
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arpi
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diff
changeset
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432 if ( gCpuCaps.hasSSE ) { |
6134 | 433 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
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arpi
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434 |
2272 | 435 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
436 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
72ff2179d396
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arpi
parents:
diff
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|
437 |
27605
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
reimar
parents:
27459
diff
changeset
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438 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
2268
72ff2179d396
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arpi
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439 } |
72ff2179d396
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arpi
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diff
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|
440 |
72ff2179d396
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arpi
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changeset
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441 /* Restore the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
442 */ |
72ff2179d396
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arpi
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diff
changeset
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443 sigaction( SIGILL, &saved_sigill, NULL ); |
72ff2179d396
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arpi
parents:
diff
changeset
|
444 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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445 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff
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446 * safe to go ahead and hook out the SSE code throughout Mesa. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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447 */ |
27605
5b7f52928bcd
Simplify cpudetect OS-support detection code, e.g. using one mp_msg to print either yes or no instead of two.
reimar
parents:
27459
diff
changeset
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448 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
2268
72ff2179d396
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arpi
parents:
diff
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449 #else |
72ff2179d396
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arpi
parents:
diff
changeset
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450 /* We can't use POSIX signal handling to test the availability of |
72ff2179d396
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arpi
parents:
diff
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451 * SSE, so we disable it by default. |
72ff2179d396
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arpi
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diff
changeset
|
452 */ |
5937 | 453 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
2268
72ff2179d396
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arpi
parents:
diff
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|
454 gCpuCaps.hasSSE=0; |
24439
680bc9411ecf
Do not check for X86_FXSR_MAGIC define, it is missing in newer
reimar
parents:
24438
diff
changeset
|
455 #endif /* _POSIX_SOURCE */ |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
456 #else |
72ff2179d396
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arpi
parents:
diff
changeset
|
457 /* Do nothing on other platforms for now. |
72ff2179d396
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arpi
parents:
diff
changeset
|
458 */ |
6134 | 459 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
2268
72ff2179d396
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arpi
parents:
diff
changeset
|
460 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
461 #endif /* __linux__ */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
462 } |
20577 | 463 #else /* ARCH_X86 */ |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
464 |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
465 #ifdef __APPLE__ |
9003 | 466 #include <sys/sysctl.h> |
25338
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
467 #elif __AMIGAOS4__ |
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
468 /* nothing */ |
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
469 #else |
9003 | 470 #include <signal.h> |
471 #include <setjmp.h> | |
472 | |
473 static sigjmp_buf jmpbuf; | |
474 static volatile sig_atomic_t canjump = 0; | |
475 | |
476 static void sigill_handler (int sig) | |
477 { | |
478 if (!canjump) { | |
479 signal (sig, SIG_DFL); | |
480 raise (sig); | |
481 } | |
482 | |
483 canjump = 0; | |
484 siglongjmp (jmpbuf, 1); | |
485 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
486 #endif /* __APPLE__ */ |
9003 | 487 |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
488 void GetCpuCaps( CpuCaps *caps) |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
489 { |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
490 caps->cpuType=0; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
491 caps->cpuModel=0; |
3403 | 492 caps->cpuStepping=0; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
493 caps->hasMMX=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
494 caps->hasMMX2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
495 caps->has3DNow=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
496 caps->has3DNowExt=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
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diff
changeset
|
497 caps->hasSSE=0; |
3164eaa93396
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michael
parents:
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diff
changeset
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498 caps->hasSSE2=0; |
3164eaa93396
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michael
parents:
2417
diff
changeset
|
499 caps->isX86=0; |
9003 | 500 caps->hasAltiVec = 0; |
501 #ifdef HAVE_ALTIVEC | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
502 #ifdef __APPLE__ |
9003 | 503 /* |
504 rip-off from ffmpeg altivec detection code. | |
505 this code also appears on Apple's AltiVec pages. | |
506 */ | |
507 { | |
508 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
509 int has_vu = 0; | |
510 size_t len = sizeof(has_vu); | |
511 int err; | |
512 | |
513 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
514 | |
515 if (err == 0) | |
516 if (has_vu != 0) | |
517 caps->hasAltiVec = 1; | |
518 } | |
25339 | 519 #elif __AMIGAOS4__ |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
520 ULONG result = 0; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
521 |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
522 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
523 if (result == VECTORTYPE_ALTIVEC) |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
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changeset
|
524 caps->hasAltiVec = 1; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
525 #else |
9003 | 526 /* no Darwin, do it the brute-force way */ |
527 /* this is borrowed from the libmpeg2 library */ | |
528 { | |
529 signal (SIGILL, sigill_handler); | |
530 if (sigsetjmp (jmpbuf, 1)) { | |
531 signal (SIGILL, SIG_DFL); | |
532 } else { | |
533 canjump = 1; | |
534 | |
535 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 536 "vand %%v0, %%v0, %%v0" |
9003 | 537 : |
538 : "r" (-1)); | |
539 | |
540 signal (SIGILL, SIG_DFL); | |
541 caps->hasAltiVec = 1; | |
542 } | |
543 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
544 #endif /* __APPLE__ */ |
9324 | 545 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 546 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
547 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
548 #ifdef ARCH_IA64 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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10955
diff
changeset
|
549 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
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diff
changeset
|
550 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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10955
diff
changeset
|
551 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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10955
diff
changeset
|
552 #ifdef ARCH_SPARC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
553 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
554 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
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diff
changeset
|
555 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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10955
diff
changeset
|
556 #ifdef ARCH_ARMV4L |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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10955
diff
changeset
|
557 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
909093c314e9
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gabucino
parents:
10955
diff
changeset
|
558 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
559 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
560 #ifdef ARCH_POWERPC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
561 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
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562 #endif |
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563 |
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564 #ifdef ARCH_ALPHA |
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565 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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566 #endif |
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567 |
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568 #ifdef ARCH_SGI_MIPS |
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569 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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570 #endif |
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571 |
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572 #ifdef ARCH_PA_RISC |
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573 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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574 #endif |
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575 |
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576 #ifdef ARCH_S390 |
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577 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
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578 #endif |
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579 |
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580 #ifdef ARCH_S390X |
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581 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
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582 #endif |
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583 |
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584 #ifdef ARCH_VAX |
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585 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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586 #endif |
25340 | 587 |
588 #ifdef ARCH_XTENSA | |
589 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" ); | |
590 #endif | |
3146
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591 } |
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592 #endif /* !ARCH_X86 */ |