annotate cpudetect.c @ 9122:5ba896a38d75

The two attached patches *should* allow for proper compilation of the AltiVec stuff on both Darwin and non-Darwin system. They've only been tested for compilation on Debian using Debian's gcc-3.2. Romain Dolbeau <dolbeau@irisa.fr>
author arpi
date Mon, 27 Jan 2003 21:47:25 +0000
parents c428933c7e54
children 300649f96e22
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1 #include "config.h"
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2 #include "cpudetect.h"
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3 #include "mp_msg.h"
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4
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5 CpuCaps gCpuCaps;
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6
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7 #ifdef HAVE_MALLOC_H
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8 #include <malloc.h>
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9 #endif
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10 #include <stdlib.h>
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11
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12 #ifdef ARCH_X86
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13
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14 #include <stdio.h>
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15 #include <string.h>
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16
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17 #ifdef __NetBSD__
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18 #include <sys/param.h>
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19 #include <sys/sysctl.h>
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20 #include <machine/cpu.h>
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21 #endif
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22
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23 #ifdef __FreeBSD__
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24 #include <sys/types.h>
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25 #include <sys/sysctl.h>
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26 #endif
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27
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28 #ifdef __linux__
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29 #include <signal.h>
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30 #endif
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31
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32 //#define X86_FXSR_MAGIC
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33 /* Thanks to the FreeBSD project for some of this cpuid code, and
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34 * help understanding how to use it. Thanks to the Mesa
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35 * team for SSE support detection and more cpu detect code.
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36 */
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37
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38 /* I believe this code works. However, it has only been used on a PII and PIII */
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39
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40 static void check_os_katmai_support( void );
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41
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42 #if 1
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43 // return TRUE if cpuid supported
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44 static int has_cpuid()
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45 {
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46 int a, c;
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47
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48 // code from libavcodec:
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49 __asm__ __volatile__ (
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50 /* See if CPUID instruction is supported ... */
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51 /* ... Get copies of EFLAGS into eax and ecx */
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52 "pushf\n\t"
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53 "popl %0\n\t"
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54 "movl %0, %1\n\t"
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55
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56 /* ... Toggle the ID bit in one copy and store */
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57 /* to the EFLAGS reg */
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58 "xorl $0x200000, %0\n\t"
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59 "push %0\n\t"
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60 "popf\n\t"
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61
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62 /* ... Get the (hopefully modified) EFLAGS */
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63 "pushf\n\t"
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64 "popl %0\n\t"
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65 : "=a" (a), "=c" (c)
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66 :
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67 : "cc"
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68 );
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69
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70 return (a!=c);
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71 }
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72 #endif
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73
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74 static void
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75 do_cpuid(unsigned int ax, unsigned int *p)
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76 {
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77 #if 0
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78 __asm __volatile(
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79 "cpuid;"
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80 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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81 : "0" (ax)
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82 );
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83 #else
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84 // code from libavcodec:
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85 __asm __volatile
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86 ("movl %%ebx, %%esi\n\t"
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87 "cpuid\n\t"
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88 "xchgl %%ebx, %%esi"
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89 : "=a" (p[0]), "=S" (p[1]),
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90 "=c" (p[2]), "=d" (p[3])
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91 : "0" (ax));
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92 #endif
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93
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94 }
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95
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96 void GetCpuCaps( CpuCaps *caps)
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97 {
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98 unsigned int regs[4];
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99 unsigned int regs2[4];
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100
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101 memset(caps, 0, sizeof(*caps));
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102 caps->isX86=1;
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103 caps->cl_size=32; /* default */
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104 if (!has_cpuid()) {
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105 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n");
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106 return;
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107 }
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108 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name
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109 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n",
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110 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]);
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111 if (regs[0]>=0x00000001)
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112 {
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113 char *tmpstr;
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114 unsigned cl_size;
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115
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116 do_cpuid(0x00000001, regs2);
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117
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118 tmpstr=GetCpuFriendlyName(regs, regs2);
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119 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr);
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120 free(tmpstr);
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121
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122 caps->cpuType=(regs2[0] >> 8)&0xf;
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123 if(caps->cpuType==0xf){
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124 // use extended family (P4, IA64)
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125 caps->cpuType=8+((regs2[0]>>20)&255);
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126 }
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127 caps->cpuStepping=regs2[0] & 0xf;
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128 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n",
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129 caps->cpuType, caps->cpuStepping);
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130
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131 // general feature flags:
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132 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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133 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000
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134 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000
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135 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too
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136 cl_size = ((regs2[1] >> 8) & 0xFF)*8;
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137 if(cl_size) caps->cl_size = cl_size;
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138 }
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139 do_cpuid(0x80000000, regs);
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140 if (regs[0]>=0x80000001) {
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141 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF);
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142 do_cpuid(0x80000001, regs2);
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143 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000
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144 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000
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145 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000
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146 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30;
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147 }
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148 if(regs[0]>=0x80000006)
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149 {
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150 do_cpuid(0x80000006, regs2);
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151 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF);
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152 caps->cl_size = regs2[2] & 0xFF;
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153 }
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154 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size);
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155 #if 0
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156 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n",
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157 gCpuCaps.hasMMX,
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158 gCpuCaps.hasMMX2,
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159 gCpuCaps.hasSSE,
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160 gCpuCaps.hasSSE2,
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161 gCpuCaps.has3DNow,
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162 gCpuCaps.has3DNowExt );
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163 #endif
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164
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165 /* FIXME: Does SSE2 need more OS support, too? */
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166 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__)
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167 if (caps->hasSSE)
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168 check_os_katmai_support();
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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169 if (!caps->hasSSE)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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170 caps->hasSSE2 = 0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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171 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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172 caps->hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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173 caps->hasSSE2 = 0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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174 #endif
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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175 // caps->has3DNow=1;
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176 // caps->hasMMX2 = 0;
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177 // caps->hasMMX = 0;
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178
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35ed5387b804 dont ignore --disable-mmx, ...
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179 #ifndef HAVE_MMX
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180 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n");
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181 caps->hasMMX=0;
35ed5387b804 dont ignore --disable-mmx, ...
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182 #endif
35ed5387b804 dont ignore --disable-mmx, ...
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183 #ifndef HAVE_MMX2
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184 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n");
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185 caps->hasMMX2=0;
35ed5387b804 dont ignore --disable-mmx, ...
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186 #endif
35ed5387b804 dont ignore --disable-mmx, ...
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187 #ifndef HAVE_SSE
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188 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n");
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189 caps->hasSSE=0;
35ed5387b804 dont ignore --disable-mmx, ...
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diff changeset
190 #endif
35ed5387b804 dont ignore --disable-mmx, ...
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191 #ifndef HAVE_SSE2
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192 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n");
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193 caps->hasSSE2=0;
35ed5387b804 dont ignore --disable-mmx, ...
michael
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diff changeset
194 #endif
35ed5387b804 dont ignore --disable-mmx, ...
michael
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diff changeset
195 #ifndef HAVE_3DNOW
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196 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n");
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197 caps->has3DNow=0;
35ed5387b804 dont ignore --disable-mmx, ...
michael
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198 #endif
35ed5387b804 dont ignore --disable-mmx, ...
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199 #ifndef HAVE_3DNOWEX
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200 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n");
4829
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201 caps->has3DNowExt=0;
35ed5387b804 dont ignore --disable-mmx, ...
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diff changeset
202 #endif
2268
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203 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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204
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205
b4c4c832cce7 Detect and show cpu name.
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206 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */
b4c4c832cce7 Detect and show cpu name.
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207 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */
b4c4c832cce7 Detect and show cpu name.
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208 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */
b4c4c832cce7 Detect and show cpu name.
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209 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */
b4c4c832cce7 Detect and show cpu name.
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210 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */
b4c4c832cce7 Detect and show cpu name.
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211 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */
b4c4c832cce7 Detect and show cpu name.
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212
b4c4c832cce7 Detect and show cpu name.
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213 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){
b4c4c832cce7 Detect and show cpu name.
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214 #include "cputable.h" /* get cpuname and cpuvendors */
b4c4c832cce7 Detect and show cpu name.
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215 char vendor[17];
2303
456e22bfb147 returns a malloc()'ed string instead of an auto char[]
pl
parents: 2301
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216 char *retname;
2301
b4c4c832cce7 Detect and show cpu name.
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diff changeset
217 int i;
b4c4c832cce7 Detect and show cpu name.
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218
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parents: 2303
diff changeset
219 if (NULL==(retname=(char*)malloc(256))) {
5937
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220 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n");
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456e22bfb147 returns a malloc()'ed string instead of an auto char[]
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parents: 2301
diff changeset
221 exit(1);
456e22bfb147 returns a malloc()'ed string instead of an auto char[]
pl
parents: 2301
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222 }
456e22bfb147 returns a malloc()'ed string instead of an auto char[]
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parents: 2301
diff changeset
223
3837
6659db99f200 warning fix
pl
parents: 3700
diff changeset
224 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2));
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
225
2301
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diff changeset
226 for(i=0; i<MAX_VENDORS; i++){
b4c4c832cce7 Detect and show cpu name.
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diff changeset
227 if(!strcmp(cpuvendors[i].string,vendor)){
b4c4c832cce7 Detect and show cpu name.
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228 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){
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456e22bfb147 returns a malloc()'ed string instead of an auto char[]
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parents: 2301
diff changeset
229 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]);
2301
b4c4c832cce7 Detect and show cpu name.
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diff changeset
230 } else {
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parents: 2301
diff changeset
231 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY);
5937
4b18bf35f153 printf to mp_msg
albeu
parents: 4829
diff changeset
232 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name);
4b18bf35f153 printf to mp_msg
albeu
parents: 4829
diff changeset
233 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string);
4b18bf35f153 printf to mp_msg
albeu
parents: 4829
diff changeset
234 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE);
4b18bf35f153 printf to mp_msg
albeu
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diff changeset
235 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY);
4b18bf35f153 printf to mp_msg
albeu
parents: 4829
diff changeset
236 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL);
4b18bf35f153 printf to mp_msg
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parents: 4829
diff changeset
237 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING);
4b18bf35f153 printf to mp_msg
albeu
parents: 4829
diff changeset
238 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name"
2301
b4c4c832cce7 Detect and show cpu name.
atmos4
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diff changeset
239 "to the MPlayer-Developers, so we can add it to the list!\n");
b4c4c832cce7 Detect and show cpu name.
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240 }
b4c4c832cce7 Detect and show cpu name.
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diff changeset
241 }
b4c4c832cce7 Detect and show cpu name.
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diff changeset
242 }
b4c4c832cce7 Detect and show cpu name.
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243
b4c4c832cce7 Detect and show cpu name.
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244 //printf("Detected CPU: %s\n", retname);
b4c4c832cce7 Detect and show cpu name.
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diff changeset
245 return retname;
b4c4c832cce7 Detect and show cpu name.
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diff changeset
246 }
b4c4c832cce7 Detect and show cpu name.
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247
b4c4c832cce7 Detect and show cpu name.
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diff changeset
248 #undef CPUID_EXTFAMILY
b4c4c832cce7 Detect and show cpu name.
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diff changeset
249 #undef CPUID_EXTMODEL
b4c4c832cce7 Detect and show cpu name.
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diff changeset
250 #undef CPUID_TYPE
b4c4c832cce7 Detect and show cpu name.
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diff changeset
251 #undef CPUID_FAMILY
b4c4c832cce7 Detect and show cpu name.
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diff changeset
252 #undef CPUID_MODEL
b4c4c832cce7 Detect and show cpu name.
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diff changeset
253 #undef CPUID_STEPPING
b4c4c832cce7 Detect and show cpu name.
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254
b4c4c832cce7 Detect and show cpu name.
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255
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
256 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
257 static void sigill_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
258 {
6134
2f59920361ff cosmetics on CPU detection messages
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259 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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diff changeset
260
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
261 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1"
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
262 * instructions are 3 bytes long. We must increment the instruction
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
263 * pointer manually to avoid repeated execution of the offending
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
264 * instruction.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
265 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
266 * If the SIGILL is caused by a divide-by-zero when unmasked
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
267 * exceptions aren't supported, the SIMD FPU status and control
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
268 * word will be restored at the end of the test, so we don't need
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
269 * to worry about doing it here. Besides, we may not be able to...
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
270 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
271 sc.eip += 3;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
272
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
273 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
274 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
275
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
276 static void sigfpe_handler_sse( int signal, struct sigcontext sc )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
277 {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
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diff changeset
278 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
2268
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279
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
280 if ( sc.fpstate->magic != 0xffff ) {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
281 /* Our signal context has the extended FPU state, so reset the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
282 * divide-by-zero exception mask and clear the divide-by-zero
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
283 * exception bit.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
284 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
285 sc.fpstate->mxcsr |= 0x00000200;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
286 sc.fpstate->mxcsr &= 0xfffffffb;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
287 } else {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
288 /* If we ever get here, we're completely hosed.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
289 */
6134
2f59920361ff cosmetics on CPU detection messages
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290 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
2f59920361ff cosmetics on CPU detection messages
arpi
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291 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
292 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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293 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff changeset
294 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
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arpi
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295
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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296 /* If we're running on a processor that can do SSE, let's see if we
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
297 * are allowed to or not. This will catch 2.4.0 or later kernels that
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
298 * haven't been configured for a Pentium III but are running on one,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
299 * and RedHat patched 2.2 kernels that have broken exception handling
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
300 * support for user space apps that do SSE.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
301 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
302 static void check_os_katmai_support( void )
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
303 {
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
304 #if defined(__FreeBSD__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
305 int has_sse=0, ret;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
306 size_t len=sizeof(has_sse);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
307
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
308 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0);
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
309 if (ret || !has_sse)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
310 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
311
8401
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
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diff changeset
312 #elif defined(__NetBSD__)
8533
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
313 #if __NetBSD_Version__ >= 105250000
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
314 int has_sse, has_sse2, ret, mib[2];
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
315 size_t varlen;
8401
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
316
8533
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
317 mib[0] = CTL_MACHDEP;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
318 mib[1] = CPU_SSE;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
319 varlen = sizeof(has_sse);
8401
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
320
8533
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
321 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
322 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0);
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
323 if (ret < 0 || !has_sse) {
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
324 gCpuCaps.hasSSE=0;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
325 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
326 } else {
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
327 gCpuCaps.hasSSE=1;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
328 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
329 }
8401
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
330
8533
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
331 mib[1] = CPU_SSE2;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
332 varlen = sizeof(has_sse2);
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
333 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " );
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
334 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0);
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
335 if (ret < 0 || !has_sse2) {
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
336 gCpuCaps.hasSSE2=0;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
337 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
338 } else {
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
339 gCpuCaps.hasSSE2=1;
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
340 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" );
8401
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
341 }
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
342 #else
8533
9b73b801af55 Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents: 8401
diff changeset
343 gCpuCaps.hasSSE = 0;
8401
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
344 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" );
1b2fc92980d9 Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents: 8123
diff changeset
345 #endif
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
346 #elif defined(__linux__)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
347 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC)
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
348 struct sigaction saved_sigill;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
349 struct sigaction saved_sigfpe;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
350
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
351 /* Save the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
352 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
353 sigaction( SIGILL, NULL, &saved_sigill );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
354 sigaction( SIGFPE, NULL, &saved_sigfpe );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
355
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
356 signal( SIGILL, (void (*)(int))sigill_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
357 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
358
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
359 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
360 * supports the extended FPU save and restore required for SSE. If
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
361 * we execute an SSE instruction on a PIII and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
362 * doesn't support Streaming SIMD Exceptions, even if the processor
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
363 * does.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
364 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
365 if ( gCpuCaps.hasSSE ) {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
366 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
367
2272
c26a9eff0993 cpu detection fixed
arpi
parents: 2268
diff changeset
368 // __asm __volatile ("xorps %%xmm0, %%xmm0");
c26a9eff0993 cpu detection fixed
arpi
parents: 2268
diff changeset
369 __asm __volatile ("xorps %xmm0, %xmm0");
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
370
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
371 if ( gCpuCaps.hasSSE ) {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
372 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
373 } else {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
374 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
375 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
376 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
377
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
378 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
379 * it supports unmasked SIMD FPU exceptions. If we unmask the
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
380 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
381 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
382 * as expected, we're okay but we need to clean up after it.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
383 *
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
384 * Are we being too stringent in our requirement that the OS support
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
385 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
386 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
387 * doesn't even support them. We at least know the user-space SSE
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
388 * support is good in kernels that do support unmasked exceptions,
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
389 * and therefore to be safe I'm going to leave this test in here.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
390 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
391 if ( gCpuCaps.hasSSE ) {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
392 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
393
2272
c26a9eff0993 cpu detection fixed
arpi
parents: 2268
diff changeset
394 // test_os_katmai_exception_support();
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
395
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
396 if ( gCpuCaps.hasSSE ) {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
397 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
398 } else {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
399 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
400 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
401 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
402
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
403 /* Restore the original signal handlers.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
404 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
405 sigaction( SIGILL, &saved_sigill, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
406 sigaction( SIGFPE, &saved_sigfpe, NULL );
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
407
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
408 /* If we've gotten to here and the XMM CPUID bit is still set, we're
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
409 * safe to go ahead and hook out the SSE code throughout Mesa.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
410 */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
411 if ( gCpuCaps.hasSSE ) {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
412 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
413 } else {
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
414 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
415 }
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
416 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
417 /* We can't use POSIX signal handling to test the availability of
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
418 * SSE, so we disable it by default.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
419 */
5937
4b18bf35f153 printf to mp_msg
albeu
parents: 4829
diff changeset
420 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
421 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
422 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
423 #else
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
424 /* Do nothing on other platforms for now.
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
425 */
6134
2f59920361ff cosmetics on CPU detection messages
arpi
parents: 5937
diff changeset
426 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" );
2268
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
427 gCpuCaps.hasSSE=0;
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
428 #endif /* __linux__ */
72ff2179d396 cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff changeset
429 }
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
430 #else /* ARCH_X86 */
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
431
9003
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
432 #ifdef SYS_DARWIN
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
433 #include <sys/sysctl.h>
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
434 #else
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
435 #include <signal.h>
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
436 #include <setjmp.h>
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
437
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
438 static sigjmp_buf jmpbuf;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
439 static volatile sig_atomic_t canjump = 0;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
440
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
441 static void sigill_handler (int sig)
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
442 {
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
443 if (!canjump) {
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
444 signal (sig, SIG_DFL);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
445 raise (sig);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
446 }
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
447
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
448 canjump = 0;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
449 siglongjmp (jmpbuf, 1);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
450 }
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
451 #endif
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
parents: 8860
diff changeset
452
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
453 void GetCpuCaps( CpuCaps *caps)
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
454 {
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
455 caps->cpuType=0;
3403
c4ca766a2d05 added cpuStepping to CpuCaps struct (needed win32.c)
alex
parents: 3146
diff changeset
456 caps->cpuStepping=0;
3146
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
457 caps->hasMMX=0;
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents: 2417
diff changeset
458 caps->hasMMX2=0;
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459 caps->has3DNow=0;
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460 caps->has3DNowExt=0;
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461 caps->hasSSE=0;
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462 caps->hasSSE2=0;
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parents: 2417
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463 caps->isX86=0;
9003
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
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464 caps->hasAltiVec = 0;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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465 #ifdef HAVE_ALTIVEC
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466 #ifdef SYS_DARWIN
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467 /*
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
arpi
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468 rip-off from ffmpeg altivec detection code.
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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469 this code also appears on Apple's AltiVec pages.
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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470 */
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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471 {
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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472 int sels[2] = {CTL_HW, HW_VECTORUNIT};
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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473 int has_vu = 0;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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474 size_t len = sizeof(has_vu);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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475 int err;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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476
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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477 err = sysctl(sels, 2, &has_vu, &len, NULL, 0);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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478
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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479 if (err == 0)
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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480 if (has_vu != 0)
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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481 caps->hasAltiVec = 1;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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482 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not "));
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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483 }
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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484 #else /* SYS_DARWIN */
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485 /* no Darwin, do it the brute-force way */
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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486 /* this is borrowed from the libmpeg2 library */
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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487 {
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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488 signal (SIGILL, sigill_handler);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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489 if (sigsetjmp (jmpbuf, 1)) {
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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490 signal (SIGILL, SIG_DFL);
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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491 } else {
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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492 canjump = 1;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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493
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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494 asm volatile ("mtspr 256, %0\n\t"
9122
5ba896a38d75 The two attached patches *should* allow for proper
arpi
parents: 9003
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495 "vand %%v0, %%v0, %%v0"
9003
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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496 :
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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497 : "r" (-1));
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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498
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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499 signal (SIGILL, SIG_DFL);
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500 caps->hasAltiVec = 1;
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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501 }
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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502 }
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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503 #endif /* SYS_DARWIN */
c428933c7e54 AltiVec detection code ("borrowed" from FFmpeg and
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504 #endif /* HAVE_ALTIVEC */
3146
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parents: 2417
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505 }
3164eaa93396 non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
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parents: 2417
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506 #endif /* !ARCH_X86 */