Mercurial > mplayer.hg
annotate cpudetect.c @ 12181:12ddc64011fe
Add license, remove bogus comment as told by Reza Jelveh, the author.
author | diego |
---|---|
date | Mon, 12 Apr 2004 23:58:06 +0000 |
parents | da228f2485d9 |
children | c315d377634f |
rev | line source |
---|---|
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
1 #include "config.h" |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
4 |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
5 CpuCaps gCpuCaps; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
12 #ifdef ARCH_X86 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
13 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
14 #include <stdio.h> |
8123
9fc45fe0d444
*HUGE* set of compiler warning fixes, unused variables removal
arpi
parents:
6135
diff
changeset
|
15 #include <string.h> |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
16 #include "osdep/timer.h" |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
17 |
12143 | 18 #if defined (__NetBSD__) || defined(__OpenBSD__) |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
19 #include <sys/param.h> |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
20 #include <sys/sysctl.h> |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
21 #include <machine/cpu.h> |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
22 #endif |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
23 |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
24 #ifdef __FreeBSD__ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
25 #include <sys/types.h> |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
26 #include <sys/sysctl.h> |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
27 #endif |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
28 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
29 #ifdef __linux__ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
30 #include <signal.h> |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
31 #endif |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
32 |
10440 | 33 #ifdef WIN32 |
34 #include <windows.h> | |
35 #endif | |
36 | |
2272 | 37 //#define X86_FXSR_MAGIC |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
38 /* Thanks to the FreeBSD project for some of this cpuid code, and |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
39 * help understanding how to use it. Thanks to the Mesa |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
40 * team for SSE support detection and more cpu detect code. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
41 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
42 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
43 /* I believe this code works. However, it has only been used on a PII and PIII */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
44 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
45 static void check_os_katmai_support( void ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
46 |
2272 | 47 #if 1 |
48 // return TRUE if cpuid supported | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
49 static int has_cpuid() |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
50 { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
51 int a, c; |
2272 | 52 |
53 // code from libavcodec: | |
54 __asm__ __volatile__ ( | |
55 /* See if CPUID instruction is supported ... */ | |
56 /* ... Get copies of EFLAGS into eax and ecx */ | |
57 "pushf\n\t" | |
58 "popl %0\n\t" | |
59 "movl %0, %1\n\t" | |
60 | |
61 /* ... Toggle the ID bit in one copy and store */ | |
62 /* to the EFLAGS reg */ | |
63 "xorl $0x200000, %0\n\t" | |
64 "push %0\n\t" | |
65 "popf\n\t" | |
66 | |
67 /* ... Get the (hopefully modified) EFLAGS */ | |
68 "pushf\n\t" | |
69 "popl %0\n\t" | |
70 : "=a" (a), "=c" (c) | |
71 : | |
72 : "cc" | |
73 ); | |
74 | |
75 return (a!=c); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
76 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
77 #endif |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
78 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
79 static void |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
80 do_cpuid(unsigned int ax, unsigned int *p) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
81 { |
2272 | 82 #if 0 |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
83 __asm __volatile( |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
84 "cpuid;" |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
85 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
86 : "0" (ax) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
87 ); |
2272 | 88 #else |
89 // code from libavcodec: | |
90 __asm __volatile | |
91 ("movl %%ebx, %%esi\n\t" | |
92 "cpuid\n\t" | |
93 "xchgl %%ebx, %%esi" | |
3403 | 94 : "=a" (p[0]), "=S" (p[1]), |
2272 | 95 "=c" (p[2]), "=d" (p[3]) |
96 : "0" (ax)); | |
97 #endif | |
98 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
99 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
100 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
101 void GetCpuCaps( CpuCaps *caps) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
102 { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
103 unsigned int regs[4]; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
104 unsigned int regs2[4]; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
105 |
8860 | 106 memset(caps, 0, sizeof(*caps)); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
107 caps->isX86=1; |
8860 | 108 caps->cl_size=32; /* default */ |
2288 | 109 if (!has_cpuid()) { |
6134 | 110 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 111 return; |
112 } | |
113 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 114 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 115 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 116 if (regs[0]>=0x00000001) |
2280 | 117 { |
2303 | 118 char *tmpstr; |
8860 | 119 unsigned cl_size; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
120 |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
121 do_cpuid(0x00000001, regs2); |
2301 | 122 |
2288 | 123 caps->cpuType=(regs2[0] >> 8)&0xf; |
124 if(caps->cpuType==0xf){ | |
125 // use extended family (P4, IA64) | |
126 caps->cpuType=8+((regs2[0]>>20)&255); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
127 } |
3403 | 128 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 129 |
130 // general feature flags: | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
131 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 132 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
133 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
134 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 135 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 136 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
137 if(cl_size) caps->cl_size = cl_size; | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
138 |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
139 tmpstr=GetCpuFriendlyName(regs, regs2); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
140 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
141 free(tmpstr); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
142 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
143 caps->cpuType, caps->cpuStepping); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
144 |
2288 | 145 } |
146 do_cpuid(0x80000000, regs); | |
147 if (regs[0]>=0x80000001) { | |
6134 | 148 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 149 do_cpuid(0x80000001, regs2); |
3840 | 150 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
151 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 152 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
153 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
154 } | |
8860 | 155 if(regs[0]>=0x80000006) |
156 { | |
157 do_cpuid(0x80000006, regs2); | |
158 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
159 caps->cl_size = regs2[2] & 0xFF; | |
160 } | |
161 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 162 #if 0 |
5937 | 163 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 164 gCpuCaps.hasMMX, |
165 gCpuCaps.hasMMX2, | |
166 gCpuCaps.hasSSE, | |
167 gCpuCaps.hasSSE2, | |
168 gCpuCaps.has3DNow, | |
169 gCpuCaps.has3DNowExt ); | |
170 #endif | |
171 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
172 /* FIXME: Does SSE2 need more OS support, too? */ |
12143 | 173 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__MINGW32__) || defined(__OpenBSD__) |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
174 if (caps->hasSSE) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
175 check_os_katmai_support(); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
176 if (!caps->hasSSE) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
177 caps->hasSSE2 = 0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
178 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
179 caps->hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
180 caps->hasSSE2 = 0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
181 #endif |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
182 // caps->has3DNow=1; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
183 // caps->hasMMX2 = 0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
184 // caps->hasMMX = 0; |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
185 |
4829 | 186 #ifndef HAVE_MMX |
6134 | 187 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 188 caps->hasMMX=0; |
189 #endif | |
190 #ifndef HAVE_MMX2 | |
6134 | 191 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 192 caps->hasMMX2=0; |
193 #endif | |
194 #ifndef HAVE_SSE | |
6134 | 195 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 196 caps->hasSSE=0; |
197 #endif | |
198 #ifndef HAVE_SSE2 | |
6134 | 199 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 200 caps->hasSSE2=0; |
201 #endif | |
202 #ifndef HAVE_3DNOW | |
6134 | 203 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 204 caps->has3DNow=0; |
205 #endif | |
206 #ifndef HAVE_3DNOWEX | |
6134 | 207 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 208 caps->has3DNowExt=0; |
209 #endif | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
210 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
211 |
2301 | 212 |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
213 static inline unsigned long long int rdtsc( void ) |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
214 { |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
215 unsigned long long int retval; |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
216 __asm __volatile ("rdtsc":"=A"(retval)::"memory"); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
217 return retval; |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
218 } |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
219 |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
220 /* Returns CPU clock in khz */ |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
221 static unsigned int GetCpuSpeed(void) |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
222 { |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
223 unsigned long long int tscstart, tscstop; |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
224 unsigned int start, stop; |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
225 |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
226 tscstart = rdtsc(); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
227 start = GetTimer(); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
228 usec_sleep(50000); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
229 stop = GetTimer(); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
230 tscstop = rdtsc(); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
231 |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
232 return((tscstop-tscstart)/((stop-start)/1000.0)); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
233 } |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
234 |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
235 |
2301 | 236 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ |
237 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
238 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
239 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
240 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
241 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
242 | |
243 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
244 #include "cputable.h" /* get cpuname and cpuvendors */ | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
245 char vendor[17], cpuspeed[16]; |
2303 | 246 char *retname; |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
247 int i=0; |
2301 | 248 |
2417 | 249 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 250 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 251 exit(1); |
252 } | |
253 | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
254 /* Measure CPU speed */ |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
255 if (gCpuCaps.hasTSC && (i = GetCpuSpeed()) > 0) { |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
256 if (i < 1000000) { |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
257 i += 50; /* for rounding */ |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
258 snprintf(cpuspeed,15, " %d.%d MHz", i/1000, (i/100)%10); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
259 } else { |
10955
6d1388df591b
more exact cpu mhz detect for fats cpus (remove rounding)
atmos4
parents:
10885
diff
changeset
|
260 //i += 500; /* for rounding */ |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
261 snprintf(cpuspeed,15, " %d MHz", i/1000); |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
262 } |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
263 } else { /* No TSC Support */ |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
264 cpuspeed[0]='\0'; |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
265 } |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
266 |
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
267 |
3837 | 268 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
269 |
2301 | 270 for(i=0; i<MAX_VENDORS; i++){ |
271 if(!strcmp(cpuvendors[i].string,vendor)){ | |
272 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
273 snprintf(retname,255,"%s %s%s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL],cpuspeed); |
2301 | 274 } else { |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
275 snprintf(retname,255,"unknown %s %d. Generation CPU%s",cpuvendors[i].name,CPUID_FAMILY,cpuspeed); |
5937 | 276 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
277 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
278 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
279 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
280 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
281 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
282 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 283 "to the MPlayer-Developers, so we can add it to the list!\n"); |
284 } | |
285 } | |
286 } | |
287 | |
288 //printf("Detected CPU: %s\n", retname); | |
289 return retname; | |
290 } | |
291 | |
292 #undef CPUID_EXTFAMILY | |
293 #undef CPUID_EXTMODEL | |
294 #undef CPUID_TYPE | |
295 #undef CPUID_FAMILY | |
296 #undef CPUID_MODEL | |
297 #undef CPUID_STEPPING | |
298 | |
299 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
300 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
301 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
302 { |
6134 | 303 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
304 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
305 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
306 * instructions are 3 bytes long. We must increment the instruction |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
307 * pointer manually to avoid repeated execution of the offending |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
308 * instruction. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
309 * |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
310 * If the SIGILL is caused by a divide-by-zero when unmasked |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
311 * exceptions aren't supported, the SIMD FPU status and control |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
312 * word will be restored at the end of the test, so we don't need |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
313 * to worry about doing it here. Besides, we may not be able to... |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
314 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
315 sc.eip += 3; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
316 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
317 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
318 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
319 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
320 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
321 { |
6134 | 322 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
323 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
324 if ( sc.fpstate->magic != 0xffff ) { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
325 /* Our signal context has the extended FPU state, so reset the |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
326 * divide-by-zero exception mask and clear the divide-by-zero |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
327 * exception bit. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
328 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
329 sc.fpstate->mxcsr |= 0x00000200; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
330 sc.fpstate->mxcsr &= 0xfffffffb; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
331 } else { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
332 /* If we ever get here, we're completely hosed. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
333 */ |
6134 | 334 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
335 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
336 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
337 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
338 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
339 |
10440 | 340 #ifdef WIN32 |
341 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
342 { | |
343 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
344 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
345 ep->ContextRecord->Eip +=3; | |
346 gCpuCaps.hasSSE=0; | |
347 return EXCEPTION_CONTINUE_EXECUTION; | |
348 } | |
349 return EXCEPTION_CONTINUE_SEARCH; | |
350 } | |
351 #endif /* WIN32 */ | |
352 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
353 /* If we're running on a processor that can do SSE, let's see if we |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
354 * are allowed to or not. This will catch 2.4.0 or later kernels that |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
355 * haven't been configured for a Pentium III but are running on one, |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
356 * and RedHat patched 2.2 kernels that have broken exception handling |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
357 * support for user space apps that do SSE. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
358 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
359 static void check_os_katmai_support( void ) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
360 { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
361 #if defined(__FreeBSD__) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
362 int has_sse=0, ret; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
363 size_t len=sizeof(has_sse); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
364 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
365 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
366 if (ret || !has_sse) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
367 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
368 |
12143 | 369 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
370 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
371 int has_sse, has_sse2, ret, mib[2]; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
372 size_t varlen; |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
373 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
374 mib[0] = CTL_MACHDEP; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
375 mib[1] = CPU_SSE; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
376 varlen = sizeof(has_sse); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
377 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
378 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
379 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
380 if (ret < 0 || !has_sse) { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
381 gCpuCaps.hasSSE=0; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
382 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
383 } else { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
384 gCpuCaps.hasSSE=1; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
385 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
386 } |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
387 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
388 mib[1] = CPU_SSE2; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
389 varlen = sizeof(has_sse2); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
390 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
391 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
392 if (ret < 0 || !has_sse2) { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
393 gCpuCaps.hasSSE2=0; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
394 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
395 } else { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
396 gCpuCaps.hasSSE2=1; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
397 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
398 } |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
399 #else |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
400 gCpuCaps.hasSSE = 0; |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
401 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
402 #endif |
10440 | 403 #elif defined(WIN32) |
404 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
405 if ( gCpuCaps.hasSSE ) { | |
406 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
407 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
408 __asm __volatile ("xorps %xmm0, %xmm0"); | |
409 SetUnhandledExceptionFilter(exc_fil); | |
410 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
411 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
412 } | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
413 #elif defined(__linux__) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
414 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
415 struct sigaction saved_sigill; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
416 struct sigaction saved_sigfpe; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
417 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
418 /* Save the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
419 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
420 sigaction( SIGILL, NULL, &saved_sigill ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
421 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
422 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
423 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
424 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
425 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
426 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
427 * supports the extended FPU save and restore required for SSE. If |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
428 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
429 * doesn't support Streaming SIMD Exceptions, even if the processor |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
430 * does. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
431 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
432 if ( gCpuCaps.hasSSE ) { |
6134 | 433 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
434 |
2272 | 435 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
436 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
437 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
438 if ( gCpuCaps.hasSSE ) { |
6134 | 439 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
440 } else { |
6134 | 441 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
442 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
443 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
444 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
445 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
446 * it supports unmasked SIMD FPU exceptions. If we unmask the |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
447 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
448 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
449 * as expected, we're okay but we need to clean up after it. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
450 * |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
451 * Are we being too stringent in our requirement that the OS support |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
452 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
453 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
454 * doesn't even support them. We at least know the user-space SSE |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
455 * support is good in kernels that do support unmasked exceptions, |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
456 * and therefore to be safe I'm going to leave this test in here. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
457 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
458 if ( gCpuCaps.hasSSE ) { |
6134 | 459 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
460 |
2272 | 461 // test_os_katmai_exception_support(); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
462 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
463 if ( gCpuCaps.hasSSE ) { |
6134 | 464 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
465 } else { |
6134 | 466 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
467 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
468 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
469 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
470 /* Restore the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
471 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
472 sigaction( SIGILL, &saved_sigill, NULL ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
473 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
474 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
475 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
476 * safe to go ahead and hook out the SSE code throughout Mesa. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
477 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
478 if ( gCpuCaps.hasSSE ) { |
6134 | 479 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
480 } else { |
6134 | 481 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
482 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
483 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
484 /* We can't use POSIX signal handling to test the availability of |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
485 * SSE, so we disable it by default. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
486 */ |
5937 | 487 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
488 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
489 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
490 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
491 /* Do nothing on other platforms for now. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
492 */ |
6134 | 493 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
494 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
495 #endif /* __linux__ */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
496 } |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
497 #else /* ARCH_X86 */ |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
498 |
9003 | 499 #ifdef SYS_DARWIN |
500 #include <sys/sysctl.h> | |
501 #else | |
502 #include <signal.h> | |
503 #include <setjmp.h> | |
504 | |
505 static sigjmp_buf jmpbuf; | |
506 static volatile sig_atomic_t canjump = 0; | |
507 | |
508 static void sigill_handler (int sig) | |
509 { | |
510 if (!canjump) { | |
511 signal (sig, SIG_DFL); | |
512 raise (sig); | |
513 } | |
514 | |
515 canjump = 0; | |
516 siglongjmp (jmpbuf, 1); | |
517 } | |
518 #endif | |
519 | |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
520 void GetCpuCaps( CpuCaps *caps) |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
521 { |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
522 caps->cpuType=0; |
3403 | 523 caps->cpuStepping=0; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
524 caps->hasMMX=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
525 caps->hasMMX2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
526 caps->has3DNow=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
527 caps->has3DNowExt=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
528 caps->hasSSE=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
529 caps->hasSSE2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
530 caps->isX86=0; |
9003 | 531 caps->hasAltiVec = 0; |
532 #ifdef HAVE_ALTIVEC | |
533 #ifdef SYS_DARWIN | |
534 /* | |
535 rip-off from ffmpeg altivec detection code. | |
536 this code also appears on Apple's AltiVec pages. | |
537 */ | |
538 { | |
539 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
540 int has_vu = 0; | |
541 size_t len = sizeof(has_vu); | |
542 int err; | |
543 | |
544 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
545 | |
546 if (err == 0) | |
547 if (has_vu != 0) | |
548 caps->hasAltiVec = 1; | |
549 } | |
550 #else /* SYS_DARWIN */ | |
551 /* no Darwin, do it the brute-force way */ | |
552 /* this is borrowed from the libmpeg2 library */ | |
553 { | |
554 signal (SIGILL, sigill_handler); | |
555 if (sigsetjmp (jmpbuf, 1)) { | |
556 signal (SIGILL, SIG_DFL); | |
557 } else { | |
558 canjump = 1; | |
559 | |
560 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 561 "vand %%v0, %%v0, %%v0" |
9003 | 562 : |
563 : "r" (-1)); | |
564 | |
565 signal (SIGILL, SIG_DFL); | |
566 caps->hasAltiVec = 1; | |
567 } | |
568 } | |
569 #endif /* SYS_DARWIN */ | |
9324 | 570 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 571 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
572 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
573 #ifdef ARCH_IA64 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
574 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
575 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
576 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
577 #ifdef ARCH_X86_64 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
578 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Advanced Micro Devices 64-bit CPU\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
579 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
580 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
581 #ifdef ARCH_SPARC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
582 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
583 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
584 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
585 #ifdef ARCH_ARMV4L |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
586 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
587 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
588 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
589 #ifdef ARCH_POWERPC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
590 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
591 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
592 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
593 #ifdef ARCH_ALPHA |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
594 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
595 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
596 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
597 #ifdef ARCH_SGI_MIPS |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
598 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
599 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
600 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
601 #ifdef ARCH_PA_RISC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
602 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
603 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
604 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
605 #ifdef ARCH_S390 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
606 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
607 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
608 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
609 #ifdef ARCH_S390X |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
610 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
611 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
612 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
613 #ifdef ARCH_VAX |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
614 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
615 #endif |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
616 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
617 #endif /* !ARCH_X86 */ |