Mercurial > mplayer.hg
annotate cpudetect.c @ 14307:2e35259a1558
change rc_init_buffer to be a fraction of total buffer size.
disallow qp_step=0.
author | lorenm |
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date | Sun, 02 Jan 2005 22:35:37 +0000 |
parents | 821f464b4d90 |
children | d94e79aecd69 |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #if defined(ARCH_X86) || defined(ARCH_X86_64) |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
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23 #ifdef __FreeBSD__ |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
2272 | 36 //#define X86_FXSR_MAGIC |
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37 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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38 * help understanding how to use it. Thanks to the Mesa |
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39 * team for SSE support detection and more cpu detect code. |
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40 */ |
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41 |
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42 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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43 |
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44 static void check_os_katmai_support( void ); |
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45 |
2272 | 46 #if 1 |
47 // return TRUE if cpuid supported | |
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48 static int has_cpuid() |
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49 { |
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50 long a, c; |
2272 | 51 |
52 // code from libavcodec: | |
53 __asm__ __volatile__ ( | |
54 /* See if CPUID instruction is supported ... */ | |
55 /* ... Get copies of EFLAGS into eax and ecx */ | |
56 "pushf\n\t" | |
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57 "pop %0\n\t" |
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58 "mov %0, %1\n\t" |
2272 | 59 |
60 /* ... Toggle the ID bit in one copy and store */ | |
61 /* to the EFLAGS reg */ | |
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62 "xor $0x200000, %0\n\t" |
2272 | 63 "push %0\n\t" |
64 "popf\n\t" | |
65 | |
66 /* ... Get the (hopefully modified) EFLAGS */ | |
67 "pushf\n\t" | |
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68 "pop %0\n\t" |
2272 | 69 : "=a" (a), "=c" (c) |
70 : | |
71 : "cc" | |
72 ); | |
73 | |
74 return (a!=c); | |
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75 } |
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76 #endif |
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77 |
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78 static void |
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79 do_cpuid(unsigned int ax, unsigned int *p) |
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80 { |
2272 | 81 #if 0 |
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82 __asm __volatile( |
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83 "cpuid;" |
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84 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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85 : "0" (ax) |
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86 ); |
2272 | 87 #else |
88 // code from libavcodec: | |
89 __asm __volatile | |
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90 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 91 "cpuid\n\t" |
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92 "xchg %%"REG_b", %%"REG_S |
3403 | 93 : "=a" (p[0]), "=S" (p[1]), |
2272 | 94 "=c" (p[2]), "=d" (p[3]) |
95 : "0" (ax)); | |
96 #endif | |
97 | |
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98 } |
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99 |
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100 void GetCpuCaps( CpuCaps *caps) |
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101 { |
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102 unsigned int regs[4]; |
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103 unsigned int regs2[4]; |
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104 |
8860 | 105 memset(caps, 0, sizeof(*caps)); |
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106 caps->isX86=1; |
8860 | 107 caps->cl_size=32; /* default */ |
2288 | 108 if (!has_cpuid()) { |
6134 | 109 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 110 return; |
111 } | |
112 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 113 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 114 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 115 if (regs[0]>=0x00000001) |
2280 | 116 { |
2303 | 117 char *tmpstr; |
8860 | 118 unsigned cl_size; |
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119 |
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120 do_cpuid(0x00000001, regs2); |
2301 | 121 |
2288 | 122 caps->cpuType=(regs2[0] >> 8)&0xf; |
123 if(caps->cpuType==0xf){ | |
124 // use extended family (P4, IA64) | |
125 caps->cpuType=8+((regs2[0]>>20)&255); | |
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126 } |
3403 | 127 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 128 |
129 // general feature flags: | |
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130 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 131 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
132 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
133 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 134 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 135 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
136 if(cl_size) caps->cl_size = cl_size; | |
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137 |
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138 tmpstr=GetCpuFriendlyName(regs, regs2); |
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139 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
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140 free(tmpstr); |
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141 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
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142 caps->cpuType, caps->cpuStepping); |
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143 |
2288 | 144 } |
145 do_cpuid(0x80000000, regs); | |
146 if (regs[0]>=0x80000001) { | |
6134 | 147 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 148 do_cpuid(0x80000001, regs2); |
3840 | 149 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
150 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 151 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
152 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
153 } | |
8860 | 154 if(regs[0]>=0x80000006) |
155 { | |
156 do_cpuid(0x80000006, regs2); | |
157 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
158 caps->cl_size = regs2[2] & 0xFF; | |
159 } | |
160 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 161 #if 0 |
5937 | 162 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 163 gCpuCaps.hasMMX, |
164 gCpuCaps.hasMMX2, | |
165 gCpuCaps.hasSSE, | |
166 gCpuCaps.hasSSE2, | |
167 gCpuCaps.has3DNow, | |
168 gCpuCaps.has3DNowExt ); | |
169 #endif | |
170 | |
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171 /* FIXME: Does SSE2 need more OS support, too? */ |
12613 | 172 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) |
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173 if (caps->hasSSE) |
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174 check_os_katmai_support(); |
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175 if (!caps->hasSSE) |
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176 caps->hasSSE2 = 0; |
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177 #else |
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178 caps->hasSSE=0; |
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179 caps->hasSSE2 = 0; |
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180 #endif |
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181 // caps->has3DNow=1; |
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182 // caps->hasMMX2 = 0; |
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183 // caps->hasMMX = 0; |
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184 |
4829 | 185 #ifndef HAVE_MMX |
6134 | 186 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 187 caps->hasMMX=0; |
188 #endif | |
189 #ifndef HAVE_MMX2 | |
6134 | 190 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 191 caps->hasMMX2=0; |
192 #endif | |
193 #ifndef HAVE_SSE | |
6134 | 194 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 195 caps->hasSSE=0; |
196 #endif | |
197 #ifndef HAVE_SSE2 | |
6134 | 198 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 199 caps->hasSSE2=0; |
200 #endif | |
201 #ifndef HAVE_3DNOW | |
6134 | 202 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 203 caps->has3DNow=0; |
204 #endif | |
205 #ifndef HAVE_3DNOWEX | |
6134 | 206 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 207 caps->has3DNowExt=0; |
208 #endif | |
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209 } |
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210 |
2301 | 211 |
212 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
213 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
214 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
215 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
216 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
217 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
218 | |
219 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
220 #include "cputable.h" /* get cpuname and cpuvendors */ | |
13628 | 221 char vendor[17]; |
2303 | 222 char *retname; |
13628 | 223 int i; |
2301 | 224 |
2417 | 225 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 226 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 227 exit(1); |
228 } | |
229 | |
3837 | 230 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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231 |
2301 | 232 for(i=0; i<MAX_VENDORS; i++){ |
233 if(!strcmp(cpuvendors[i].string,vendor)){ | |
234 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 235 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 236 } else { |
13628 | 237 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 238 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
239 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
240 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
241 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
242 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
243 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
244 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 245 "to the MPlayer-Developers, so we can add it to the list!\n"); |
246 } | |
247 } | |
248 } | |
249 | |
250 //printf("Detected CPU: %s\n", retname); | |
251 return retname; | |
252 } | |
253 | |
254 #undef CPUID_EXTFAMILY | |
255 #undef CPUID_EXTMODEL | |
256 #undef CPUID_TYPE | |
257 #undef CPUID_FAMILY | |
258 #undef CPUID_MODEL | |
259 #undef CPUID_STEPPING | |
260 | |
261 | |
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262 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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263 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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264 { |
6134 | 265 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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266 |
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267 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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268 * instructions are 3 bytes long. We must increment the instruction |
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269 * pointer manually to avoid repeated execution of the offending |
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270 * instruction. |
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271 * |
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272 * If the SIGILL is caused by a divide-by-zero when unmasked |
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273 * exceptions aren't supported, the SIMD FPU status and control |
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274 * word will be restored at the end of the test, so we don't need |
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275 * to worry about doing it here. Besides, we may not be able to... |
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276 */ |
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277 sc.eip += 3; |
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278 |
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279 gCpuCaps.hasSSE=0; |
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280 } |
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281 |
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282 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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283 { |
6134 | 284 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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285 |
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286 if ( sc.fpstate->magic != 0xffff ) { |
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287 /* Our signal context has the extended FPU state, so reset the |
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288 * divide-by-zero exception mask and clear the divide-by-zero |
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289 * exception bit. |
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290 */ |
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291 sc.fpstate->mxcsr |= 0x00000200; |
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292 sc.fpstate->mxcsr &= 0xfffffffb; |
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293 } else { |
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294 /* If we ever get here, we're completely hosed. |
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295 */ |
6134 | 296 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
297 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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298 } |
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299 } |
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300 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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301 |
10440 | 302 #ifdef WIN32 |
303 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
304 { | |
305 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
306 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
307 ep->ContextRecord->Eip +=3; | |
308 gCpuCaps.hasSSE=0; | |
309 return EXCEPTION_CONTINUE_EXECUTION; | |
310 } | |
311 return EXCEPTION_CONTINUE_SEARCH; | |
312 } | |
313 #endif /* WIN32 */ | |
314 | |
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315 /* If we're running on a processor that can do SSE, let's see if we |
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316 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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317 * haven't been configured for a Pentium III but are running on one, |
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318 * and RedHat patched 2.2 kernels that have broken exception handling |
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319 * support for user space apps that do SSE. |
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320 */ |
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321 static void check_os_katmai_support( void ) |
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322 { |
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323 #if defined(__FreeBSD__) |
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324 int has_sse=0, ret; |
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325 size_t len=sizeof(has_sse); |
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326 |
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327 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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328 if (ret || !has_sse) |
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329 gCpuCaps.hasSSE=0; |
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330 |
12143 | 331 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
332 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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333 int has_sse, has_sse2, ret, mib[2]; |
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334 size_t varlen; |
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335 |
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336 mib[0] = CTL_MACHDEP; |
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337 mib[1] = CPU_SSE; |
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338 varlen = sizeof(has_sse); |
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339 |
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340 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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341 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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342 if (ret < 0 || !has_sse) { |
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343 gCpuCaps.hasSSE=0; |
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344 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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345 } else { |
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346 gCpuCaps.hasSSE=1; |
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347 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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348 } |
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349 |
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350 mib[1] = CPU_SSE2; |
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351 varlen = sizeof(has_sse2); |
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352 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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353 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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354 if (ret < 0 || !has_sse2) { |
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355 gCpuCaps.hasSSE2=0; |
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356 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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357 } else { |
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358 gCpuCaps.hasSSE2=1; |
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359 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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360 } |
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361 #else |
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362 gCpuCaps.hasSSE = 0; |
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363 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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364 #endif |
10440 | 365 #elif defined(WIN32) |
366 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
367 if ( gCpuCaps.hasSSE ) { | |
368 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
369 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
370 __asm __volatile ("xorps %xmm0, %xmm0"); | |
371 SetUnhandledExceptionFilter(exc_fil); | |
372 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
373 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
374 } | |
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375 #elif defined(__linux__) |
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376 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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377 struct sigaction saved_sigill; |
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378 struct sigaction saved_sigfpe; |
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379 |
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380 /* Save the original signal handlers. |
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381 */ |
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382 sigaction( SIGILL, NULL, &saved_sigill ); |
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383 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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384 |
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385 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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386 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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387 |
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388 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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389 * supports the extended FPU save and restore required for SSE. If |
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390 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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391 * doesn't support Streaming SIMD Exceptions, even if the processor |
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392 * does. |
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393 */ |
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394 if ( gCpuCaps.hasSSE ) { |
6134 | 395 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
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396 |
2272 | 397 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
398 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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399 |
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400 if ( gCpuCaps.hasSSE ) { |
6134 | 401 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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402 } else { |
6134 | 403 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
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404 } |
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405 } |
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406 |
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407 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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408 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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409 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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410 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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411 * as expected, we're okay but we need to clean up after it. |
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412 * |
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413 * Are we being too stringent in our requirement that the OS support |
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414 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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415 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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416 * doesn't even support them. We at least know the user-space SSE |
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417 * support is good in kernels that do support unmasked exceptions, |
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418 * and therefore to be safe I'm going to leave this test in here. |
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419 */ |
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420 if ( gCpuCaps.hasSSE ) { |
6134 | 421 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
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422 |
2272 | 423 // test_os_katmai_exception_support(); |
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424 |
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425 if ( gCpuCaps.hasSSE ) { |
6134 | 426 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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427 } else { |
6134 | 428 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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429 } |
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430 } |
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431 |
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432 /* Restore the original signal handlers. |
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433 */ |
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434 sigaction( SIGILL, &saved_sigill, NULL ); |
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435 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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436 |
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437 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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438 * safe to go ahead and hook out the SSE code throughout Mesa. |
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439 */ |
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440 if ( gCpuCaps.hasSSE ) { |
6134 | 441 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
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442 } else { |
6134 | 443 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
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444 } |
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445 #else |
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446 /* We can't use POSIX signal handling to test the availability of |
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447 * SSE, so we disable it by default. |
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448 */ |
5937 | 449 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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450 gCpuCaps.hasSSE=0; |
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451 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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452 #else |
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453 /* Do nothing on other platforms for now. |
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454 */ |
6134 | 455 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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456 gCpuCaps.hasSSE=0; |
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457 #endif /* __linux__ */ |
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458 } |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
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459 #else /* ARCH_X86 || ARCH_X86_64 */ |
3146
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460 |
9003 | 461 #ifdef SYS_DARWIN |
462 #include <sys/sysctl.h> | |
463 #else | |
464 #include <signal.h> | |
465 #include <setjmp.h> | |
466 | |
467 static sigjmp_buf jmpbuf; | |
468 static volatile sig_atomic_t canjump = 0; | |
469 | |
470 static void sigill_handler (int sig) | |
471 { | |
472 if (!canjump) { | |
473 signal (sig, SIG_DFL); | |
474 raise (sig); | |
475 } | |
476 | |
477 canjump = 0; | |
478 siglongjmp (jmpbuf, 1); | |
479 } | |
480 #endif | |
481 | |
3146
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482 void GetCpuCaps( CpuCaps *caps) |
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483 { |
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484 caps->cpuType=0; |
3403 | 485 caps->cpuStepping=0; |
3146
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486 caps->hasMMX=0; |
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487 caps->hasMMX2=0; |
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488 caps->has3DNow=0; |
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489 caps->has3DNowExt=0; |
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490 caps->hasSSE=0; |
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491 caps->hasSSE2=0; |
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492 caps->isX86=0; |
9003 | 493 caps->hasAltiVec = 0; |
494 #ifdef HAVE_ALTIVEC | |
495 #ifdef SYS_DARWIN | |
496 /* | |
497 rip-off from ffmpeg altivec detection code. | |
498 this code also appears on Apple's AltiVec pages. | |
499 */ | |
500 { | |
501 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
502 int has_vu = 0; | |
503 size_t len = sizeof(has_vu); | |
504 int err; | |
505 | |
506 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
507 | |
508 if (err == 0) | |
509 if (has_vu != 0) | |
510 caps->hasAltiVec = 1; | |
511 } | |
512 #else /* SYS_DARWIN */ | |
513 /* no Darwin, do it the brute-force way */ | |
514 /* this is borrowed from the libmpeg2 library */ | |
515 { | |
516 signal (SIGILL, sigill_handler); | |
517 if (sigsetjmp (jmpbuf, 1)) { | |
518 signal (SIGILL, SIG_DFL); | |
519 } else { | |
520 canjump = 1; | |
521 | |
522 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 523 "vand %%v0, %%v0, %%v0" |
9003 | 524 : |
525 : "r" (-1)); | |
526 | |
527 signal (SIGILL, SIG_DFL); | |
528 caps->hasAltiVec = 1; | |
529 } | |
530 } | |
531 #endif /* SYS_DARWIN */ | |
9324 | 532 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 533 #endif /* HAVE_ALTIVEC */ |
11962
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|
534 |
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535 #ifdef ARCH_IA64 |
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536 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
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537 #endif |
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diff
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|
538 |
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diff
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|
539 #ifdef ARCH_SPARC |
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540 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
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|
541 #endif |
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|
542 |
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543 #ifdef ARCH_ARMV4L |
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544 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
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545 #endif |
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|
546 |
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547 #ifdef ARCH_POWERPC |
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548 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
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549 #endif |
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|
550 |
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551 #ifdef ARCH_ALPHA |
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552 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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553 #endif |
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|
554 |
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555 #ifdef ARCH_SGI_MIPS |
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556 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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557 #endif |
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|
558 |
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559 #ifdef ARCH_PA_RISC |
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560 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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|
561 #endif |
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|
562 |
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|
563 #ifdef ARCH_S390 |
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564 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
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changeset
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565 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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566 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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567 #ifdef ARCH_S390X |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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568 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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569 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
570 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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571 #ifdef ARCH_VAX |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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changeset
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572 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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573 #endif |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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574 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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575 #endif /* !ARCH_X86 */ |