Mercurial > mplayer.hg
annotate cpudetect.c @ 27030:345888b380b1
spelling/wording fixes
author | diego |
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date | Sun, 15 Jun 2008 11:20:09 +0000 |
parents | 8eff880f638c |
children | 11c1f98df84c |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
20577 | 12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
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23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
26061 | 36 #ifdef __OS2__ |
37 #define INCL_DOS | |
38 #include <os2.h> | |
39 #endif | |
40 | |
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41 #ifdef __AMIGAOS4__ |
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42 #include <proto/exec.h> |
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43 #endif |
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44 |
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45 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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46 * help understanding how to use it. Thanks to the Mesa |
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47 * team for SSE support detection and more cpu detect code. |
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48 */ |
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49 |
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50 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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51 |
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52 static void check_os_katmai_support( void ); |
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53 |
2272 | 54 #if 1 |
55 // return TRUE if cpuid supported | |
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56 static int has_cpuid(void) |
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57 { |
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58 long a, c; |
2272 | 59 |
60 // code from libavcodec: | |
61 __asm__ __volatile__ ( | |
62 /* See if CPUID instruction is supported ... */ | |
63 /* ... Get copies of EFLAGS into eax and ecx */ | |
64 "pushf\n\t" | |
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65 "pop %0\n\t" |
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66 "mov %0, %1\n\t" |
2272 | 67 |
68 /* ... Toggle the ID bit in one copy and store */ | |
69 /* to the EFLAGS reg */ | |
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70 "xor $0x200000, %0\n\t" |
2272 | 71 "push %0\n\t" |
72 "popf\n\t" | |
73 | |
74 /* ... Get the (hopefully modified) EFLAGS */ | |
75 "pushf\n\t" | |
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76 "pop %0\n\t" |
2272 | 77 : "=a" (a), "=c" (c) |
78 : | |
79 : "cc" | |
80 ); | |
81 | |
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82 return a != c; |
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83 } |
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84 #endif |
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85 |
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86 static void |
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87 do_cpuid(unsigned int ax, unsigned int *p) |
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88 { |
2272 | 89 #if 0 |
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90 __asm __volatile( |
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91 "cpuid;" |
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92 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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93 : "0" (ax) |
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94 ); |
2272 | 95 #else |
96 // code from libavcodec: | |
97 __asm __volatile | |
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98 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 99 "cpuid\n\t" |
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100 "xchg %%"REG_b", %%"REG_S |
3403 | 101 : "=a" (p[0]), "=S" (p[1]), |
2272 | 102 "=c" (p[2]), "=d" (p[3]) |
103 : "0" (ax)); | |
104 #endif | |
105 | |
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106 } |
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107 |
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108 void GetCpuCaps( CpuCaps *caps) |
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109 { |
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110 unsigned int regs[4]; |
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111 unsigned int regs2[4]; |
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112 |
8860 | 113 memset(caps, 0, sizeof(*caps)); |
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114 caps->isX86=1; |
8860 | 115 caps->cl_size=32; /* default */ |
2288 | 116 if (!has_cpuid()) { |
6134 | 117 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 118 return; |
119 } | |
120 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 121 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 122 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 123 if (regs[0]>=0x00000001) |
2280 | 124 { |
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125 char *tmpstr, *ptmpstr; |
8860 | 126 unsigned cl_size; |
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127 |
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128 do_cpuid(0x00000001, regs2); |
2301 | 129 |
2288 | 130 caps->cpuType=(regs2[0] >> 8)&0xf; |
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131 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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132 |
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133 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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134 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 135 if(caps->cpuType==0xf){ |
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136 // use extended family (P4, IA64, K8) |
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137 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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138 } |
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139 if(caps->cpuType==0xf || caps->cpuType==6) |
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140 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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141 |
3403 | 142 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 143 |
144 // general feature flags: | |
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145 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 146 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
147 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
148 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 149 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 150 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
151 if(cl_size) caps->cl_size = cl_size; | |
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152 |
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153 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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154 while(*ptmpstr == ' ') // strip leading spaces |
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155 ptmpstr++; |
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156 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
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157 free(tmpstr); |
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158 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
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159 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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160 |
2288 | 161 } |
162 do_cpuid(0x80000000, regs); | |
163 if (regs[0]>=0x80000001) { | |
6134 | 164 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 165 do_cpuid(0x80000001, regs2); |
3840 | 166 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
167 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 168 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
169 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
170 } | |
8860 | 171 if(regs[0]>=0x80000006) |
172 { | |
173 do_cpuid(0x80000006, regs2); | |
174 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
175 caps->cl_size = regs2[2] & 0xFF; | |
176 } | |
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177 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 178 #if 0 |
5937 | 179 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 180 gCpuCaps.hasMMX, |
181 gCpuCaps.hasMMX2, | |
182 gCpuCaps.hasSSE, | |
183 gCpuCaps.hasSSE2, | |
184 gCpuCaps.has3DNow, | |
185 gCpuCaps.has3DNowExt ); | |
186 #endif | |
187 | |
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188 /* FIXME: Does SSE2 need more OS support, too? */ |
26060 | 189 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
190 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \ | |
26061 | 191 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \ |
192 || defined(__OS2__) | |
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193 if (caps->hasSSE) |
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194 check_os_katmai_support(); |
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195 if (!caps->hasSSE) |
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196 caps->hasSSE2 = 0; |
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197 #else |
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198 caps->hasSSE=0; |
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199 caps->hasSSE2 = 0; |
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200 #endif |
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201 // caps->has3DNow=1; |
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202 // caps->hasMMX2 = 0; |
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203 // caps->hasMMX = 0; |
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204 |
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205 #ifndef RUNTIME_CPUDETECT |
4829 | 206 #ifndef HAVE_MMX |
6134 | 207 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 208 caps->hasMMX=0; |
209 #endif | |
210 #ifndef HAVE_MMX2 | |
6134 | 211 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 212 caps->hasMMX2=0; |
213 #endif | |
214 #ifndef HAVE_SSE | |
6134 | 215 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 216 caps->hasSSE=0; |
217 #endif | |
218 #ifndef HAVE_SSE2 | |
6134 | 219 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 220 caps->hasSSE2=0; |
221 #endif | |
222 #ifndef HAVE_3DNOW | |
6134 | 223 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 224 caps->has3DNow=0; |
225 #endif | |
226 #ifndef HAVE_3DNOWEX | |
6134 | 227 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 228 caps->has3DNowExt=0; |
229 #endif | |
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230 #endif // RUNTIME_CPUDETECT |
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231 } |
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232 |
2301 | 233 |
234 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
235 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
236 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
237 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
238 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
239 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
240 | |
241 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
242 #include "cputable.h" /* get cpuname and cpuvendors */ | |
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243 char vendor[13]; |
2303 | 244 char *retname; |
13628 | 245 int i; |
2301 | 246 |
18869 | 247 if (NULL==(retname=malloc(256))) { |
5937 | 248 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 249 exit(1); |
250 } | |
251 | |
3837 | 252 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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253 |
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254 do_cpuid(0x80000000,regs); |
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255 if (regs[0] >= 0x80000004) |
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256 { |
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257 // CPU has built-in namestring |
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258 retname[0] = '\0'; |
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259 for (i = 0x80000002; i <= 0x80000004; i++) |
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260 { |
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261 do_cpuid(i, regs); |
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262 strncat(retname, (char*)regs, 16); |
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263 } |
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264 return retname; |
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265 } |
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266 |
2301 | 267 for(i=0; i<MAX_VENDORS; i++){ |
268 if(!strcmp(cpuvendors[i].string,vendor)){ | |
269 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 270 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 271 } else { |
13628 | 272 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 273 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
274 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
275 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
276 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
277 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
278 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
279 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 280 "to the MPlayer-Developers, so we can add it to the list!\n"); |
281 } | |
282 } | |
283 } | |
14478 | 284 retname[255] = 0; |
2301 | 285 |
286 //printf("Detected CPU: %s\n", retname); | |
287 return retname; | |
288 } | |
289 | |
290 #undef CPUID_EXTFAMILY | |
291 #undef CPUID_EXTMODEL | |
292 #undef CPUID_TYPE | |
293 #undef CPUID_FAMILY | |
294 #undef CPUID_MODEL | |
295 #undef CPUID_STEPPING | |
296 | |
297 | |
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298 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64) |
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299 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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300 { |
6134 | 301 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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302 |
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303 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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304 * instructions are 3 bytes long. We must increment the instruction |
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305 * pointer manually to avoid repeated execution of the offending |
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306 * instruction. |
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307 * |
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308 * If the SIGILL is caused by a divide-by-zero when unmasked |
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309 * exceptions aren't supported, the SIMD FPU status and control |
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310 * word will be restored at the end of the test, so we don't need |
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311 * to worry about doing it here. Besides, we may not be able to... |
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312 */ |
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313 sc.eip += 3; |
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314 |
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315 gCpuCaps.hasSSE=0; |
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316 } |
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317 #endif /* __linux__ && _POSIX_SOURCE */ |
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318 |
10440 | 319 #ifdef WIN32 |
320 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
321 { | |
322 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
323 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
324 ep->ContextRecord->Eip +=3; | |
325 gCpuCaps.hasSSE=0; | |
326 return EXCEPTION_CONTINUE_EXECUTION; | |
327 } | |
328 return EXCEPTION_CONTINUE_SEARCH; | |
329 } | |
330 #endif /* WIN32 */ | |
331 | |
26061 | 332 #ifdef __OS2__ |
333 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
334 PEXCEPTIONREGISTRATIONRECORD p2, | |
335 PCONTEXTRECORD p3, | |
336 PVOID p4 ) | |
337 { | |
338 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
339 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
340 | |
341 p3->ctx_RegEip += 3; | |
342 gCpuCaps.hasSSE = 0; | |
343 | |
344 return XCPT_CONTINUE_EXECUTION; | |
345 } | |
346 return XCPT_CONTINUE_SEARCH; | |
347 } | |
348 #endif | |
349 | |
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350 /* If we're running on a processor that can do SSE, let's see if we |
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351 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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352 * haven't been configured for a Pentium III but are running on one, |
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353 * and RedHat patched 2.2 kernels that have broken exception handling |
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354 * support for user space apps that do SSE. |
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355 */ |
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356 |
21848 | 357 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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358 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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359 #elif defined(__APPLE__) |
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360 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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361 #endif |
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362 |
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363 static void check_os_katmai_support( void ) |
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364 { |
14455 | 365 #ifdef ARCH_X86_64 |
366 gCpuCaps.hasSSE=1; | |
367 gCpuCaps.hasSSE2=1; | |
21848 | 368 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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369 int has_sse=0, ret; |
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370 size_t len=sizeof(has_sse); |
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371 |
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372 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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373 if (ret || !has_sse) |
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374 gCpuCaps.hasSSE=0; |
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375 |
12143 | 376 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
377 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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378 int has_sse, has_sse2, ret, mib[2]; |
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379 size_t varlen; |
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380 |
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381 mib[0] = CTL_MACHDEP; |
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382 mib[1] = CPU_SSE; |
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383 varlen = sizeof(has_sse); |
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384 |
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385 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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386 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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387 if (ret < 0 || !has_sse) { |
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arpi
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388 gCpuCaps.hasSSE=0; |
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389 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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390 } else { |
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Ok, here is a better patch, which even adds a fix to compile it on older
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391 gCpuCaps.hasSSE=1; |
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392 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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393 } |
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Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
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394 |
8533
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Ok, here is a better patch, which even adds a fix to compile it on older
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parents:
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395 mib[1] = CPU_SSE2; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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396 varlen = sizeof(has_sse2); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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397 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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398 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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399 if (ret < 0 || !has_sse2) { |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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400 gCpuCaps.hasSSE2=0; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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parents:
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401 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
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402 } else { |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
403 gCpuCaps.hasSSE2=1; |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
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404 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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diff
changeset
|
405 } |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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diff
changeset
|
406 #else |
8533
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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diff
changeset
|
407 gCpuCaps.hasSSE = 0; |
8401
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Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
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408 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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409 #endif |
10440 | 410 #elif defined(WIN32) |
411 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
412 if ( gCpuCaps.hasSSE ) { | |
413 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
414 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
415 __asm __volatile ("xorps %xmm0, %xmm0"); | |
416 SetUnhandledExceptionFilter(exc_fil); | |
417 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
418 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
419 } | |
26061 | 420 #elif defined(__OS2__) |
421 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
422 if ( gCpuCaps.hasSSE ) { | |
423 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
424 DosSetExceptionHandler( &RegRec ); | |
425 __asm __volatile ("xorps %xmm0, %xmm0"); | |
426 DosUnsetExceptionHandler( &RegRec ); | |
427 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
428 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
429 } | |
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430 #elif defined(__linux__) |
24439
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Do not check for X86_FXSR_MAGIC define, it is missing in newer
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431 #if defined(_POSIX_SOURCE) |
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432 struct sigaction saved_sigill; |
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433 |
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arpi
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434 /* Save the original signal handlers. |
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arpi
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435 */ |
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436 sigaction( SIGILL, NULL, &saved_sigill ); |
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arpi
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437 |
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arpi
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438 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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arpi
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439 |
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arpi
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440 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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441 * supports the extended FPU save and restore required for SSE. If |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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442 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
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443 * doesn't support Streaming SIMD Exceptions, even if the processor |
72ff2179d396
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arpi
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444 * does. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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445 */ |
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446 if ( gCpuCaps.hasSSE ) { |
6134 | 447 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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448 |
2272 | 449 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
450 __asm __volatile ("xorps %xmm0, %xmm0"); | |
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451 |
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arpi
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452 if ( gCpuCaps.hasSSE ) { |
6134 | 453 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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454 } else { |
6134 | 455 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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456 } |
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arpi
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457 } |
72ff2179d396
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arpi
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458 |
72ff2179d396
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arpi
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459 /* Restore the original signal handlers. |
72ff2179d396
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arpi
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460 */ |
72ff2179d396
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arpi
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461 sigaction( SIGILL, &saved_sigill, NULL ); |
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arpi
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462 |
72ff2179d396
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arpi
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463 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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diff
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464 * safe to go ahead and hook out the SSE code throughout Mesa. |
72ff2179d396
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arpi
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465 */ |
72ff2179d396
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arpi
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466 if ( gCpuCaps.hasSSE ) { |
6134 | 467 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
2268
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arpi
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468 } else { |
6134 | 469 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
72ff2179d396
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arpi
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470 } |
72ff2179d396
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arpi
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471 #else |
72ff2179d396
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arpi
parents:
diff
changeset
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472 /* We can't use POSIX signal handling to test the availability of |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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473 * SSE, so we disable it by default. |
72ff2179d396
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arpi
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diff
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474 */ |
5937 | 475 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
2268
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arpi
parents:
diff
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|
476 gCpuCaps.hasSSE=0; |
24439
680bc9411ecf
Do not check for X86_FXSR_MAGIC define, it is missing in newer
reimar
parents:
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diff
changeset
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477 #endif /* _POSIX_SOURCE */ |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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|
478 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
479 /* Do nothing on other platforms for now. |
72ff2179d396
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arpi
parents:
diff
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|
480 */ |
6134 | 481 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
2268
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arpi
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482 gCpuCaps.hasSSE=0; |
72ff2179d396
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arpi
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|
483 #endif /* __linux__ */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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|
484 } |
20577 | 485 #else /* ARCH_X86 */ |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
486 |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
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487 #ifdef __APPLE__ |
9003 | 488 #include <sys/sysctl.h> |
25338
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
489 #elif __AMIGAOS4__ |
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
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490 /* nothing */ |
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
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diff
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491 #else |
9003 | 492 #include <signal.h> |
493 #include <setjmp.h> | |
494 | |
495 static sigjmp_buf jmpbuf; | |
496 static volatile sig_atomic_t canjump = 0; | |
497 | |
498 static void sigill_handler (int sig) | |
499 { | |
500 if (!canjump) { | |
501 signal (sig, SIG_DFL); | |
502 raise (sig); | |
503 } | |
504 | |
505 canjump = 0; | |
506 siglongjmp (jmpbuf, 1); | |
507 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
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diff
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508 #endif /* __APPLE__ */ |
9003 | 509 |
3146
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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diff
changeset
|
510 void GetCpuCaps( CpuCaps *caps) |
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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diff
changeset
|
511 { |
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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diff
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|
512 caps->cpuType=0; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
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513 caps->cpuModel=0; |
3403 | 514 caps->cpuStepping=0; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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515 caps->hasMMX=0; |
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changeset
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516 caps->hasMMX2=0; |
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517 caps->has3DNow=0; |
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michael
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518 caps->has3DNowExt=0; |
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changeset
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519 caps->hasSSE=0; |
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michael
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changeset
|
520 caps->hasSSE2=0; |
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michael
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changeset
|
521 caps->isX86=0; |
9003 | 522 caps->hasAltiVec = 0; |
523 #ifdef HAVE_ALTIVEC | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
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24664
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changeset
|
524 #ifdef __APPLE__ |
9003 | 525 /* |
526 rip-off from ffmpeg altivec detection code. | |
527 this code also appears on Apple's AltiVec pages. | |
528 */ | |
529 { | |
530 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
531 int has_vu = 0; | |
532 size_t len = sizeof(has_vu); | |
533 int err; | |
534 | |
535 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
536 | |
537 if (err == 0) | |
538 if (has_vu != 0) | |
539 caps->hasAltiVec = 1; | |
540 } | |
25339 | 541 #elif __AMIGAOS4__ |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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|
542 ULONG result = 0; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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543 |
485f04e5a58c
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544 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
485f04e5a58c
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545 if (result == VECTORTYPE_ALTIVEC) |
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546 caps->hasAltiVec = 1; |
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547 #else |
9003 | 548 /* no Darwin, do it the brute-force way */ |
549 /* this is borrowed from the libmpeg2 library */ | |
550 { | |
551 signal (SIGILL, sigill_handler); | |
552 if (sigsetjmp (jmpbuf, 1)) { | |
553 signal (SIGILL, SIG_DFL); | |
554 } else { | |
555 canjump = 1; | |
556 | |
557 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 558 "vand %%v0, %%v0, %%v0" |
9003 | 559 : |
560 : "r" (-1)); | |
561 | |
562 signal (SIGILL, SIG_DFL); | |
563 caps->hasAltiVec = 1; | |
564 } | |
565 } | |
25329
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566 #endif /* __APPLE__ */ |
9324 | 567 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 568 #endif /* HAVE_ALTIVEC */ |
11962
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gabucino
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|
569 |
909093c314e9
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gabucino
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diff
changeset
|
570 #ifdef ARCH_IA64 |
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571 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
909093c314e9
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changeset
|
572 #endif |
909093c314e9
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gabucino
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diff
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|
573 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
574 #ifdef ARCH_SPARC |
909093c314e9
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10955
diff
changeset
|
575 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
909093c314e9
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gabucino
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10955
diff
changeset
|
576 #endif |
909093c314e9
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gabucino
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10955
diff
changeset
|
577 |
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578 #ifdef ARCH_ARMV4L |
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579 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
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580 #endif |
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581 |
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582 #ifdef ARCH_POWERPC |
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583 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
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584 #endif |
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585 |
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586 #ifdef ARCH_ALPHA |
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587 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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588 #endif |
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589 |
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590 #ifdef ARCH_SGI_MIPS |
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591 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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592 #endif |
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593 |
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594 #ifdef ARCH_PA_RISC |
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595 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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596 #endif |
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597 |
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598 #ifdef ARCH_S390 |
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599 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
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600 #endif |
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601 |
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602 #ifdef ARCH_S390X |
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603 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
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604 #endif |
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605 |
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606 #ifdef ARCH_VAX |
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607 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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608 #endif |
25340 | 609 |
610 #ifdef ARCH_XTENSA | |
611 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" ); | |
612 #endif | |
3146
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613 } |
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614 #endif /* !ARCH_X86 */ |