Mercurial > mplayer.hg
annotate vidix/drivers/mach64_vid.c @ 7825:52818222a8be
endianness fixes for mach64 vidix driver patch by (Colin Leroy <colin at colino dot net>)
author | michael |
---|---|
date | Mon, 21 Oct 2002 16:57:02 +0000 |
parents | d2aec12937f8 |
children | 6bfe33dc531e |
rev | line source |
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4691 | 1 /* |
2 mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips | |
3 Copyrights 2002 Nick Kurshev. This file is based on sources from | |
4 GATOS (gatos.sf.net) and X11 (www.xfree86.org) | |
5 Licence: GPL | |
4866 | 6 WARNING: THIS DRIVER IS IN BETTA STAGE |
4691 | 7 */ |
8 #include <errno.h> | |
9 #include <stdio.h> | |
10 #include <stdlib.h> | |
11 #include <string.h> | |
12 #include <math.h> | |
13 #include <inttypes.h> | |
14 #include <fcntl.h> | |
15 | |
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16 #include "../../config.h" |
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17 #include "../../bswap.h" |
4691 | 18 #include "../vidix.h" |
19 #include "../fourcc.h" | |
20 #include "../../libdha/libdha.h" | |
21 #include "../../libdha/pci_ids.h" | |
22 #include "../../libdha/pci_names.h" | |
23 | |
24 #include "mach64.h" | |
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25 #include "../../version.h" |
4691 | 26 |
27 #define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ | |
28 | |
29 static void *mach64_mmio_base = 0; | |
30 static void *mach64_mem_base = 0; | |
4721 | 31 static int32_t mach64_overlay_offset = 0; |
4691 | 32 static uint32_t mach64_ram_size = 0; |
4866 | 33 static uint32_t mach64_buffer_base[10][3]; |
34 static int num_mach64_buffers=-1; | |
4876 | 35 static int supports_planar=0; |
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36 static int supports_lcd_v_stretch=0; |
4691 | 37 |
38 pciinfo_t pci_info; | |
39 static int probed = 0; | |
40 static int __verbose = 0; | |
4721 | 41 |
4758 | 42 #define VERBOSE_LEVEL 1 |
43 | |
4721 | 44 typedef struct bes_registers_s |
45 { | |
46 /* base address of yuv framebuffer */ | |
47 uint32_t yuv_base; | |
48 uint32_t fourcc; | |
49 /* YUV BES registers */ | |
50 uint32_t reg_load_cntl; | |
51 uint32_t scale_inc; | |
52 uint32_t y_x_start; | |
53 uint32_t y_x_end; | |
54 uint32_t vid_buf_pitch; | |
55 uint32_t height_width; | |
56 | |
57 uint32_t scale_cntl; | |
58 uint32_t exclusive_horz; | |
59 uint32_t auto_flip_cntl; | |
60 uint32_t filter_cntl; | |
61 uint32_t key_cntl; | |
62 uint32_t test; | |
63 /* Configurable stuff */ | |
64 | |
65 int brightness; | |
66 int saturation; | |
67 | |
68 int ckey_on; | |
69 uint32_t graphics_key_clr; | |
70 uint32_t graphics_key_msk; | |
71 | |
72 int deinterlace_on; | |
73 uint32_t deinterlace_pattern; | |
74 | |
75 } bes_registers_t; | |
76 | |
77 static bes_registers_t besr; | |
78 | |
79 typedef struct video_registers_s | |
80 { | |
81 const char * sname; | |
82 uint32_t name; | |
83 uint32_t value; | |
84 }video_registers_t; | |
85 | |
86 static bes_registers_t besr; | |
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87 |
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88 /* Graphic keys */ |
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89 static vidix_grkey_t mach64_grkey; |
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90 |
4721 | 91 #define DECLARE_VREG(name) { #name, name, 0 } |
92 static video_registers_t vregs[] = | |
93 { | |
94 DECLARE_VREG(OVERLAY_SCALE_INC), | |
95 DECLARE_VREG(OVERLAY_Y_X_START), | |
96 DECLARE_VREG(OVERLAY_Y_X_END), | |
97 DECLARE_VREG(OVERLAY_SCALE_CNTL), | |
98 DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), | |
99 DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), | |
100 DECLARE_VREG(OVERLAY_TEST), | |
101 DECLARE_VREG(SCALER_BUF_PITCH), | |
102 DECLARE_VREG(SCALER_HEIGHT_WIDTH), | |
103 DECLARE_VREG(SCALER_BUF0_OFFSET), | |
104 DECLARE_VREG(SCALER_BUF0_OFFSET_U), | |
105 DECLARE_VREG(SCALER_BUF0_OFFSET_V), | |
106 DECLARE_VREG(SCALER_BUF1_OFFSET), | |
107 DECLARE_VREG(SCALER_BUF1_OFFSET_U), | |
108 DECLARE_VREG(SCALER_BUF1_OFFSET_V), | |
109 DECLARE_VREG(SCALER_H_COEFF0), | |
110 DECLARE_VREG(SCALER_H_COEFF1), | |
111 DECLARE_VREG(SCALER_H_COEFF2), | |
112 DECLARE_VREG(SCALER_H_COEFF3), | |
113 DECLARE_VREG(SCALER_H_COEFF4), | |
114 DECLARE_VREG(SCALER_COLOUR_CNTL), | |
115 DECLARE_VREG(SCALER_THRESHOLD), | |
116 DECLARE_VREG(VIDEO_FORMAT), | |
117 DECLARE_VREG(VIDEO_CONFIG), | |
118 DECLARE_VREG(VIDEO_SYNC_TEST), | |
119 DECLARE_VREG(VIDEO_SYNC_TEST_B) | |
120 }; | |
121 | |
4691 | 122 /* VIDIX exports */ |
123 | |
124 /* MMIO space*/ | |
125 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
126 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
127 | |
4721 | 128 #define INREG8(addr) GETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2) |
129 #define OUTREG8(addr,val) SETREG(uint8_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,val) | |
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130 #define INREG(addr) le2me_32(GETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2)) |
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131 #define OUTREG(addr,val) SETREG(uint32_t,(uint32_t)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val)) |
4691 | 132 |
133 #define OUTREGP(addr,val,mask) \ | |
134 do { \ | |
135 unsigned int _tmp = INREG(addr); \ | |
136 _tmp &= (mask); \ | |
137 _tmp |= (val); \ | |
138 OUTREG(addr, _tmp); \ | |
139 } while (0) | |
140 | |
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141 static __inline__ int ATIGetMach64LCDReg(int _Index) |
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142 { |
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143 OUTREG8(LCD_INDEX, _Index); |
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144 return INREG(LCD_DATA); |
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145 } |
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146 |
4691 | 147 static __inline__ uint32_t INPLL(uint32_t addr) |
148 { | |
4721 | 149 uint32_t res; |
5731 | 150 uint32_t in; |
151 | |
5792 | 152 in= INREG(CLOCK_CNTL); |
153 in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff | |
154 OUTREG(CLOCK_CNTL, in | (addr<<10)); | |
5731 | 155 |
4721 | 156 /* read the register value */ |
5792 | 157 res = (INREG(CLOCK_CNTL)>>16)&0xFF; |
4721 | 158 return res; |
4691 | 159 } |
160 | |
4721 | 161 static __inline__ void OUTPLL(uint32_t addr,uint32_t val) |
162 { | |
5792 | 163 //FIXME buggy but its not used |
4721 | 164 /* write addr byte */ |
165 OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); | |
166 /* write the register value */ | |
167 OUTREG(CLOCK_CNTL + 2, val); | |
168 OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); | |
169 } | |
170 | |
4691 | 171 #define OUTPLLP(addr,val,mask) \ |
172 do { \ | |
173 unsigned int _tmp = INPLL(addr); \ | |
174 _tmp &= (mask); \ | |
175 _tmp |= (val); \ | |
176 OUTPLL(addr, _tmp); \ | |
177 } while (0) | |
178 | |
4721 | 179 static void mach64_fifo_wait(unsigned n) |
180 { | |
181 while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); | |
182 } | |
183 | |
184 static void mach64_wait_for_idle( void ) | |
185 { | |
186 mach64_fifo_wait(16); | |
187 while ((INREG(GUI_STAT) & 1)!= 0); | |
188 } | |
189 | |
4876 | 190 static void mach64_wait_vsync( void ) |
191 { | |
192 int i; | |
193 | |
194 for(i=0; i<2000000; i++) | |
195 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; | |
196 for(i=0; i<2000000; i++) | |
197 if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; | |
198 | |
199 } | |
200 | |
4691 | 201 static vidix_capability_t mach64_cap = |
202 { | |
203 "BES driver for Mach64/3DRage cards", | |
4872 | 204 "Nick Kurshev and Michael Niedermayer", |
4691 | 205 TYPE_OUTPUT, |
206 { 0, 0, 0, 0 }, | |
207 2048, | |
208 2048, | |
209 4, | |
210 4, | |
211 -1, | |
212 FLAG_UPSCALER|FLAG_DOWNSCALER, | |
213 VENDOR_ATI, | |
214 -1, | |
215 { 0, 0, 0, 0 } | |
216 }; | |
217 | |
4721 | 218 static uint32_t mach64_vid_get_dbpp( void ) |
219 { | |
220 uint32_t dbpp,retval; | |
221 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; | |
222 switch(dbpp) | |
223 { | |
224 case 1: retval = 4; break; | |
225 case 2: retval = 8; break; | |
226 case 3: retval = 15; break; | |
227 case 4: retval = 16; break; | |
228 case 5: retval = 24; break; | |
229 default: retval=32; break; | |
230 } | |
231 return retval; | |
232 } | |
233 | |
234 static int mach64_is_dbl_scan( void ) | |
235 { | |
236 return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; | |
237 } | |
238 | |
239 static int mach64_is_interlace( void ) | |
240 { | |
241 return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; | |
242 } | |
243 | |
244 static uint32_t mach64_get_xres( void ) | |
245 { | |
246 /* FIXME: currently we extract that from CRTC!!!*/ | |
247 uint32_t xres,h_total; | |
248 h_total = INREG(CRTC_H_TOTAL_DISP); | |
249 xres = (h_total >> 16) & 0xffff; | |
250 return (xres + 1)*8; | |
251 } | |
252 | |
253 static uint32_t mach64_get_yres( void ) | |
254 { | |
255 /* FIXME: currently we extract that from CRTC!!!*/ | |
256 uint32_t yres,v_total; | |
257 v_total = INREG(CRTC_V_TOTAL_DISP); | |
258 yres = (v_total >> 16) & 0xffff; | |
259 return yres + 1; | |
260 } | |
261 | |
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262 // returns the verical stretch factor in 16.16 |
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263 static int mach64_get_vert_stretch(void) |
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264 { |
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265 int lcd_index; |
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266 int vert_stretching; |
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267 int ext_vert_stretch; |
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268 int ret; |
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269 int yres= mach64_get_yres(); |
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270 |
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271 if(!supports_lcd_v_stretch){ |
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272 if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); |
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273 return 1<<16; |
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274 } |
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275 |
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276 lcd_index= INREG(LCD_INDEX); |
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277 |
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278 vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); |
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279 if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; |
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280 else |
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281 { |
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282 int panel_size; |
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283 |
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284 ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); |
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285 panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; |
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286 panel_size++; |
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287 |
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288 ret= ((yres<<16) + (panel_size>>1))/panel_size; |
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289 } |
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290 |
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291 // lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); |
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292 |
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293 OUTREG(LCD_INDEX, lcd_index); |
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294 |
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295 if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); |
4872 | 296 |
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297 return ret; |
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298 } |
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299 |
4721 | 300 static void mach64_vid_make_default() |
301 { | |
4872 | 302 mach64_fifo_wait(5); |
4761 | 303 OUTREG(SCALER_COLOUR_CNTL,0x00101000); |
4872 | 304 |
305 besr.ckey_on=0; | |
306 besr.graphics_key_msk=0; | |
307 besr.graphics_key_clr=0; | |
308 | |
309 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
310 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
311 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
312 | |
4721 | 313 } |
314 | |
315 static void mach64_vid_dump_regs( void ) | |
316 { | |
317 size_t i; | |
318 printf("[mach64] *** Begin of DRIVER variables dump ***\n"); | |
319 printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); | |
320 printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); | |
321 printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); | |
322 printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); | |
323 printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); | |
324 printf("[mach64] *** Begin of OV0 registers dump ***\n"); | |
325 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
326 { | |
327 mach64_wait_for_idle(); | |
328 printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); | |
329 } | |
330 printf("[mach64] *** End of OV0 registers dump ***\n"); | |
331 } | |
332 | |
333 | |
4691 | 334 unsigned int vixGetVersion(void) |
335 { | |
336 return(VIDIX_VERSION); | |
337 } | |
338 | |
339 static unsigned short ati_card_ids[] = | |
340 { | |
341 DEVICE_ATI_215CT_MACH64_CT, | |
342 DEVICE_ATI_210888CX_MACH64_CX, | |
343 DEVICE_ATI_210888ET_MACH64_ET, | |
344 DEVICE_ATI_MACH64_VT, | |
345 DEVICE_ATI_210888GX_MACH64_GX, | |
346 DEVICE_ATI_264LT_MACH64_LT, | |
347 DEVICE_ATI_264VT_MACH64_VT, | |
348 DEVICE_ATI_264VT3_MACH64_VT3, | |
349 DEVICE_ATI_264VT4_MACH64_VT4, | |
350 /**/ | |
351 DEVICE_ATI_3D_RAGE_PRO, | |
352 DEVICE_ATI_3D_RAGE_PRO2, | |
353 DEVICE_ATI_3D_RAGE_PRO3, | |
354 DEVICE_ATI_3D_RAGE_PRO4, | |
355 DEVICE_ATI_RAGE_XC, | |
356 DEVICE_ATI_RAGE_XL_AGP, | |
357 DEVICE_ATI_RAGE_XC_AGP, | |
358 DEVICE_ATI_RAGE_XL, | |
359 DEVICE_ATI_3D_RAGE_PRO5, | |
360 DEVICE_ATI_3D_RAGE_PRO6, | |
361 DEVICE_ATI_RAGE_XL2, | |
362 DEVICE_ATI_RAGE_XC2, | |
363 DEVICE_ATI_3D_RAGE_I_II, | |
364 DEVICE_ATI_3D_RAGE_II, | |
365 DEVICE_ATI_3D_RAGE_IIC, | |
366 DEVICE_ATI_3D_RAGE_IIC2, | |
367 DEVICE_ATI_3D_RAGE_IIC3, | |
368 DEVICE_ATI_3D_RAGE_IIC4, | |
369 DEVICE_ATI_3D_RAGE_LT, | |
370 DEVICE_ATI_3D_RAGE_LT2, | |
371 DEVICE_ATI_3D_RAGE_LT_G, | |
372 DEVICE_ATI_3D_RAGE_LT3, | |
373 DEVICE_ATI_RAGE_MOBILITY_P_M, | |
374 DEVICE_ATI_RAGE_MOBILITY_L, | |
375 DEVICE_ATI_3D_RAGE_LT4, | |
376 DEVICE_ATI_3D_RAGE_LT5, | |
377 DEVICE_ATI_RAGE_MOBILITY_P_M2, | |
378 DEVICE_ATI_RAGE_MOBILITY_L2 | |
379 }; | |
380 | |
381 static int find_chip(unsigned chip_id) | |
382 { | |
383 unsigned i; | |
384 for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) | |
385 { | |
386 if(chip_id == ati_card_ids[i]) return i; | |
387 } | |
388 return -1; | |
389 } | |
390 | |
391 int vixProbe(int verbose,int force) | |
392 { | |
393 pciinfo_t lst[MAX_PCI_DEVICES]; | |
394 unsigned i,num_pci; | |
395 int err; | |
396 __verbose = verbose; | |
397 err = pci_scan(lst,&num_pci); | |
398 if(err) | |
399 { | |
400 printf("[mach64] Error occured during pci scan: %s\n",strerror(err)); | |
401 return err; | |
402 } | |
403 else | |
404 { | |
405 err = ENXIO; | |
406 for(i=0;i<num_pci;i++) | |
407 { | |
408 if(lst[i].vendor == VENDOR_ATI) | |
409 { | |
410 int idx; | |
411 const char *dname; | |
412 idx = find_chip(lst[i].device); | |
413 if(idx == -1 && force == PROBE_NORMAL) continue; | |
414 dname = pci_device_name(VENDOR_ATI,lst[i].device); | |
415 dname = dname ? dname : "Unknown chip"; | |
416 printf("[mach64] Found chip: %s\n",dname); | |
417 if(force > PROBE_NORMAL) | |
418 { | |
419 printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); | |
420 if(idx == -1) | |
421 printf("[mach64] Assuming it as Mach64\n"); | |
422 } | |
423 mach64_cap.device_id = lst[i].device; | |
424 err = 0; | |
425 memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); | |
426 probed=1; | |
427 break; | |
428 } | |
429 } | |
430 } | |
431 if(err && verbose) printf("[mach64] Can't find chip\n"); | |
432 return err; | |
433 } | |
434 | |
4721 | 435 static void reset_regs( void ) |
436 { | |
437 size_t i; | |
438 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
439 { | |
440 mach64_fifo_wait(2); | |
4758 | 441 OUTREG(vregs[i].name,0); |
4721 | 442 } |
443 } | |
444 | |
445 | |
4691 | 446 int vixInit(void) |
447 { | |
448 int err; | |
449 if(!probed) | |
450 { | |
451 printf("[mach64] Driver was not probed but is being initializing\n"); | |
452 return EINTR; | |
453 } | |
5641
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454 if(__verbose>0) printf("[mach64] version %s\n", VERSION); |
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455 |
4721 | 456 if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x4000))==(void *)-1) return ENOMEM; |
457 mach64_wait_for_idle(); | |
4691 | 458 mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; |
459 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; | |
460 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; | |
461 else mach64_ram_size = (mach64_ram_size - 7) * 2048; | |
462 mach64_ram_size *= 0x400; /* KB -> bytes */ | |
463 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; | |
4758 | 464 memset(&besr,0,sizeof(bes_registers_t)); |
4691 | 465 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); |
466 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); | |
467 if(!err) printf("[mach64] Set write-combining type of video memory\n"); | |
4876 | 468 |
469 /* check if planar formats are supported */ | |
470 supports_planar=0; | |
471 mach64_wait_for_idle(); | |
472 mach64_fifo_wait(2); | |
473 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
474 else | |
475 { | |
476 OUTREG(SCALER_BUF0_OFFSET_U, -1); | |
477 | |
478 mach64_wait_vsync(); | |
479 mach64_wait_for_idle(); | |
480 mach64_fifo_wait(2); | |
481 | |
482 if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; | |
483 } | |
484 if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); | |
485 else printf("[mach64] Planar YUV formats are not supported :(\n"); | |
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486 |
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487 if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M |
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488 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 |
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489 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L |
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490 || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) |
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491 supports_lcd_v_stretch=1; |
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492 else |
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493 supports_lcd_v_stretch=0; |
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494 |
4721 | 495 reset_regs(); |
4761 | 496 mach64_vid_make_default(); |
4876 | 497 |
4758 | 498 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4691 | 499 return 0; |
500 } | |
501 | |
502 void vixDestroy(void) | |
503 { | |
504 unmap_phys_mem(mach64_mem_base,mach64_ram_size); | |
4721 | 505 unmap_phys_mem(mach64_mmio_base,0x4000); |
4691 | 506 } |
507 | |
508 int vixGetCapability(vidix_capability_t *to) | |
509 { | |
510 memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); | |
511 return 0; | |
512 } | |
513 | |
4721 | 514 static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) |
515 { | |
516 unsigned pitch,spy,spv,spu; | |
517 spy = spv = spu = 0; | |
518 switch(spitch->y) | |
519 { | |
520 case 16: | |
521 case 32: | |
522 case 64: | |
523 case 128: | |
524 case 256: spy = spitch->y; break; | |
525 default: break; | |
526 } | |
527 switch(spitch->u) | |
528 { | |
529 case 16: | |
530 case 32: | |
531 case 64: | |
532 case 128: | |
533 case 256: spu = spitch->u; break; | |
534 default: break; | |
535 } | |
536 switch(spitch->v) | |
537 { | |
538 case 16: | |
539 case 32: | |
540 case 64: | |
541 case 128: | |
542 case 256: spv = spitch->v; break; | |
543 default: break; | |
544 } | |
545 switch(fourcc) | |
546 { | |
547 /* 4:2:0 */ | |
548 case IMGFMT_IYUV: | |
549 case IMGFMT_YV12: | |
550 case IMGFMT_I420: | |
551 if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; | |
552 else pitch = 32; | |
553 break; | |
4872 | 554 case IMGFMT_YVU9: |
555 if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; | |
556 else pitch = 64; | |
557 break; | |
4721 | 558 default: |
4722
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559 if(spy >= 16) pitch = spy; |
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|
560 else pitch = 16; |
4721 | 561 break; |
562 } | |
563 return pitch; | |
564 } | |
565 | |
566 static void mach64_compute_framesize(vidix_playback_t *info) | |
567 { | |
568 unsigned pitch,awidth; | |
569 pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); | |
570 switch(info->fourcc) | |
571 { | |
572 case IMGFMT_I420: | |
573 case IMGFMT_YV12: | |
574 case IMGFMT_IYUV: | |
575 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
576 info->frame_size = awidth*(info->src.h+info->src.h/2); | |
577 break; | |
4872 | 578 case IMGFMT_YVU9: |
579 awidth = (info->src.w + (pitch-1)) & ~(pitch-1); | |
580 info->frame_size = awidth*(info->src.h+info->src.h/8); | |
581 break; | |
582 // case IMGFMT_RGB32: | |
4721 | 583 case IMGFMT_BGR32: |
584 awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); | |
585 info->frame_size = (awidth*info->src.h); | |
586 break; | |
587 /* YUY2 YVYU, RGB15, RGB16 */ | |
588 default: | |
589 awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); | |
590 info->frame_size = (awidth*info->src.h); | |
591 break; | |
592 } | |
4872 | 593 info->frame_size+=256; // so we have some space for alignment & such |
594 info->frame_size&=~16; | |
4721 | 595 } |
596 | |
597 static void mach64_vid_stop_video( void ) | |
598 { | |
599 mach64_fifo_wait(14); | |
600 OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); | |
601 OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); | |
602 OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); | |
603 OUTREG(SCALER_H_COEFF0, 0x00002000); | |
604 OUTREG(SCALER_H_COEFF1, 0x0D06200D); | |
605 OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); | |
606 OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); | |
607 OUTREG(SCALER_H_COEFF4, 0x0C14140C); | |
608 OUTREG(VIDEO_FORMAT, 0xB000B); | |
609 OUTREG(OVERLAY_TEST, 0x0); | |
610 } | |
611 | |
612 static void mach64_vid_display_video( void ) | |
613 { | |
614 uint32_t vf; | |
615 mach64_fifo_wait(14); | |
616 | |
617 OUTREG(OVERLAY_Y_X_START, besr.y_x_start); | |
618 OUTREG(OVERLAY_Y_X_END, besr.y_x_end); | |
619 OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); | |
620 OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); | |
621 OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); | |
4866 | 622 OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); |
623 OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); | |
624 OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); | |
625 OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); | |
626 OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); | |
627 OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); | |
4876 | 628 mach64_wait_vsync(); |
629 | |
630 mach64_fifo_wait(4); | |
4758 | 631 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); |
4760 | 632 // OVERLAY_SCALE_CNTL bits & what they seem to affect |
633 // bit 0 no effect | |
634 // bit 1 yuv2rgb coeff related | |
635 // bit 2 horizontal interpolation if 0 | |
636 // bit 3 vertical interpolation if 0 | |
4847 | 637 // bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) |
4760 | 638 // bit 5-6 gamma correction |
639 // bit 7 nothing visible if set | |
640 // bit 8-27 no effect | |
641 // bit 28-31 nothing interresting just crashed my system when i played with them :( | |
4847 | 642 |
4721 | 643 mach64_wait_for_idle(); |
644 vf = INREG(VIDEO_FORMAT); | |
4751 | 645 |
646 // Bits 16-19 seem to select the format | |
4769 | 647 // 0x0 dunno behaves strange |
648 // 0x1 dunno behaves strange | |
649 // 0x2 dunno behaves strange | |
650 // 0x3 BGR15 | |
651 // 0x4 BGR16 | |
652 // 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) | |
653 // 0x6 BGR32 | |
654 // 0x7 BGR32 with somehow mixed even / odd pixels ? | |
655 // 0x8 YYYYUVUV | |
656 // 0x9 YVU9 | |
657 // 0xA YV12 | |
658 // 0xB YUY2 | |
659 // 0xC UYVY | |
4847 | 660 // 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) |
4769 | 661 // 0xE dunno behaves strange |
662 // 0xF dunno behaves strange | |
663 // Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) | |
4751 | 664 // the remaining bits seem to have no effect |
665 | |
4769 | 666 |
4721 | 667 switch(besr.fourcc) |
668 { | |
4769 | 669 /* BGR formats */ |
670 case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; | |
671 case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; | |
672 case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; | |
4721 | 673 /* 4:2:0 */ |
674 case IMGFMT_IYUV: | |
675 case IMGFMT_I420: | |
4769 | 676 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; |
4872 | 677 |
678 case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; | |
4721 | 679 /* 4:2:2 */ |
680 case IMGFMT_YVYU: | |
4769 | 681 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; |
4721 | 682 case IMGFMT_YUY2: |
4769 | 683 default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; |
4721 | 684 } |
4758 | 685 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 686 } |
687 | |
688 static int mach64_vid_init_video( vidix_playback_t *config ) | |
689 { | |
4758 | 690 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; |
4721 | 691 int is_420,best_pitch,mpitch; |
4866 | 692 int src_offset_y, src_offset_u, src_offset_v; |
693 unsigned int i; | |
4872 | 694 |
4721 | 695 mach64_vid_stop_video(); |
4866 | 696 /* warning, if left or top are != 0 this will fail, as the framesize is too small then */ |
697 left = config->src.x; | |
698 top = config->src.y; | |
4721 | 699 src_h = config->src.h; |
700 src_w = config->src.w; | |
701 is_420 = 0; | |
702 if(config->fourcc == IMGFMT_YV12 || | |
703 config->fourcc == IMGFMT_I420 || | |
704 config->fourcc == IMGFMT_IYUV) is_420 = 1; | |
705 best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); | |
706 mpitch = best_pitch-1; | |
707 switch(config->fourcc) | |
708 { | |
4872 | 709 case IMGFMT_YVU9: |
4721 | 710 /* 4:2:0 */ |
711 case IMGFMT_IYUV: | |
712 case IMGFMT_YV12: | |
713 case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; | |
714 config->dest.pitch.y = | |
715 config->dest.pitch.u = | |
716 config->dest.pitch.v = best_pitch; | |
4769 | 717 besr.vid_buf_pitch= pitch; |
4721 | 718 break; |
719 /* RGB 4:4:4:4 */ | |
720 case IMGFMT_RGB32: | |
721 case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; | |
722 config->dest.pitch.y = | |
723 config->dest.pitch.u = | |
724 config->dest.pitch.v = best_pitch; | |
4769 | 725 besr.vid_buf_pitch= pitch>>2; |
4721 | 726 break; |
727 /* 4:2:2 */ | |
728 default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ | |
729 pitch = ((src_w*2) + mpitch) & ~mpitch; | |
730 config->dest.pitch.y = | |
731 config->dest.pitch.u = | |
732 config->dest.pitch.v = best_pitch; | |
4769 | 733 besr.vid_buf_pitch= pitch>>1; |
4721 | 734 break; |
735 } | |
736 dest_w = config->dest.w; | |
737 dest_h = config->dest.h; | |
738 besr.fourcc = config->fourcc; | |
739 ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; | |
5792 | 740 #if 0 |
741 { | |
742 int i; | |
743 for(i=0; i<32; i++){ | |
744 printf("%X ", INPLL(i)); | |
745 } | |
746 } | |
747 #endif | |
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748 if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); |
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749 v_inc = src_h * mach64_get_vert_stretch(); |
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750 |
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751 if(mach64_is_interlace()) v_inc<<=1; |
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752 if(mach64_is_dbl_scan() ) v_inc>>=1; |
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753 v_inc>>=4; // convert 16.16 -> 20.12 |
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754 v_inc/= dest_h; |
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755 |
5731 | 756 h_inc = (src_w << (12+ecp)) / dest_w; |
4721 | 757 /* keep everything in 16.16 */ |
758 config->offsets[0] = 0; | |
4866 | 759 for(i=1; i<config->num_frames; i++) |
760 config->offsets[i] = config->offsets[i-1] + config->frame_size; | |
761 | |
4872 | 762 /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) |
763 1. the framesize isnt known as the outer src rectangle dimensions arent known | |
764 2. the mach64 needs aligned addresses so it cant work anyway | |
765 -> so we could shift the outer buffer to compensate that but that would mean | |
766 alignment problems for the code which writes into it | |
767 */ | |
768 | |
4721 | 769 if(is_420) |
770 { | |
4866 | 771 config->offset.y= 0; |
4872 | 772 config->offset.u= (pitch*src_h + 15)&~15; |
773 config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; | |
774 | |
4866 | 775 src_offset_y= config->offset.y + top*pitch + left; |
776 src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); | |
777 src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); | |
4872 | 778 |
4721 | 779 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) |
780 { | |
781 uint32_t tmp; | |
782 tmp = config->offset.u; | |
783 config->offset.u = config->offset.v; | |
784 config->offset.v = tmp; | |
785 } | |
786 } | |
4872 | 787 else if(besr.fourcc == IMGFMT_YVU9) |
788 { | |
789 config->offset.y= 0; | |
790 config->offset.u= (pitch*src_h + 15)&~15; | |
791 config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; | |
792 | |
793 src_offset_y= config->offset.y + top*pitch + left; | |
794 src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); | |
795 src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); | |
796 } | |
4866 | 797 else if(besr.fourcc == IMGFMT_BGR32) |
798 { | |
799 config->offset.y = config->offset.u = config->offset.v = 0; | |
4872 | 800 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); |
4866 | 801 } |
4721 | 802 else |
803 { | |
4866 | 804 config->offset.y = config->offset.u = config->offset.v = 0; |
4872 | 805 src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); |
4866 | 806 } |
807 | |
808 num_mach64_buffers= config->num_frames; | |
809 for(i=0; i<config->num_frames; i++) | |
810 { | |
811 mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; | |
812 mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; | |
813 mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; | |
4721 | 814 } |
815 | |
816 leftUV = (left >> 17) & 15; | |
817 left = (left >> 16) & 15; | |
818 besr.scale_inc = ( h_inc << 16 ) | v_inc; | |
4758 | 819 y_pos = config->dest.y; |
820 if(mach64_is_dbl_scan()) y_pos*=2; | |
821 else | |
822 if(mach64_is_interlace()) y_pos/=2; | |
823 besr.y_x_start = y_pos | (config->dest.x << 16); | |
824 y_pos =config->dest.y + dest_h; | |
825 if(mach64_is_dbl_scan()) y_pos*=2; | |
826 else | |
827 if(mach64_is_interlace()) y_pos/=2; | |
828 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); | |
4721 | 829 besr.height_width = ((src_w - left)<<16) | (src_h - top); |
4769 | 830 |
4721 | 831 return 0; |
832 } | |
833 | |
4876 | 834 static int is_supported_fourcc(uint32_t fourcc) |
4721 | 835 { |
4876 | 836 switch(fourcc) |
837 { | |
838 case IMGFMT_YV12: | |
839 case IMGFMT_I420: | |
840 case IMGFMT_YVU9: | |
841 case IMGFMT_IYUV: | |
842 return supports_planar; | |
843 case IMGFMT_YUY2: | |
844 case IMGFMT_UYVY: | |
845 case IMGFMT_BGR15: | |
846 case IMGFMT_BGR16: | |
847 case IMGFMT_BGR32: | |
848 return 1; | |
849 default: | |
850 return 0; | |
851 } | |
4721 | 852 } |
853 | |
4691 | 854 int vixQueryFourcc(vidix_fourcc_t *to) |
855 { | |
4721 | 856 if(is_supported_fourcc(to->fourcc)) |
857 { | |
858 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
859 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
860 VID_DEPTH_12BPP| VID_DEPTH_15BPP| | |
861 VID_DEPTH_16BPP| VID_DEPTH_24BPP| | |
862 VID_DEPTH_32BPP; | |
4861
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863 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; |
4721 | 864 return 0; |
865 } | |
866 else to->depth = to->flags = 0; | |
4691 | 867 return ENOSYS; |
868 } | |
869 | |
870 int vixConfigPlayback(vidix_playback_t *info) | |
871 { | |
4721 | 872 if(!is_supported_fourcc(info->fourcc)) return ENOSYS; |
4866 | 873 |
4721 | 874 mach64_compute_framesize(info); |
4894
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875 |
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876 if(info->num_frames>4) info->num_frames=4; |
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877 for(;info->num_frames>0; info->num_frames--) |
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878 { |
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879 mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; |
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880 mach64_overlay_offset &= 0xffff0000; |
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881 if(mach64_overlay_offset>0) break; |
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882 } |
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883 if(info->num_frames <= 0) return EINVAL; |
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884 |
4721 | 885 info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; |
886 mach64_vid_init_video(info); | |
887 return 0; | |
4691 | 888 } |
889 | |
890 int vixPlaybackOn(void) | |
891 { | |
4721 | 892 mach64_vid_display_video(); |
893 return 0; | |
4691 | 894 } |
895 | |
896 int vixPlaybackOff(void) | |
897 { | |
4721 | 898 mach64_vid_stop_video(); |
899 return 0; | |
900 } | |
901 | |
4691 | 902 int vixPlaybackFrameSelect(unsigned int frame) |
903 { | |
4721 | 904 uint32_t off[6]; |
4866 | 905 int i; |
906 int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; | |
907 //printf("Selecting frame %d\n", frame); | |
4721 | 908 /* |
909 buf3-5 always should point onto second buffer for better | |
910 deinterlacing and TV-in | |
911 */ | |
4866 | 912 if(num_mach64_buffers==1) return 0; |
913 | |
914 for(i=0; i<3; i++) | |
4721 | 915 { |
4866 | 916 off[i] = mach64_buffer_base[frame][i]; |
917 off[i+3]= mach64_buffer_base[last_frame][i]; | |
918 } | |
4769 | 919 |
4847 | 920 #if 0 // delay routine so the individual frames can be ssen better |
921 { | |
922 volatile int i=0; | |
923 for(i=0; i<10000000; i++); | |
924 } | |
925 #endif | |
4721 | 926 |
927 mach64_wait_for_idle(); | |
928 mach64_fifo_wait(7); | |
4847 | 929 |
4721 | 930 OUTREG(SCALER_BUF0_OFFSET, off[0]); |
931 OUTREG(SCALER_BUF0_OFFSET_U, off[1]); | |
932 OUTREG(SCALER_BUF0_OFFSET_V, off[2]); | |
933 OUTREG(SCALER_BUF1_OFFSET, off[3]); | |
934 OUTREG(SCALER_BUF1_OFFSET_U, off[4]); | |
935 OUTREG(SCALER_BUF1_OFFSET_V, off[5]); | |
4866 | 936 if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering |
937 | |
4758 | 938 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); |
4721 | 939 return 0; |
4691 | 940 } |
4721 | 941 |
942 vidix_video_eq_t equal = | |
943 { | |
944 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | |
945 , | |
946 0, 0, 0, 0, 0, 0, 0, 0 }; | |
947 | |
948 int vixPlaybackGetEq( vidix_video_eq_t * eq) | |
949 { | |
950 memcpy(eq,&equal,sizeof(vidix_video_eq_t)); | |
951 return 0; | |
952 } | |
953 | |
954 int vixPlaybackSetEq( const vidix_video_eq_t * eq) | |
955 { | |
956 int br,sat; | |
957 if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; | |
958 if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; | |
959 if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; | |
960 if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; | |
961 if(eq->cap & VEQ_CAP_RGB_INTENSITY) | |
962 { | |
963 equal.red_intensity = eq->red_intensity; | |
964 equal.green_intensity = eq->green_intensity; | |
965 equal.blue_intensity = eq->blue_intensity; | |
966 } | |
967 equal.flags = eq->flags; | |
968 br = equal.brightness * 64 / 1000; | |
969 if(br < -64) br = -64; if(br > 63) br = 63; | |
970 sat = (equal.saturation + 1000) * 16 / 1000; | |
971 if(sat < 0) sat = 0; if(sat > 31) sat = 31; | |
972 OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); | |
973 return 0; | |
974 } | |
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975 |
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976 int vixGetGrKeys(vidix_grkey_t *grkey) |
601e8a796c38
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977 { |
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978 memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); |
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parents:
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979 return(0); |
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parents:
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980 } |
601e8a796c38
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981 |
601e8a796c38
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982 int vixSetGrKeys(const vidix_grkey_t *grkey) |
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michael
parents:
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983 { |
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984 memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); |
4872 | 985 |
986 if(mach64_grkey.ckey.op == CKEY_TRUE) | |
987 { | |
988 besr.ckey_on=1; | |
989 | |
990 switch(mach64_vid_get_dbpp()) | |
991 { | |
992 case 15: | |
993 besr.graphics_key_msk=0x7FFF; | |
994 besr.graphics_key_clr= | |
995 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
996 | ((mach64_grkey.ckey.green&0xF8)<<2) | |
997 | ((mach64_grkey.ckey.red &0xF8)<<7); | |
998 break; | |
999 case 16: | |
1000 besr.graphics_key_msk=0xFFFF; | |
1001 besr.graphics_key_clr= | |
1002 ((mach64_grkey.ckey.blue &0xF8)>>3) | |
1003 | ((mach64_grkey.ckey.green&0xFC)<<3) | |
1004 | ((mach64_grkey.ckey.red &0xF8)<<8); | |
1005 break; | |
1006 case 24: | |
1007 besr.graphics_key_msk=0xFFFFFF; | |
1008 besr.graphics_key_clr= | |
1009 ((mach64_grkey.ckey.blue &0xFF)) | |
1010 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
1011 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1012 break; | |
1013 case 32: | |
1014 besr.graphics_key_msk=0xFFFFFF; | |
1015 besr.graphics_key_clr= | |
1016 ((mach64_grkey.ckey.blue &0xFF)) | |
1017 | ((mach64_grkey.ckey.green&0xFF)<<8) | |
1018 | ((mach64_grkey.ckey.red &0xFF)<<16); | |
1019 break; | |
1020 default: | |
1021 besr.ckey_on=0; | |
1022 besr.graphics_key_msk=0; | |
1023 besr.graphics_key_clr=0; | |
1024 } | |
1025 } | |
1026 else | |
1027 { | |
1028 besr.ckey_on=0; | |
1029 besr.graphics_key_msk=0; | |
1030 besr.graphics_key_clr=0; | |
1031 } | |
1032 | |
1033 mach64_fifo_wait(4); | |
1034 OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); | |
1035 OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); | |
1036 // OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); | |
1037 // OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); | |
1038 if(besr.ckey_on) | |
1039 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); | |
1040 else | |
1041 OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); | |
1042 | |
4861
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1043 return(0); |
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1044 } |