Mercurial > mplayer.hg
annotate cpudetect.c @ 32334:541a774ce8e4
Drop removal of AAC encoder from list of FFmpeg encoders.
The original reason to drop this particular encoder, that it
failed to build on many platforms, should no longer be the case.
author | diego |
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date | Fri, 01 Oct 2010 16:04:43 +0000 |
parents | f3aed7bffcbb |
children | fdf3f93c2828 |
rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
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19 #include "config.h" |
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20 #include "cpudetect.h" |
5937 | 21 #include "mp_msg.h" |
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22 |
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23 CpuCaps gCpuCaps; |
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24 |
3837 | 25 #include <stdlib.h> |
26 | |
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27 #if ARCH_X86 |
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28 |
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29 #include <stdio.h> |
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30 #include <string.h> |
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31 |
12143 | 32 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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33 #include <sys/param.h> |
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34 #include <sys/sysctl.h> |
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35 #include <machine/cpu.h> |
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36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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37 #include <sys/types.h> |
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38 #include <sys/sysctl.h> |
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39 #elif defined(__linux__) |
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40 #include <signal.h> |
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41 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 42 #include <windows.h> |
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43 #elif defined(__OS2__) |
26061 | 44 #define INCL_DOS |
45 #include <os2.h> | |
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46 #elif defined(__AMIGAOS4__) |
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47 #include <proto/exec.h> |
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48 #endif |
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49 |
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50 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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51 * help understanding how to use it. Thanks to the Mesa |
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52 * team for SSE support detection and more cpu detect code. |
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53 */ |
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54 |
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55 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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56 |
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57 static void check_os_katmai_support( void ); |
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58 |
2272 | 59 // return TRUE if cpuid supported |
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60 static int has_cpuid(void) |
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61 { |
2272 | 62 // code from libavcodec: |
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63 #if ARCH_X86_64 |
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64 return 1; |
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65 #else |
31077 | 66 long a, c; |
67 __asm__ volatile ( | |
68 /* See if CPUID instruction is supported ... */ | |
69 /* ... Get copies of EFLAGS into eax and ecx */ | |
70 "pushfl\n\t" | |
71 "pop %0\n\t" | |
72 "mov %0, %1\n\t" | |
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73 |
31077 | 74 /* ... Toggle the ID bit in one copy and store */ |
75 /* to the EFLAGS reg */ | |
76 "xor $0x200000, %0\n\t" | |
77 "push %0\n\t" | |
78 "popfl\n\t" | |
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79 |
31077 | 80 /* ... Get the (hopefully modified) EFLAGS */ |
81 "pushfl\n\t" | |
82 "pop %0\n\t" | |
83 : "=a" (a), "=c" (c) | |
84 : | |
85 : "cc" | |
86 ); | |
2272 | 87 |
31077 | 88 return a != c; |
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89 #endif |
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90 } |
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91 |
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92 void |
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93 do_cpuid(unsigned int ax, unsigned int *p) |
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94 { |
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96 __asm__ volatile |
31077 | 97 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 98 "cpuid\n\t" |
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99 "xchg %%"REG_b", %%"REG_S |
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100 : "=a" (p[0]), "=S" (p[1]), |
2272 | 101 "=c" (p[2]), "=d" (p[3]) |
102 : "0" (ax)); | |
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103 } |
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104 |
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105 void GetCpuCaps( CpuCaps *caps) |
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106 { |
31077 | 107 unsigned int regs[4]; |
108 unsigned int regs2[4]; | |
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109 |
31077 | 110 memset(caps, 0, sizeof(*caps)); |
111 caps->isX86=1; | |
112 caps->cl_size=32; /* default */ | |
113 if (!has_cpuid()) { | |
114 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); | |
115 return; | |
116 } | |
117 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
118 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", | |
119 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
120 if (regs[0]>=0x00000001) | |
121 { | |
122 char *tmpstr, *ptmpstr; | |
123 unsigned cl_size; | |
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124 |
31077 | 125 do_cpuid(0x00000001, regs2); |
2301 | 126 |
31077 | 127 caps->cpuType=(regs2[0] >> 8)&0xf; |
128 caps->cpuModel=(regs2[0] >> 4)&0xf; | |
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129 |
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130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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131 // System Instructions, Table 3-2: Effective family computation, page 120. |
31077 | 132 if(caps->cpuType==0xf){ |
133 // use extended family (P4, IA64, K8) | |
134 caps->cpuType=0xf+((regs2[0]>>20)&255); | |
135 } | |
136 if(caps->cpuType==0xf || caps->cpuType==6) | |
137 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; | |
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138 |
31077 | 139 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 140 |
31077 | 141 // general feature flags: |
142 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 | |
143 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
144 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
145 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
146 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 | |
147 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 | |
148 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too | |
149 cl_size = ((regs2[1] >> 8) & 0xFF)*8; | |
150 if(cl_size) caps->cl_size = cl_size; | |
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151 |
31077 | 152 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
153 while(*ptmpstr == ' ') // strip leading spaces | |
154 ptmpstr++; | |
155 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); | |
156 free(tmpstr); | |
157 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", | |
158 caps->cpuType, caps->cpuModel, caps->cpuStepping); | |
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159 |
31077 | 160 } |
161 do_cpuid(0x80000000, regs); | |
162 if (regs[0]>=0x80000001) { | |
163 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
164 do_cpuid(0x80000001, regs2); | |
165 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
166 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
167 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 | |
168 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
169 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 | |
170 } | |
171 if(regs[0]>=0x80000006) | |
172 { | |
173 do_cpuid(0x80000006, regs2); | |
174 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
175 caps->cl_size = regs2[2] & 0xFF; | |
176 } | |
177 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 178 #if 0 |
31077 | 179 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
180 gCpuCaps.hasMMX, | |
181 gCpuCaps.hasMMX2, | |
182 gCpuCaps.hasSSE, | |
183 gCpuCaps.hasSSE2, | |
184 gCpuCaps.has3DNow, | |
185 gCpuCaps.has3DNowExt); | |
2288 | 186 #endif |
187 | |
31077 | 188 /* FIXME: Does SSE2 need more OS support, too? */ |
189 if (caps->hasSSE) | |
190 check_os_katmai_support(); | |
191 if (!caps->hasSSE) | |
192 caps->hasSSE2 = 0; | |
193 // caps->has3DNow=1; | |
194 // caps->hasMMX2 = 0; | |
195 // caps->hasMMX = 0; | |
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196 |
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197 #if !CONFIG_RUNTIME_CPUDETECT |
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198 #if !HAVE_MMX |
31077 | 199 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
200 caps->hasMMX=0; | |
4829 | 201 #endif |
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202 #if !HAVE_MMX2 |
31077 | 203 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
204 caps->hasMMX2=0; | |
4829 | 205 #endif |
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206 #if !HAVE_SSE |
31077 | 207 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
208 caps->hasSSE=0; | |
4829 | 209 #endif |
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210 #if !HAVE_SSE2 |
31077 | 211 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
212 caps->hasSSE2=0; | |
4829 | 213 #endif |
28335 | 214 #if !HAVE_AMD3DNOW |
31077 | 215 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
216 caps->has3DNow=0; | |
4829 | 217 #endif |
28335 | 218 #if !HAVE_AMD3DNOWEXT |
31077 | 219 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
220 caps->has3DNowExt=0; | |
4829 | 221 #endif |
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222 #endif // CONFIG_RUNTIME_CPUDETECT |
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223 } |
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224 |
2301 | 225 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
31077 | 226 char vendor[13]; |
227 char *retname; | |
228 int i; | |
2301 | 229 |
31077 | 230 if (NULL==(retname=malloc(256))) { |
231 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); | |
232 exit(1); | |
233 } | |
234 retname[0] = '\0'; | |
2303 | 235 |
31077 | 236 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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237 |
31077 | 238 do_cpuid(0x80000000,regs); |
239 if (regs[0] >= 0x80000004) | |
240 { | |
241 // CPU has built-in namestring | |
242 for (i = 0x80000002; i <= 0x80000004; i++) | |
243 { | |
244 do_cpuid(i, regs); | |
245 strncat(retname, (char*)regs, 16); | |
246 } | |
247 } | |
248 return retname; | |
2301 | 249 } |
250 | |
28295 | 251 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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252 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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253 { |
6134 | 254 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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255 |
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256 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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257 * instructions are 3 bytes long. We must increment the instruction |
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258 * pointer manually to avoid repeated execution of the offending |
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259 * instruction. |
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260 * |
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261 * If the SIGILL is caused by a divide-by-zero when unmasked |
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262 * exceptions aren't supported, the SIMD FPU status and control |
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263 * word will be restored at the end of the test, so we don't need |
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264 * to worry about doing it here. Besides, we may not be able to... |
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265 */ |
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266 sc.eip += 3; |
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267 |
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268 gCpuCaps.hasSSE=0; |
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269 } |
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270 #endif /* __linux__ && _POSIX_SOURCE */ |
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271 |
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272 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
10440 | 273 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
274 { | |
31077 | 275 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ |
276 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
277 ep->ContextRecord->Eip +=3; | |
278 gCpuCaps.hasSSE=0; | |
279 return EXCEPTION_CONTINUE_EXECUTION; | |
280 } | |
281 return EXCEPTION_CONTINUE_SEARCH; | |
10440 | 282 } |
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283 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 284 |
26061 | 285 #ifdef __OS2__ |
31077 | 286 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1, |
287 PEXCEPTIONREGISTRATIONRECORD p2, | |
288 PCONTEXTRECORD p3, | |
289 PVOID p4) | |
26061 | 290 { |
31077 | 291 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ |
292 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
26061 | 293 |
31077 | 294 p3->ctx_RegEip += 3; |
295 gCpuCaps.hasSSE = 0; | |
26061 | 296 |
31077 | 297 return XCPT_CONTINUE_EXECUTION; |
298 } | |
299 return XCPT_CONTINUE_SEARCH; | |
26061 | 300 } |
301 #endif | |
302 | |
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303 /* If we're running on a processor that can do SSE, let's see if we |
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304 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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305 * haven't been configured for a Pentium III but are running on one, |
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306 * and RedHat patched 2.2 kernels that have broken exception handling |
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307 * support for user space apps that do SSE. |
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308 */ |
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309 |
21848 | 310 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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311 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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312 #elif defined(__APPLE__) |
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313 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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314 #endif |
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315 |
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316 static void check_os_katmai_support( void ) |
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317 { |
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318 #if ARCH_X86_64 |
31077 | 319 gCpuCaps.hasSSE=1; |
320 gCpuCaps.hasSSE2=1; | |
21848 | 321 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
31077 | 322 int has_sse=0, ret; |
323 size_t len=sizeof(has_sse); | |
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324 |
31077 | 325 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
326 if (ret || !has_sse) | |
327 gCpuCaps.hasSSE=0; | |
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328 |
12143 | 329 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
330 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
31077 | 331 int has_sse, has_sse2, ret, mib[2]; |
332 size_t varlen; | |
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333 |
31077 | 334 mib[0] = CTL_MACHDEP; |
335 mib[1] = CPU_SSE; | |
336 varlen = sizeof(has_sse); | |
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337 |
31077 | 338 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
339 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); | |
340 gCpuCaps.hasSSE = ret >= 0 && has_sse; | |
341 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); | |
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342 |
31077 | 343 mib[1] = CPU_SSE2; |
344 varlen = sizeof(has_sse2); | |
345 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); | |
346 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); | |
347 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; | |
348 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); | |
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349 #else |
31077 | 350 gCpuCaps.hasSSE = 0; |
351 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); | |
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352 #endif |
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353 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
31077 | 354 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
355 if ( gCpuCaps.hasSSE ) { | |
356 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
357 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
358 __asm__ volatile ("xorps %xmm0, %xmm0"); | |
359 SetUnhandledExceptionFilter(exc_fil); | |
360 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); | |
361 } | |
26061 | 362 #elif defined(__OS2__) |
31077 | 363 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; |
364 if ( gCpuCaps.hasSSE ) { | |
365 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
366 DosSetExceptionHandler( &RegRec ); | |
367 __asm__ volatile ("xorps %xmm0, %xmm0"); | |
368 DosUnsetExceptionHandler( &RegRec ); | |
369 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); | |
370 } | |
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371 #elif defined(__linux__) |
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372 #if defined(_POSIX_SOURCE) |
31077 | 373 struct sigaction saved_sigill; |
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374 |
31077 | 375 /* Save the original signal handlers. |
376 */ | |
377 sigaction( SIGILL, NULL, &saved_sigill ); | |
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378 |
31077 | 379 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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380 |
31077 | 381 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
382 * supports the extended FPU save and restore required for SSE. If | |
383 * we execute an SSE instruction on a PIII and get a SIGILL, the OS | |
384 * doesn't support Streaming SIMD Exceptions, even if the processor | |
385 * does. | |
386 */ | |
387 if ( gCpuCaps.hasSSE ) { | |
388 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
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389 |
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390 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
31077 | 391 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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392 |
31077 | 393 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
394 } | |
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395 |
31077 | 396 /* Restore the original signal handlers. |
397 */ | |
398 sigaction( SIGILL, &saved_sigill, NULL ); | |
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399 |
31077 | 400 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
401 * safe to go ahead and hook out the SSE code throughout Mesa. | |
402 */ | |
403 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); | |
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404 #else |
31077 | 405 /* We can't use POSIX signal handling to test the availability of |
406 * SSE, so we disable it by default. | |
407 */ | |
408 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); | |
409 gCpuCaps.hasSSE=0; | |
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410 #endif /* _POSIX_SOURCE */ |
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411 #else |
31077 | 412 /* Do nothing on other platforms for now. |
413 */ | |
414 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); | |
415 gCpuCaps.hasSSE=0; | |
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416 #endif /* __linux__ */ |
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417 } |
20577 | 418 #else /* ARCH_X86 */ |
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419 |
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420 #ifdef __APPLE__ |
9003 | 421 #include <sys/sysctl.h> |
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422 #elif defined(__AMIGAOS4__) |
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423 /* nothing */ |
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424 #else |
9003 | 425 #include <signal.h> |
426 #include <setjmp.h> | |
427 | |
428 static sigjmp_buf jmpbuf; | |
429 static volatile sig_atomic_t canjump = 0; | |
430 | |
431 static void sigill_handler (int sig) | |
432 { | |
433 if (!canjump) { | |
434 signal (sig, SIG_DFL); | |
435 raise (sig); | |
436 } | |
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437 |
9003 | 438 canjump = 0; |
439 siglongjmp (jmpbuf, 1); | |
440 } | |
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441 #endif /* __APPLE__ */ |
9003 | 442 |
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443 void GetCpuCaps( CpuCaps *caps) |
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444 { |
31077 | 445 caps->cpuType=0; |
446 caps->cpuModel=0; | |
447 caps->cpuStepping=0; | |
448 caps->hasMMX=0; | |
449 caps->hasMMX2=0; | |
450 caps->has3DNow=0; | |
451 caps->has3DNowExt=0; | |
452 caps->hasSSE=0; | |
453 caps->hasSSE2=0; | |
454 caps->hasSSE3=0; | |
455 caps->hasSSSE3=0; | |
456 caps->hasSSE4a=0; | |
457 caps->isX86=0; | |
458 caps->hasAltiVec = 0; | |
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459 #if HAVE_ALTIVEC |
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460 #ifdef __APPLE__ |
9003 | 461 /* |
462 rip-off from ffmpeg altivec detection code. | |
463 this code also appears on Apple's AltiVec pages. | |
464 */ | |
31077 | 465 { |
466 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
467 int has_vu = 0; | |
468 size_t len = sizeof(has_vu); | |
469 int err; | |
9003 | 470 |
31077 | 471 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 472 |
31077 | 473 if (err == 0) |
474 if (has_vu != 0) | |
475 caps->hasAltiVec = 1; | |
476 } | |
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477 #elif defined(__AMIGAOS4__) |
31077 | 478 ULONG result = 0; |
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add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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479 |
31077 | 480 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
481 if (result == VECTORTYPE_ALTIVEC) | |
482 caps->hasAltiVec = 1; | |
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add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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483 #else |
9003 | 484 /* no Darwin, do it the brute-force way */ |
485 /* this is borrowed from the libmpeg2 library */ | |
31077 | 486 { |
487 signal (SIGILL, sigill_handler); | |
488 if (sigsetjmp (jmpbuf, 1)) { | |
9003 | 489 signal (SIGILL, SIG_DFL); |
31077 | 490 } else { |
9003 | 491 canjump = 1; |
29263
0f1b5b68af32
whitespace cosmetics: Remove all trailing whitespace.
diego
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492 |
31077 | 493 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 494 "vand %%v0, %%v0, %%v0" |
9003 | 495 : |
496 : "r" (-1)); | |
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whitespace cosmetics: Remove all trailing whitespace.
diego
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497 |
31077 | 498 signal (SIGILL, SIG_DFL); |
499 caps->hasAltiVec = 1; | |
9003 | 500 } |
31077 | 501 } |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
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502 #endif /* __APPLE__ */ |
31077 | 503 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 504 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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505 |
31077 | 506 if (ARCH_IA64) |
507 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); | |
11962
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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508 |
31077 | 509 if (ARCH_SPARC) |
510 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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10955
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changeset
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511 |
31077 | 512 if (ARCH_ARM) |
513 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); | |
11962
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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514 |
31077 | 515 if (ARCH_PPC) |
516 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); | |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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517 |
31077 | 518 if (ARCH_ALPHA) |
519 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); | |
11962
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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changeset
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520 |
31077 | 521 if (ARCH_MIPS) |
522 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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523 |
31077 | 524 if (ARCH_PA_RISC) |
525 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); | |
11962
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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changeset
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526 |
31077 | 527 if (ARCH_S390) |
528 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); | |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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changeset
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529 |
31077 | 530 if (ARCH_S390X) |
531 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); | |
11962
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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532 |
31077 | 533 if (ARCH_VAX) |
534 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); | |
25340 | 535 |
31077 | 536 if (ARCH_XTENSA) |
537 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); | |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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2417
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538 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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539 #endif /* !ARCH_X86 */ |