Mercurial > mplayer.hg
annotate cpudetect.c @ 31666:796b778e2411
Enable robust resync for mpg123 decoder.
This prevents the decoder from giving up give after long pieces of invalid
data, for example during transmission errors with DVB-T and similar.
patch by Thomas Orgis, thomas-forum orgis org
author | diego |
---|---|
date | Tue, 13 Jul 2010 15:11:34 +0000 |
parents | dd7f15a3fb1b |
children | 544f29a58a6b |
rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
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19 #include "config.h" |
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20 #include "cpudetect.h" |
5937 | 21 #include "mp_msg.h" |
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22 |
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23 CpuCaps gCpuCaps; |
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24 |
3837 | 25 #include <stdlib.h> |
26 | |
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27 #if ARCH_X86 |
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28 |
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29 #include <stdio.h> |
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30 #include <string.h> |
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31 |
12143 | 32 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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33 #include <sys/param.h> |
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34 #include <sys/sysctl.h> |
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35 #include <machine/cpu.h> |
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36 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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37 #include <sys/types.h> |
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38 #include <sys/sysctl.h> |
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39 #elif defined(__linux__) |
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40 #include <signal.h> |
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41 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 42 #include <windows.h> |
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43 #elif defined(__OS2__) |
26061 | 44 #define INCL_DOS |
45 #include <os2.h> | |
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46 #elif defined(__AMIGAOS4__) |
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47 #include <proto/exec.h> |
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48 #endif |
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49 |
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50 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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51 * help understanding how to use it. Thanks to the Mesa |
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52 * team for SSE support detection and more cpu detect code. |
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53 */ |
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54 |
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55 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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56 |
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57 static void check_os_katmai_support( void ); |
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58 |
2272 | 59 // return TRUE if cpuid supported |
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60 static int has_cpuid(void) |
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61 { |
2272 | 62 // code from libavcodec: |
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63 #if ARCH_X86_64 |
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64 return 1; |
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65 #else |
31077 | 66 long a, c; |
67 __asm__ volatile ( | |
68 /* See if CPUID instruction is supported ... */ | |
69 /* ... Get copies of EFLAGS into eax and ecx */ | |
70 "pushfl\n\t" | |
71 "pop %0\n\t" | |
72 "mov %0, %1\n\t" | |
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73 |
31077 | 74 /* ... Toggle the ID bit in one copy and store */ |
75 /* to the EFLAGS reg */ | |
76 "xor $0x200000, %0\n\t" | |
77 "push %0\n\t" | |
78 "popfl\n\t" | |
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79 |
31077 | 80 /* ... Get the (hopefully modified) EFLAGS */ |
81 "pushfl\n\t" | |
82 "pop %0\n\t" | |
83 : "=a" (a), "=c" (c) | |
84 : | |
85 : "cc" | |
86 ); | |
2272 | 87 |
31077 | 88 return a != c; |
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89 #endif |
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90 } |
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91 |
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92 static void |
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93 do_cpuid(unsigned int ax, unsigned int *p) |
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94 { |
2272 | 95 #if 0 |
31077 | 96 __asm__ volatile( |
97 "cpuid;" | |
98 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) | |
99 : "0" (ax) | |
100 ); | |
2272 | 101 #else |
102 // code from libavcodec: | |
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103 __asm__ volatile |
31077 | 104 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 105 "cpuid\n\t" |
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106 "xchg %%"REG_b", %%"REG_S |
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107 : "=a" (p[0]), "=S" (p[1]), |
2272 | 108 "=c" (p[2]), "=d" (p[3]) |
109 : "0" (ax)); | |
110 #endif | |
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111 } |
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112 |
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113 void GetCpuCaps( CpuCaps *caps) |
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114 { |
31077 | 115 unsigned int regs[4]; |
116 unsigned int regs2[4]; | |
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117 |
31077 | 118 memset(caps, 0, sizeof(*caps)); |
119 caps->isX86=1; | |
120 caps->cl_size=32; /* default */ | |
121 if (!has_cpuid()) { | |
122 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); | |
123 return; | |
124 } | |
125 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
126 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", | |
127 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
128 if (regs[0]>=0x00000001) | |
129 { | |
130 char *tmpstr, *ptmpstr; | |
131 unsigned cl_size; | |
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132 |
31077 | 133 do_cpuid(0x00000001, regs2); |
2301 | 134 |
31077 | 135 caps->cpuType=(regs2[0] >> 8)&0xf; |
136 caps->cpuModel=(regs2[0] >> 4)&0xf; | |
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137 |
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138 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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139 // System Instructions, Table 3-2: Effective family computation, page 120. |
31077 | 140 if(caps->cpuType==0xf){ |
141 // use extended family (P4, IA64, K8) | |
142 caps->cpuType=0xf+((regs2[0]>>20)&255); | |
143 } | |
144 if(caps->cpuType==0xf || caps->cpuType==6) | |
145 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; | |
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146 |
31077 | 147 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 148 |
31077 | 149 // general feature flags: |
150 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 | |
151 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
152 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
153 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
154 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 | |
155 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 | |
156 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too | |
157 cl_size = ((regs2[1] >> 8) & 0xFF)*8; | |
158 if(cl_size) caps->cl_size = cl_size; | |
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159 |
31077 | 160 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
161 while(*ptmpstr == ' ') // strip leading spaces | |
162 ptmpstr++; | |
163 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); | |
164 free(tmpstr); | |
165 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", | |
166 caps->cpuType, caps->cpuModel, caps->cpuStepping); | |
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167 |
31077 | 168 } |
169 do_cpuid(0x80000000, regs); | |
170 if (regs[0]>=0x80000001) { | |
171 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
172 do_cpuid(0x80000001, regs2); | |
173 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
174 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
175 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 | |
176 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
177 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 | |
178 } | |
179 if(regs[0]>=0x80000006) | |
180 { | |
181 do_cpuid(0x80000006, regs2); | |
182 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
183 caps->cl_size = regs2[2] & 0xFF; | |
184 } | |
185 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 186 #if 0 |
31077 | 187 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
188 gCpuCaps.hasMMX, | |
189 gCpuCaps.hasMMX2, | |
190 gCpuCaps.hasSSE, | |
191 gCpuCaps.hasSSE2, | |
192 gCpuCaps.has3DNow, | |
193 gCpuCaps.has3DNowExt); | |
2288 | 194 #endif |
195 | |
31077 | 196 /* FIXME: Does SSE2 need more OS support, too? */ |
197 if (caps->hasSSE) | |
198 check_os_katmai_support(); | |
199 if (!caps->hasSSE) | |
200 caps->hasSSE2 = 0; | |
201 // caps->has3DNow=1; | |
202 // caps->hasMMX2 = 0; | |
203 // caps->hasMMX = 0; | |
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204 |
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205 #if !CONFIG_RUNTIME_CPUDETECT |
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206 #if !HAVE_MMX |
31077 | 207 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
208 caps->hasMMX=0; | |
4829 | 209 #endif |
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210 #if !HAVE_MMX2 |
31077 | 211 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
212 caps->hasMMX2=0; | |
4829 | 213 #endif |
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214 #if !HAVE_SSE |
31077 | 215 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
216 caps->hasSSE=0; | |
4829 | 217 #endif |
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218 #if !HAVE_SSE2 |
31077 | 219 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
220 caps->hasSSE2=0; | |
4829 | 221 #endif |
28335 | 222 #if !HAVE_AMD3DNOW |
31077 | 223 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
224 caps->has3DNow=0; | |
4829 | 225 #endif |
28335 | 226 #if !HAVE_AMD3DNOWEXT |
31077 | 227 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
228 caps->has3DNowExt=0; | |
4829 | 229 #endif |
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230 #endif // CONFIG_RUNTIME_CPUDETECT |
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231 } |
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232 |
2301 | 233 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
31077 | 234 char vendor[13]; |
235 char *retname; | |
236 int i; | |
2301 | 237 |
31077 | 238 if (NULL==(retname=malloc(256))) { |
239 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); | |
240 exit(1); | |
241 } | |
242 retname[0] = '\0'; | |
2303 | 243 |
31077 | 244 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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245 |
31077 | 246 do_cpuid(0x80000000,regs); |
247 if (regs[0] >= 0x80000004) | |
248 { | |
249 // CPU has built-in namestring | |
250 for (i = 0x80000002; i <= 0x80000004; i++) | |
251 { | |
252 do_cpuid(i, regs); | |
253 strncat(retname, (char*)regs, 16); | |
254 } | |
255 } | |
256 return retname; | |
2301 | 257 } |
258 | |
28295 | 259 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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260 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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261 { |
6134 | 262 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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263 |
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264 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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265 * instructions are 3 bytes long. We must increment the instruction |
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266 * pointer manually to avoid repeated execution of the offending |
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267 * instruction. |
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268 * |
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269 * If the SIGILL is caused by a divide-by-zero when unmasked |
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270 * exceptions aren't supported, the SIMD FPU status and control |
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271 * word will be restored at the end of the test, so we don't need |
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272 * to worry about doing it here. Besides, we may not be able to... |
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273 */ |
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274 sc.eip += 3; |
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275 |
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276 gCpuCaps.hasSSE=0; |
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277 } |
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278 #endif /* __linux__ && _POSIX_SOURCE */ |
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279 |
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280 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
10440 | 281 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
282 { | |
31077 | 283 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ |
284 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
285 ep->ContextRecord->Eip +=3; | |
286 gCpuCaps.hasSSE=0; | |
287 return EXCEPTION_CONTINUE_EXECUTION; | |
288 } | |
289 return EXCEPTION_CONTINUE_SEARCH; | |
10440 | 290 } |
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291 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 292 |
26061 | 293 #ifdef __OS2__ |
31077 | 294 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1, |
295 PEXCEPTIONREGISTRATIONRECORD p2, | |
296 PCONTEXTRECORD p3, | |
297 PVOID p4) | |
26061 | 298 { |
31077 | 299 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ |
300 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
26061 | 301 |
31077 | 302 p3->ctx_RegEip += 3; |
303 gCpuCaps.hasSSE = 0; | |
26061 | 304 |
31077 | 305 return XCPT_CONTINUE_EXECUTION; |
306 } | |
307 return XCPT_CONTINUE_SEARCH; | |
26061 | 308 } |
309 #endif | |
310 | |
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311 /* If we're running on a processor that can do SSE, let's see if we |
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312 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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313 * haven't been configured for a Pentium III but are running on one, |
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314 * and RedHat patched 2.2 kernels that have broken exception handling |
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315 * support for user space apps that do SSE. |
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316 */ |
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317 |
21848 | 318 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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319 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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320 #elif defined(__APPLE__) |
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321 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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322 #endif |
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323 |
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324 static void check_os_katmai_support( void ) |
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325 { |
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326 #if ARCH_X86_64 |
31077 | 327 gCpuCaps.hasSSE=1; |
328 gCpuCaps.hasSSE2=1; | |
21848 | 329 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
31077 | 330 int has_sse=0, ret; |
331 size_t len=sizeof(has_sse); | |
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332 |
31077 | 333 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
334 if (ret || !has_sse) | |
335 gCpuCaps.hasSSE=0; | |
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336 |
12143 | 337 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
338 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
31077 | 339 int has_sse, has_sse2, ret, mib[2]; |
340 size_t varlen; | |
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341 |
31077 | 342 mib[0] = CTL_MACHDEP; |
343 mib[1] = CPU_SSE; | |
344 varlen = sizeof(has_sse); | |
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345 |
31077 | 346 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
347 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); | |
348 gCpuCaps.hasSSE = ret >= 0 && has_sse; | |
349 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); | |
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350 |
31077 | 351 mib[1] = CPU_SSE2; |
352 varlen = sizeof(has_sse2); | |
353 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); | |
354 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); | |
355 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; | |
356 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); | |
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357 #else |
31077 | 358 gCpuCaps.hasSSE = 0; |
359 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); | |
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360 #endif |
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361 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
31077 | 362 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
363 if ( gCpuCaps.hasSSE ) { | |
364 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
365 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
366 __asm__ volatile ("xorps %xmm0, %xmm0"); | |
367 SetUnhandledExceptionFilter(exc_fil); | |
368 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); | |
369 } | |
26061 | 370 #elif defined(__OS2__) |
31077 | 371 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; |
372 if ( gCpuCaps.hasSSE ) { | |
373 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
374 DosSetExceptionHandler( &RegRec ); | |
375 __asm__ volatile ("xorps %xmm0, %xmm0"); | |
376 DosUnsetExceptionHandler( &RegRec ); | |
377 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); | |
378 } | |
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379 #elif defined(__linux__) |
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380 #if defined(_POSIX_SOURCE) |
31077 | 381 struct sigaction saved_sigill; |
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382 |
31077 | 383 /* Save the original signal handlers. |
384 */ | |
385 sigaction( SIGILL, NULL, &saved_sigill ); | |
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386 |
31077 | 387 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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388 |
31077 | 389 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
390 * supports the extended FPU save and restore required for SSE. If | |
391 * we execute an SSE instruction on a PIII and get a SIGILL, the OS | |
392 * doesn't support Streaming SIMD Exceptions, even if the processor | |
393 * does. | |
394 */ | |
395 if ( gCpuCaps.hasSSE ) { | |
396 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
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397 |
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398 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
31077 | 399 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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400 |
31077 | 401 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
402 } | |
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403 |
31077 | 404 /* Restore the original signal handlers. |
405 */ | |
406 sigaction( SIGILL, &saved_sigill, NULL ); | |
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407 |
31077 | 408 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
409 * safe to go ahead and hook out the SSE code throughout Mesa. | |
410 */ | |
411 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); | |
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412 #else |
31077 | 413 /* We can't use POSIX signal handling to test the availability of |
414 * SSE, so we disable it by default. | |
415 */ | |
416 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); | |
417 gCpuCaps.hasSSE=0; | |
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418 #endif /* _POSIX_SOURCE */ |
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419 #else |
31077 | 420 /* Do nothing on other platforms for now. |
421 */ | |
422 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); | |
423 gCpuCaps.hasSSE=0; | |
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424 #endif /* __linux__ */ |
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425 } |
20577 | 426 #else /* ARCH_X86 */ |
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427 |
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428 #ifdef __APPLE__ |
9003 | 429 #include <sys/sysctl.h> |
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430 #elif defined(__AMIGAOS4__) |
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431 /* nothing */ |
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432 #else |
9003 | 433 #include <signal.h> |
434 #include <setjmp.h> | |
435 | |
436 static sigjmp_buf jmpbuf; | |
437 static volatile sig_atomic_t canjump = 0; | |
438 | |
439 static void sigill_handler (int sig) | |
440 { | |
441 if (!canjump) { | |
442 signal (sig, SIG_DFL); | |
443 raise (sig); | |
444 } | |
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445 |
9003 | 446 canjump = 0; |
447 siglongjmp (jmpbuf, 1); | |
448 } | |
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449 #endif /* __APPLE__ */ |
9003 | 450 |
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451 void GetCpuCaps( CpuCaps *caps) |
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452 { |
31077 | 453 caps->cpuType=0; |
454 caps->cpuModel=0; | |
455 caps->cpuStepping=0; | |
456 caps->hasMMX=0; | |
457 caps->hasMMX2=0; | |
458 caps->has3DNow=0; | |
459 caps->has3DNowExt=0; | |
460 caps->hasSSE=0; | |
461 caps->hasSSE2=0; | |
462 caps->hasSSE3=0; | |
463 caps->hasSSSE3=0; | |
464 caps->hasSSE4a=0; | |
465 caps->isX86=0; | |
466 caps->hasAltiVec = 0; | |
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467 #if HAVE_ALTIVEC |
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468 #ifdef __APPLE__ |
9003 | 469 /* |
470 rip-off from ffmpeg altivec detection code. | |
471 this code also appears on Apple's AltiVec pages. | |
472 */ | |
31077 | 473 { |
474 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
475 int has_vu = 0; | |
476 size_t len = sizeof(has_vu); | |
477 int err; | |
9003 | 478 |
31077 | 479 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 480 |
31077 | 481 if (err == 0) |
482 if (has_vu != 0) | |
483 caps->hasAltiVec = 1; | |
484 } | |
28364
3e3bd9da4c7e
Use OS preprocessor checks with '#if defined()' consistently.
diego
parents:
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diff
changeset
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485 #elif defined(__AMIGAOS4__) |
31077 | 486 ULONG result = 0; |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
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487 |
31077 | 488 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
489 if (result == VECTORTYPE_ALTIVEC) | |
490 caps->hasAltiVec = 1; | |
17702
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add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
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changeset
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491 #else |
9003 | 492 /* no Darwin, do it the brute-force way */ |
493 /* this is borrowed from the libmpeg2 library */ | |
31077 | 494 { |
495 signal (SIGILL, sigill_handler); | |
496 if (sigsetjmp (jmpbuf, 1)) { | |
9003 | 497 signal (SIGILL, SIG_DFL); |
31077 | 498 } else { |
9003 | 499 canjump = 1; |
29263
0f1b5b68af32
whitespace cosmetics: Remove all trailing whitespace.
diego
parents:
29114
diff
changeset
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500 |
31077 | 501 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 502 "vand %%v0, %%v0, %%v0" |
9003 | 503 : |
504 : "r" (-1)); | |
29263
0f1b5b68af32
whitespace cosmetics: Remove all trailing whitespace.
diego
parents:
29114
diff
changeset
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505 |
31077 | 506 signal (SIGILL, SIG_DFL); |
507 caps->hasAltiVec = 1; | |
9003 | 508 } |
31077 | 509 } |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
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diff
changeset
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510 #endif /* __APPLE__ */ |
31077 | 511 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 512 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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513 |
31077 | 514 if (ARCH_IA64) |
515 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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516 |
31077 | 517 if (ARCH_SPARC) |
518 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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519 |
31077 | 520 if (ARCH_ARM) |
521 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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522 |
31077 | 523 if (ARCH_PPC) |
524 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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525 |
31077 | 526 if (ARCH_ALPHA) |
527 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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528 |
31077 | 529 if (ARCH_MIPS) |
530 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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531 |
31077 | 532 if (ARCH_PA_RISC) |
533 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
534 |
31077 | 535 if (ARCH_S390) |
536 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
537 |
31077 | 538 if (ARCH_S390X) |
539 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); | |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
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540 |
31077 | 541 if (ARCH_VAX) |
542 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); | |
25340 | 543 |
31077 | 544 if (ARCH_XTENSA) |
545 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); | |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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546 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
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547 #endif /* !ARCH_X86 */ |