Mercurial > mplayer.hg
annotate cpudetect.c @ 36557:7bfdbba6f2f7
menu_param: fix memleak on menu click.
author | reimar |
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date | Sun, 19 Jan 2014 22:24:49 +0000 |
parents | 88c5a06d1db9 |
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rev | line source |
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1 /* |
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2 * This file is part of MPlayer. |
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3 * |
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4 * MPlayer is free software; you can redistribute it and/or modify |
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5 * it under the terms of the GNU General Public License as published by |
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6 * the Free Software Foundation; either version 2 of the License, or |
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7 * (at your option) any later version. |
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8 * |
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9 * MPlayer is distributed in the hope that it will be useful, |
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 * GNU General Public License for more details. |
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13 * |
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14 * You should have received a copy of the GNU General Public License along |
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15 * with MPlayer; if not, write to the Free Software Foundation, Inc., |
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. |
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17 */ |
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18 |
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19 #include "libavutil/x86/asm.h" |
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20 #include "config.h" |
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21 #include "cpudetect.h" |
5937 | 22 #include "mp_msg.h" |
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23 |
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24 CpuCaps gCpuCaps; |
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25 |
3837 | 26 #include <stdlib.h> |
27 | |
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28 #if ARCH_X86 |
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29 |
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30 #include <stdio.h> |
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31 #include <string.h> |
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32 |
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34 #include <sys/param.h> |
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35 #include <sys/sysctl.h> |
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36 #include <machine/cpu.h> |
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37 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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38 #include <sys/types.h> |
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39 #include <sys/sysctl.h> |
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40 #elif defined(__linux__) |
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41 #include <signal.h> |
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42 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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44 #elif defined(__OS2__) |
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46 #include <os2.h> | |
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47 #elif defined(__AMIGAOS4__) |
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48 #include <proto/exec.h> |
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49 #endif |
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50 |
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51 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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52 * help understanding how to use it. Thanks to the Mesa |
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53 * team for SSE support detection and more cpu detect code. |
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54 */ |
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55 |
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56 #if CONFIG_RUNTIME_CPUDETECT |
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57 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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58 |
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59 #if defined(__linux__) && !ARCH_X86_64 |
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60 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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61 { |
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62 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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63 |
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64 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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65 * instructions are 3 bytes long. We must increment the instruction |
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66 * pointer manually to avoid repeated execution of the offending |
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67 * instruction. |
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68 * |
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69 * If the SIGILL is caused by a divide-by-zero when unmasked |
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70 * exceptions aren't supported, the SIMD FPU status and control |
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71 * word will be restored at the end of the test, so we don't need |
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72 * to worry about doing it here. Besides, we may not be able to... |
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73 */ |
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74 sc.eip += 3; |
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75 |
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76 gCpuCaps.hasSSE=0; |
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77 } |
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78 #endif /* __linux__ */ |
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79 |
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80 #if (defined(__MINGW32__) || defined(__CYGWIN__)) && !ARCH_X86_64 |
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81 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
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82 { |
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83 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ |
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84 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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85 ep->ContextRecord->Eip +=3; |
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86 gCpuCaps.hasSSE=0; |
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87 return EXCEPTION_CONTINUE_EXECUTION; |
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88 } |
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89 return EXCEPTION_CONTINUE_SEARCH; |
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90 } |
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91 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
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92 |
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93 #ifdef __OS2__ |
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94 ULONG _System os2_sig_handler_sse(PEXCEPTIONREPORTRECORD p1, |
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95 PEXCEPTIONREGISTRATIONRECORD p2, |
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96 PCONTEXTRECORD p3, |
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97 PVOID p4) |
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98 { |
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99 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ |
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100 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); |
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101 |
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102 p3->ctx_RegEip += 3; |
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103 gCpuCaps.hasSSE = 0; |
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104 |
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105 return XCPT_CONTINUE_EXECUTION; |
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106 } |
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107 return XCPT_CONTINUE_SEARCH; |
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108 } |
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109 #endif |
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110 |
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111 /* If we're running on a processor that can do SSE, let's see if we |
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112 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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113 * haven't been configured for a Pentium III but are running on one, |
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114 * and RedHat patched 2.2 kernels that have broken exception handling |
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115 * support for user space apps that do SSE. |
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116 */ |
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117 |
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118 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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119 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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120 #elif defined(__APPLE__) |
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121 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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122 #endif |
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123 |
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124 static void check_os_katmai_support( void ) |
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125 { |
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126 #if ARCH_X86_64 |
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127 gCpuCaps.hasSSE=1; |
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128 gCpuCaps.hasSSE2=1; |
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129 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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130 int has_sse=0, ret; |
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131 size_t len=sizeof(has_sse); |
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132 |
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133 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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134 if (ret || !has_sse) |
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135 gCpuCaps.hasSSE=0; |
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136 |
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137 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
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138 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) |
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139 int has_sse, has_sse2, ret, mib[2]; |
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140 size_t varlen; |
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141 |
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142 mib[0] = CTL_MACHDEP; |
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143 mib[1] = CPU_SSE; |
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144 varlen = sizeof(has_sse); |
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145 |
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146 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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147 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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148 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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149 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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150 |
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151 mib[1] = CPU_SSE2; |
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152 varlen = sizeof(has_sse2); |
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153 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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154 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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155 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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156 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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157 #else |
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158 gCpuCaps.hasSSE = 0; |
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159 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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160 #endif |
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161 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
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162 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
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163 if ( gCpuCaps.hasSSE ) { |
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164 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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165 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); |
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166 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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167 SetUnhandledExceptionFilter(exc_fil); |
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168 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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169 } |
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170 #elif defined(__OS2__) |
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171 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; |
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172 if ( gCpuCaps.hasSSE ) { |
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173 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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174 DosSetExceptionHandler( &RegRec ); |
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175 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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176 DosUnsetExceptionHandler( &RegRec ); |
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177 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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178 } |
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179 #elif defined(__linux__) |
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180 struct sigaction saved_sigill; |
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181 |
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182 /* Save the original signal handlers. |
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183 */ |
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184 sigaction( SIGILL, NULL, &saved_sigill ); |
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185 |
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186 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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187 |
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188 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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189 * supports the extended FPU save and restore required for SSE. If |
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190 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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191 * doesn't support Streaming SIMD Exceptions, even if the processor |
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192 * does. |
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193 */ |
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194 if ( gCpuCaps.hasSSE ) { |
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195 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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196 |
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197 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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198 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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199 |
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200 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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201 } |
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202 |
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203 /* Restore the original signal handlers. |
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204 */ |
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205 sigaction( SIGILL, &saved_sigill, NULL ); |
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206 |
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207 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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208 * safe to go ahead and hook out the SSE code throughout Mesa. |
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209 */ |
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210 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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211 #else |
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212 /* Do nothing on other platforms for now. |
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213 */ |
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214 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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215 gCpuCaps.hasSSE=0; |
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216 #endif /* __linux__ */ |
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217 } |
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218 #endif |
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219 |
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220 |
2272 | 221 // return TRUE if cpuid supported |
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222 static int has_cpuid(void) |
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223 { |
2272 | 224 // code from libavcodec: |
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225 #if ARCH_X86_64 |
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226 return 1; |
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227 #else |
31077 | 228 long a, c; |
229 __asm__ volatile ( | |
230 /* See if CPUID instruction is supported ... */ | |
231 /* ... Get copies of EFLAGS into eax and ecx */ | |
232 "pushfl\n\t" | |
233 "pop %0\n\t" | |
234 "mov %0, %1\n\t" | |
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235 |
31077 | 236 /* ... Toggle the ID bit in one copy and store */ |
237 /* to the EFLAGS reg */ | |
238 "xor $0x200000, %0\n\t" | |
239 "push %0\n\t" | |
240 "popfl\n\t" | |
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241 |
31077 | 242 /* ... Get the (hopefully modified) EFLAGS */ |
243 "pushfl\n\t" | |
244 "pop %0\n\t" | |
245 : "=a" (a), "=c" (c) | |
246 : | |
247 : "cc" | |
248 ); | |
2272 | 249 |
31077 | 250 return a != c; |
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251 #endif |
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252 } |
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253 |
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254 void |
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255 do_cpuid(unsigned int ax, unsigned int *p) |
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256 { |
2272 | 257 // code from libavcodec: |
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258 __asm__ volatile |
31077 | 259 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 260 "cpuid\n\t" |
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261 "xchg %%"REG_b", %%"REG_S |
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262 : "=a" (p[0]), "=S" (p[1]), |
2272 | 263 "=c" (p[2]), "=d" (p[3]) |
264 : "0" (ax)); | |
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265 } |
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266 |
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267 void GetCpuCaps( CpuCaps *caps) |
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268 { |
31077 | 269 unsigned int regs[4]; |
270 unsigned int regs2[4]; | |
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271 |
31077 | 272 memset(caps, 0, sizeof(*caps)); |
273 caps->isX86=1; | |
274 caps->cl_size=32; /* default */ | |
275 if (!has_cpuid()) { | |
276 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); | |
277 return; | |
278 } | |
279 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
280 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", | |
281 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); | |
282 if (regs[0]>=0x00000001) | |
283 { | |
284 char *tmpstr, *ptmpstr; | |
285 unsigned cl_size; | |
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286 |
31077 | 287 do_cpuid(0x00000001, regs2); |
2301 | 288 |
31077 | 289 caps->cpuType=(regs2[0] >> 8)&0xf; |
290 caps->cpuModel=(regs2[0] >> 4)&0xf; | |
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291 |
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292 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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293 // System Instructions, Table 3-2: Effective family computation, page 120. |
31077 | 294 if(caps->cpuType==0xf){ |
295 // use extended family (P4, IA64, K8) | |
296 caps->cpuType=0xf+((regs2[0]>>20)&255); | |
297 } | |
298 if(caps->cpuType==0xf || caps->cpuType==6) | |
299 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; | |
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300 |
31077 | 301 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 302 |
31077 | 303 // general feature flags: |
304 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 | |
305 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
306 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
307 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
308 caps->hasSSE3 = (regs2[2] & 1); // 0x0000001 | |
309 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 | |
35101 | 310 caps->hasSSE4 = (regs2[2] & (1 << 19 )) >> 19; // 0x0080000 |
311 caps->hasSSE42 = (regs2[2] & (1 << 20)) >> 20; // 0x0100000 | |
312 caps->hasAVX = (regs2[2] & (1 << 28 )) >> 28; // 0x10000000 | |
31077 | 313 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
314 cl_size = ((regs2[1] >> 8) & 0xFF)*8; | |
315 if(cl_size) caps->cl_size = cl_size; | |
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316 |
31077 | 317 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
318 while(*ptmpstr == ' ') // strip leading spaces | |
319 ptmpstr++; | |
320 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: %s ", ptmpstr); | |
321 free(tmpstr); | |
322 mp_msg(MSGT_CPUDETECT,MSGL_V,"(Family: %d, Model: %d, Stepping: %d)\n", | |
323 caps->cpuType, caps->cpuModel, caps->cpuStepping); | |
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324 |
31077 | 325 } |
326 do_cpuid(0x80000000, regs); | |
327 if (regs[0]>=0x80000001) { | |
328 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); | |
329 do_cpuid(0x80000001, regs2); | |
330 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 | |
331 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
332 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 | |
333 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
334 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 | |
335 } | |
336 if(regs[0]>=0x80000006) | |
337 { | |
338 do_cpuid(0x80000006, regs2); | |
339 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
340 caps->cl_size = regs2[2] & 0xFF; | |
341 } | |
342 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); | |
2288 | 343 #if 0 |
31077 | 344 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
345 gCpuCaps.hasMMX, | |
346 gCpuCaps.hasMMX2, | |
347 gCpuCaps.hasSSE, | |
348 gCpuCaps.hasSSE2, | |
349 gCpuCaps.has3DNow, | |
350 gCpuCaps.has3DNowExt); | |
2288 | 351 #endif |
352 | |
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353 #if CONFIG_RUNTIME_CPUDETECT |
31077 | 354 /* FIXME: Does SSE2 need more OS support, too? */ |
355 if (caps->hasSSE) | |
356 check_os_katmai_support(); | |
357 if (!caps->hasSSE) | |
358 caps->hasSSE2 = 0; | |
359 // caps->has3DNow=1; | |
360 // caps->hasMMX2 = 0; | |
361 // caps->hasMMX = 0; | |
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362 |
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363 #else |
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364 #if !HAVE_MMX |
31077 | 365 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
366 caps->hasMMX=0; | |
4829 | 367 #endif |
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368 #if !HAVE_MMX2 |
31077 | 369 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
370 caps->hasMMX2=0; | |
4829 | 371 #endif |
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372 #if !HAVE_SSE |
31077 | 373 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
374 caps->hasSSE=0; | |
4829 | 375 #endif |
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376 #if !HAVE_SSE2 |
31077 | 377 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
378 caps->hasSSE2=0; | |
4829 | 379 #endif |
28335 | 380 #if !HAVE_AMD3DNOW |
31077 | 381 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
382 caps->has3DNow=0; | |
4829 | 383 #endif |
28335 | 384 #if !HAVE_AMD3DNOWEXT |
31077 | 385 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
386 caps->has3DNowExt=0; | |
4829 | 387 #endif |
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388 #endif // CONFIG_RUNTIME_CPUDETECT |
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389 } |
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390 |
2301 | 391 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ |
31077 | 392 char vendor[13]; |
393 char *retname; | |
394 int i; | |
2301 | 395 |
31077 | 396 if (NULL==(retname=malloc(256))) { |
397 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); | |
398 exit(1); | |
399 } | |
400 retname[0] = '\0'; | |
2303 | 401 |
31077 | 402 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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403 |
31077 | 404 do_cpuid(0x80000000,regs); |
405 if (regs[0] >= 0x80000004) | |
406 { | |
407 // CPU has built-in namestring | |
408 for (i = 0x80000002; i <= 0x80000004; i++) | |
409 { | |
410 do_cpuid(i, regs); | |
411 strncat(retname, (char*)regs, 16); | |
412 } | |
413 } | |
414 return retname; | |
2301 | 415 } |
416 | |
20577 | 417 #else /* ARCH_X86 */ |
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418 |
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419 #ifdef __APPLE__ |
9003 | 420 #include <sys/sysctl.h> |
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421 #elif defined(__AMIGAOS4__) |
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422 /* nothing */ |
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423 #else |
9003 | 424 #include <signal.h> |
425 #include <setjmp.h> | |
426 | |
427 static sigjmp_buf jmpbuf; | |
428 static volatile sig_atomic_t canjump = 0; | |
429 | |
430 static void sigill_handler (int sig) | |
431 { | |
432 if (!canjump) { | |
433 signal (sig, SIG_DFL); | |
434 raise (sig); | |
435 } | |
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436 |
9003 | 437 canjump = 0; |
438 siglongjmp (jmpbuf, 1); | |
439 } | |
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440 #endif /* __APPLE__ */ |
9003 | 441 |
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442 void GetCpuCaps( CpuCaps *caps) |
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443 { |
31077 | 444 caps->cpuType=0; |
445 caps->cpuModel=0; | |
446 caps->cpuStepping=0; | |
447 caps->hasMMX=0; | |
448 caps->hasMMX2=0; | |
449 caps->has3DNow=0; | |
450 caps->has3DNowExt=0; | |
451 caps->hasSSE=0; | |
452 caps->hasSSE2=0; | |
453 caps->hasSSE3=0; | |
454 caps->hasSSSE3=0; | |
35101 | 455 caps->hasSSE4=0; |
456 caps->hasSSE42=0; | |
31077 | 457 caps->hasSSE4a=0; |
35101 | 458 caps->hasAVX=0; |
31077 | 459 caps->isX86=0; |
460 caps->hasAltiVec = 0; | |
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461 #if HAVE_ALTIVEC |
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462 #ifdef __APPLE__ |
9003 | 463 /* |
464 rip-off from ffmpeg altivec detection code. | |
465 this code also appears on Apple's AltiVec pages. | |
466 */ | |
31077 | 467 { |
468 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
469 int has_vu = 0; | |
470 size_t len = sizeof(has_vu); | |
471 int err; | |
9003 | 472 |
31077 | 473 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); |
9003 | 474 |
31077 | 475 if (err == 0) |
476 if (has_vu != 0) | |
477 caps->hasAltiVec = 1; | |
478 } | |
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479 #elif defined(__AMIGAOS4__) |
31077 | 480 ULONG result = 0; |
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481 |
31077 | 482 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
483 if (result == VECTORTYPE_ALTIVEC) | |
484 caps->hasAltiVec = 1; | |
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485 #else |
9003 | 486 /* no Darwin, do it the brute-force way */ |
487 /* this is borrowed from the libmpeg2 library */ | |
31077 | 488 { |
489 signal (SIGILL, sigill_handler); | |
490 if (sigsetjmp (jmpbuf, 1)) { | |
9003 | 491 signal (SIGILL, SIG_DFL); |
31077 | 492 } else { |
9003 | 493 canjump = 1; |
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494 |
31077 | 495 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 496 "vand %%v0, %%v0, %%v0" |
9003 | 497 : |
498 : "r" (-1)); | |
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499 |
31077 | 500 signal (SIGILL, SIG_DFL); |
501 caps->hasAltiVec = 1; | |
9003 | 502 } |
31077 | 503 } |
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504 #endif /* __APPLE__ */ |
31077 | 505 mp_msg(MSGT_CPUDETECT,MSGL_V,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 506 #endif /* HAVE_ALTIVEC */ |
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507 |
31077 | 508 if (ARCH_IA64) |
509 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Intel Itanium\n"); | |
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510 |
31077 | 511 if (ARCH_SPARC) |
512 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Sun Sparc\n"); | |
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513 |
31077 | 514 if (ARCH_ARM) |
515 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: ARM\n"); | |
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516 |
31077 | 517 if (ARCH_PPC) |
518 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: PowerPC\n"); | |
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519 |
31077 | 520 if (ARCH_ALPHA) |
521 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Digital Alpha\n"); | |
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522 |
31077 | 523 if (ARCH_MIPS) |
524 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: MIPS\n"); | |
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525 |
31077 | 526 if (ARCH_PA_RISC) |
527 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: Hewlett-Packard PA-RISC\n"); | |
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528 |
31077 | 529 if (ARCH_S390) |
530 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390\n"); | |
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531 |
31077 | 532 if (ARCH_S390X) |
533 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU: IBM S/390X\n"); | |
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534 |
31077 | 535 if (ARCH_VAX) |
536 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Digital VAX\n" ); | |
25340 | 537 |
31077 | 538 if (ARCH_XTENSA) |
539 mp_msg(MSGT_CPUDETECT,MSGL_V, "CPU: Tensilica Xtensa\n" ); | |
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540 } |
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541 #endif /* !ARCH_X86 */ |