Mercurial > mplayer.hg
annotate drivers/radeon/radeon_vid.c @ 3247:7cec2396bde3
Tune up driver through reading and writing /dev/radeon_vid ;)
author | nick |
---|---|
date | Sat, 01 Dec 2001 17:08:37 +0000 |
parents | 5eae81895171 |
children | 61b1441c0f8c |
rev | line source |
---|---|
2870 | 1 /* |
2 * | |
3 * radeon_vid.c | |
4 * | |
5 * Copyright (C) 2001 Nick Kurshev | |
6 * | |
3164 | 7 * BES YUV video overlay driver for Radeon/Rage128Pro/Rage128 cards |
2870 | 8 * |
9 * This software has been released under the terms of the GNU Public | |
10 * license. See http://www.gnu.org/copyleft/gpl.html for details. | |
11 * | |
12 * This file is partly based on mga_vid and sis_vid stuff from | |
13 * mplayer's package. | |
2917 | 14 * Also here was used code from CVS of GATOS project and X11 trees. |
2870 | 15 */ |
16 | |
3164 | 17 #define RADEON_VID_VERSION "1.0.0" |
2951 | 18 |
2870 | 19 /* |
20 It's entirely possible this major conflicts with something else | |
21 mknod /dev/radeon_vid c 178 0 | |
3164 | 22 or |
23 mknod /dev/rage128_vid c 178 0 | |
24 for Rage128/Rage128Pro chips (althrough it doesn't matter) | |
25 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ | |
26 TESTED and WORKING formats: YUY2, UYVY, IYUV, I420, YV12 | |
27 ----------------------------------------------------------- | |
2870 | 28 TODO: |
3164 | 29 Highest priority: fbvid.h compatibility |
30 High priority: RGB/BGR 2-32, YVU9, IF09 support | |
3122 | 31 Middle priority: |
32 OV0_COLOUR_CNTL brightness saturation | |
33 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? | |
34 OV0_GRAPHICS_KEY_CLR color key | |
35 OV0_AUTO_FLIP_CNTL | |
36 OV0_FILTER_CNTL | |
37 OV0_VIDEO_KEY_CLR | |
38 OV0_KEY_CNTL | |
3164 | 39 Low priority: CLPL, IYU1, IYU2, UYNV, CYUV |
3122 | 40 YUNV, YVYU, Y41P, Y211, Y41T, Y42T, V422, V655, CLJR |
41 ^^^^ | |
42 YUVP, UYVP, Mpeg PES (mpeg-1,2) support | |
2870 | 43 */ |
44 | |
45 #include <linux/config.h> | |
46 #include <linux/version.h> | |
47 #include <linux/module.h> | |
48 #include <linux/types.h> | |
49 #include <linux/kernel.h> | |
50 #include <linux/sched.h> | |
51 #include <linux/mm.h> | |
52 #include <linux/string.h> | |
53 #include <linux/errno.h> | |
54 #include <linux/slab.h> | |
55 #include <linux/pci.h> | |
56 #include <linux/ioport.h> | |
57 #include <linux/init.h> | |
58 | |
59 #include "radeon_vid.h" | |
60 #include "radeon.h" | |
61 | |
62 #ifdef CONFIG_MTRR | |
63 #include <asm/mtrr.h> | |
64 #endif | |
65 | |
66 #include <asm/uaccess.h> | |
67 #include <asm/system.h> | |
68 #include <asm/io.h> | |
69 | |
70 #define TRUE 1 | |
71 #define FALSE 0 | |
72 | |
73 #define RADEON_VID_MAJOR 178 | |
74 | |
75 | |
76 MODULE_AUTHOR("Nick Kurshev <nickols_k@mail.ru>"); | |
3198 | 77 #ifdef RAGE128 |
78 MODULE_DESCRIPTION("Accelerated YUV BES driver for Rage128. Version: "RADEON_VID_VERSION); | |
79 #else | |
80 MODULE_DESCRIPTION("Accelerated YUV BES driver for Radeons. Version: "RADEON_VID_VERSION); | |
81 #endif | |
2965 | 82 #ifdef MODULE_LICENSE |
2870 | 83 MODULE_LICENSE("GPL"); |
2965 | 84 #endif |
2870 | 85 |
3164 | 86 #ifdef RAGE128 |
87 #define RVID_MSG "rage128_vid: " | |
88 #define X_ADJUST 0 | |
89 #else | |
90 #define RVID_MSG "radeon_vid: " | |
91 #define X_ADJUST 8 | |
3198 | 92 #ifndef RADEON |
93 #define RADEON | |
94 #endif | |
3164 | 95 #endif |
96 | |
2870 | 97 typedef struct bes_registers_s |
98 { | |
99 /* base address of yuv framebuffer */ | |
100 uint32_t yuv_base; | |
101 uint32_t fourcc; | |
102 /* YUV BES registers */ | |
103 uint32_t reg_load_cntl; | |
104 uint32_t h_inc; | |
105 uint32_t step_by; | |
106 uint32_t y_x_start; | |
107 uint32_t y_x_end; | |
108 uint32_t v_inc; | |
109 uint32_t p1_blank_lines_at_top; | |
3019 | 110 uint32_t p23_blank_lines_at_top; |
2870 | 111 uint32_t vid_buf_pitch0_value; |
2944 | 112 uint32_t vid_buf_pitch1_value; |
2870 | 113 uint32_t p1_x_start_end; |
114 uint32_t p2_x_start_end; | |
115 uint32_t p3_x_start_end; | |
3122 | 116 uint32_t base_addr; |
2870 | 117 uint32_t vid_buf0_base_adrs; |
118 /* These ones are for auto flip: maybe in the future */ | |
119 uint32_t vid_buf1_base_adrs; | |
120 uint32_t vid_buf2_base_adrs; | |
121 uint32_t vid_buf3_base_adrs; | |
122 uint32_t vid_buf4_base_adrs; | |
123 uint32_t vid_buf5_base_adrs; | |
124 | |
125 uint32_t p1_v_accum_init; | |
126 uint32_t p1_h_accum_init; | |
3019 | 127 uint32_t p23_v_accum_init; |
2870 | 128 uint32_t p23_h_accum_init; |
129 uint32_t scale_cntl; | |
130 uint32_t exclusive_horz; | |
131 uint32_t auto_flip_cntl; | |
132 uint32_t filter_cntl; | |
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133 int brightness; |
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134 int saturation; |
2870 | 135 uint32_t graphics_key_msk; |
136 uint32_t graphics_key_clr; | |
137 uint32_t key_cntl; | |
138 uint32_t test; | |
139 } bes_registers_t; | |
140 | |
141 typedef struct video_registers_s | |
142 { | |
143 uint32_t name; | |
144 uint32_t value; | |
145 }video_registers_t; | |
146 | |
147 static bes_registers_t besr; | |
148 static video_registers_t vregs[] = | |
149 { | |
150 { OV0_REG_LOAD_CNTL, 0 }, | |
151 { OV0_H_INC, 0 }, | |
152 { OV0_STEP_BY, 0 }, | |
153 { OV0_Y_X_START, 0 }, | |
154 { OV0_Y_X_END, 0 }, | |
155 { OV0_V_INC, 0 }, | |
156 { OV0_P1_BLANK_LINES_AT_TOP, 0 }, | |
3019 | 157 { OV0_P23_BLANK_LINES_AT_TOP, 0 }, |
2870 | 158 { OV0_VID_BUF_PITCH0_VALUE, 0 }, |
2944 | 159 { OV0_VID_BUF_PITCH1_VALUE, 0 }, |
2870 | 160 { OV0_P1_X_START_END, 0 }, |
161 { OV0_P2_X_START_END, 0 }, | |
162 { OV0_P3_X_START_END, 0 }, | |
3122 | 163 { OV0_BASE_ADDR, 0 }, |
2870 | 164 { OV0_VID_BUF0_BASE_ADRS, 0 }, |
165 { OV0_VID_BUF1_BASE_ADRS, 0 }, | |
166 { OV0_VID_BUF2_BASE_ADRS, 0 }, | |
167 { OV0_VID_BUF3_BASE_ADRS, 0 }, | |
168 { OV0_VID_BUF4_BASE_ADRS, 0 }, | |
169 { OV0_VID_BUF5_BASE_ADRS, 0 }, | |
170 { OV0_P1_V_ACCUM_INIT, 0 }, | |
171 { OV0_P1_H_ACCUM_INIT, 0 }, | |
3019 | 172 { OV0_P23_V_ACCUM_INIT, 0 }, |
2870 | 173 { OV0_P23_H_ACCUM_INIT, 0 }, |
174 { OV0_SCALE_CNTL, 0 }, | |
175 { OV0_EXCLUSIVE_HORZ, 0 }, | |
176 { OV0_AUTO_FLIP_CNTL, 0 }, | |
177 { OV0_FILTER_CNTL, 0 }, | |
178 { OV0_COLOUR_CNTL, 0 }, | |
179 { OV0_GRAPHICS_KEY_MSK, 0 }, | |
180 { OV0_GRAPHICS_KEY_CLR, 0 }, | |
181 { OV0_KEY_CNTL, 0 }, | |
182 { OV0_TEST, 0 } | |
183 }; | |
184 | |
185 static uint32_t radeon_vid_in_use = 0; | |
186 | |
187 static uint8_t *radeon_mmio_base = 0; | |
188 static uint32_t radeon_mem_base = 0; | |
3019 | 189 static int32_t radeon_overlay_off = 0; |
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190 static int radeon_double_buff=1; |
2870 | 191 static uint32_t radeon_ram_size = 0; |
192 | |
193 static mga_vid_config_t radeon_config; | |
194 | |
2951 | 195 #undef DEBUG |
2870 | 196 #if DEBUG |
197 #define RTRACE printk | |
198 #else | |
199 #define RTRACE(...) ((void)0) | |
200 #endif | |
201 | |
3122 | 202 static char *fourcc_format_name(int format) |
203 { | |
204 switch(format) | |
205 { | |
206 case IMGFMT_RGB8: return("RGB 8-bit"); | |
207 case IMGFMT_RGB15: return("RGB 15-bit"); | |
208 case IMGFMT_RGB16: return("RGB 16-bit"); | |
209 case IMGFMT_RGB24: return("RGB 24-bit"); | |
210 case IMGFMT_RGB32: return("RGB 32-bit"); | |
211 case IMGFMT_BGR8: return("BGR 8-bit"); | |
212 case IMGFMT_BGR15: return("BGR 15-bit"); | |
213 case IMGFMT_BGR16: return("BGR 16-bit"); | |
214 case IMGFMT_BGR24: return("BGR 24-bit"); | |
215 case IMGFMT_BGR32: return("BGR 32-bit"); | |
216 case IMGFMT_YVU9: return("Planar YVU9"); | |
217 case IMGFMT_IF09: return("Planar IF09"); | |
218 case IMGFMT_YV12: return("Planar YV12"); | |
219 case IMGFMT_I420: return("Planar I420"); | |
220 case IMGFMT_IYUV: return("Planar IYUV"); | |
221 case IMGFMT_CLPL: return("Planar CLPL"); | |
3198 | 222 case IMGFMT_Y800: return("Planar Y800"); |
223 case IMGFMT_Y8: return("Planar Y8"); | |
224 case IMGFMT_IUYV: return("Packed IUYV"); | |
225 case IMGFMT_IY41: return("Packed IY41"); | |
3122 | 226 case IMGFMT_IYU1: return("Packed IYU1"); |
227 case IMGFMT_IYU2: return("Packed IYU2"); | |
228 case IMGFMT_UYVY: return("Packed UYVY"); | |
229 case IMGFMT_UYNV: return("Packed UYNV"); | |
230 case IMGFMT_cyuv: return("Packed CYUV"); | |
3198 | 231 case IMGFMT_Y422: return("Packed Y422"); |
3122 | 232 case IMGFMT_YUY2: return("Packed YUY2"); |
233 case IMGFMT_YUNV: return("Packed YUNV"); | |
234 case IMGFMT_YVYU: return("Packed YVYU"); | |
235 case IMGFMT_Y41P: return("Packed Y41P"); | |
236 case IMGFMT_Y211: return("Packed Y211"); | |
237 case IMGFMT_Y41T: return("Packed Y41T"); | |
238 case IMGFMT_Y42T: return("Packed Y42T"); | |
239 case IMGFMT_V422: return("Packed V422"); | |
240 case IMGFMT_V655: return("Packed V655"); | |
241 case IMGFMT_CLJR: return("Packed CLJR"); | |
242 case IMGFMT_YUVP: return("Packed YUVP"); | |
243 case IMGFMT_UYVP: return("Packed UYVP"); | |
3198 | 244 case IMGFMT_MPEGPES: return("Mpeg PES"); |
3122 | 245 } |
246 return("Unknown"); | |
247 } | |
248 | |
2870 | 249 |
250 /* | |
251 * IO macros | |
252 */ | |
253 | |
254 #define INREG8(addr) readb((radeon_mmio_base)+addr) | |
255 #define OUTREG8(addr,val) writeb(val, (radeon_mmio_base)+addr) | |
256 #define INREG(addr) readl((radeon_mmio_base)+addr) | |
257 #define OUTREG(addr,val) writel(val, (radeon_mmio_base)+addr) | |
258 | |
259 static void radeon_vid_save_state( void ) | |
260 { | |
261 size_t i; | |
262 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
263 vregs[i].value = INREG(vregs[i].name); | |
264 } | |
265 | |
266 static void radeon_vid_restore_state( void ) | |
267 { | |
268 size_t i; | |
269 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) | |
270 OUTREG(vregs[i].name,vregs[i].value); | |
271 } | |
272 | |
273 static void radeon_vid_stop_video( void ) | |
274 { | |
275 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); | |
276 OUTREG(OV0_EXCLUSIVE_HORZ, 0); | |
277 OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ | |
278 OUTREG(OV0_FILTER_CNTL, 0x0000000f); | |
279 /* | |
280 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
281 (saturation << 8) | | |
282 (saturation << 16)); | |
283 OUTREG(OV0_GRAPHICS_KEY_MSK, (1 << depth) - 1); | |
284 OUTREG(OV0_GRAPHICS_KEY_CLR, colorKey); | |
285 */ | |
286 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); | |
287 OUTREG(OV0_TEST, 0); | |
288 } | |
289 | |
290 static void radeon_vid_display_video( void ) | |
291 { | |
292 int bes_flags; | |
3164 | 293 RTRACE(RVID_MSG"OV0: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
294 RTRACE(RVID_MSG"OV0: vid_buf0_base=%x\n",besr.vid_buf0_base_adrs); | |
295 RTRACE(RVID_MSG"OV0: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 296 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
3164 | 297 RTRACE(RVID_MSG"OV0: p1_x_start_end=%x p2_x_start_end=%x p3_x_start-end=%x\n" |
2951 | 298 ,besr.p1_x_start_end,besr.p2_x_start_end,besr.p2_x_start_end); |
3164 | 299 RTRACE(RVID_MSG"OV0: p1_v_accum_init=%x p1_h_accum_init=%x p23_h_accum_init=%x\n" |
2951 | 300 ,besr.p1_v_accum_init,besr.p1_h_accum_init,besr.p23_h_accum_init); |
2870 | 301 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
302 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
2965 | 303 |
2870 | 304 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); |
305 | |
3164 | 306 OUTREG(OV0_DEINTERLACE_PATTERN,0x900AAAAA); |
2870 | 307 |
308 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
309 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE)); | |
2965 | 310 |
2870 | 311 OUTREG(OV0_H_INC, besr.h_inc); |
312 OUTREG(OV0_STEP_BY, besr.step_by); | |
313 OUTREG(OV0_Y_X_START, besr.y_x_start); | |
314 OUTREG(OV0_Y_X_END, besr.y_x_end); | |
315 OUTREG(OV0_V_INC, besr.v_inc); | |
316 OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); | |
3164 | 317 OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); |
2870 | 318 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); |
2944 | 319 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); |
2870 | 320 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); |
321 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); | |
322 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); | |
3198 | 323 #if 0 |
3122 | 324 OUTREG(OV0_BASE_ADDR, besr.base_addr); |
325 #endif | |
2870 | 326 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); |
327 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); | |
328 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); | |
329 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); | |
330 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); | |
331 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf5_base_adrs); | |
332 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); | |
333 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); | |
334 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); | |
3164 | 335 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); |
2870 | 336 |
337 bes_flags = SCALER_ENABLE | | |
2965 | 338 SCALER_ADAPTIVE_DEINT | |
2870 | 339 SCALER_SMART_SWITCH | |
340 SCALER_HORZ_PICK_NEAREST; | |
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341 if(radeon_double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; |
3198 | 342 #ifdef RAGE128 |
343 bes_flags |= SCALER_BURST_PER_PLANE; | |
344 #endif | |
2870 | 345 switch(besr.fourcc) |
346 { | |
347 case IMGFMT_RGB15: | |
348 case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; | |
349 case IMGFMT_RGB16: | |
350 case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; | |
351 case IMGFMT_RGB24: | |
352 case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; | |
353 case IMGFMT_RGB32: | |
354 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; | |
3164 | 355 /* 4:1:0*/ |
356 case IMGFMT_IF09: | |
2870 | 357 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; |
3164 | 358 /* 4:2:0 */ |
3122 | 359 case IMGFMT_IYUV: |
2870 | 360 case IMGFMT_I420: |
3164 | 361 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; |
362 /* 4:2:2 */ | |
363 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; | |
2870 | 364 case IMGFMT_YUY2: |
365 default: bes_flags |= SCALER_SOURCE_VYUY422; break; | |
366 } | |
3164 | 367 RTRACE(RVID_MSG"OV0: SCALER=%x\n",bes_flags); |
2870 | 368 OUTREG(OV0_SCALE_CNTL, bes_flags); |
369 /* | |
370 TODO: | |
371 brightness: -64 : +63 | |
372 saturation: 0 : 31 | |
373 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | | |
374 (saturation << 8) | | |
375 (saturation << 16)); | |
376 OUTREG(OV0_GRAPHICS_KEY_CLR, colkey_red | colkey_green << 8 | colkey_blue << 16); | |
377 | |
378 */ | |
379 OUTREG(OV0_REG_LOAD_CNTL, 0); | |
380 } | |
381 | |
2951 | 382 #define XXX_SRC_X 0 |
383 #define XXX_SRC_Y 0 | |
2870 | 384 |
2944 | 385 #define XXX_WIDTH config->src_width |
386 #define XXX_HEIGHT config->src_height | |
2870 | 387 |
2951 | 388 #define XXX_DRW_W config->dest_width |
389 #define XXX_DRW_H config->dest_height | |
2925 | 390 |
2870 | 391 static int radeon_vid_init_video( mga_vid_config_t *config ) |
392 { | |
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393 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top; |
3019 | 394 int is_420; |
3164 | 395 RTRACE(RVID_MSG"usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" |
2870 | 396 ,(uint32_t)config->version |
2951 | 397 ,(uint32_t)config->format |
2870 | 398 ,(uint32_t)config->card_type |
399 ,(uint32_t)config->ram_size | |
400 ,(uint32_t)config->src_width | |
401 ,(uint32_t)config->src_height | |
402 ,(uint32_t)config->x_org | |
403 ,(uint32_t)config->y_org | |
404 ,(uint32_t)config->dest_width | |
405 ,(uint32_t)config->dest_height | |
406 ,(uint32_t)config->frame_size | |
407 ,(uint32_t)config->num_frames); | |
2917 | 408 radeon_vid_stop_video(); |
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409 left = XXX_SRC_X << 16; |
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410 top = XXX_SRC_Y << 16; |
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411 src_h = config->src_height; |
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nick
parents:
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412 src_w = config->src_width; |
2870 | 413 switch(config->format) |
414 { | |
415 case IMGFMT_RGB15: | |
416 case IMGFMT_BGR15: | |
417 case IMGFMT_RGB16: | |
418 case IMGFMT_BGR16: | |
419 case IMGFMT_RGB24: | |
420 case IMGFMT_BGR24: | |
421 case IMGFMT_RGB32: | |
422 case IMGFMT_BGR32: | |
3164 | 423 /* 4:1:0 */ |
424 case IMGFMT_IF09: | |
2870 | 425 case IMGFMT_YVU9: |
3164 | 426 /* 4:2:0 */ |
2870 | 427 case IMGFMT_IYUV: |
428 case IMGFMT_YV12: | |
429 case IMGFMT_I420: | |
3164 | 430 /* 4:2:2 */ |
431 case IMGFMT_UYVY: | |
2870 | 432 case IMGFMT_YUY2: |
433 break; | |
434 default: | |
3164 | 435 printk(RVID_MSG"Unsupported pixel format: 0x%X\n",config->format); |
2870 | 436 return -1; |
437 } | |
3019 | 438 is_420 = 0; |
3122 | 439 if(config->format == IMGFMT_YV12 || |
440 config->format == IMGFMT_I420 || | |
441 config->format == IMGFMT_IYUV) is_420 = 1; | |
2951 | 442 switch(config->format) |
443 { | |
3164 | 444 /* 4:1:0 */ |
2951 | 445 case IMGFMT_YVU9: |
3164 | 446 case IMGFMT_IF09: |
447 /* 4:2:0 */ | |
2951 | 448 case IMGFMT_IYUV: |
3164 | 449 case IMGFMT_YV12: |
450 case IMGFMT_I420: pitch = (src_w + 31) & ~31; break; | |
451 /* 4:2:2 */ | |
452 default: | |
2951 | 453 case IMGFMT_UYVY: |
454 case IMGFMT_YUY2: | |
455 case IMGFMT_RGB15: | |
456 case IMGFMT_BGR15: | |
457 case IMGFMT_RGB16: | |
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458 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break; |
2951 | 459 case IMGFMT_RGB24: |
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460 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break; |
2951 | 461 case IMGFMT_RGB32: |
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462 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break; |
2951 | 463 } |
464 | |
2870 | 465 besr.fourcc = config->format; |
466 | |
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467 besr.v_inc = (src_h << 20) / XXX_DRW_H; |
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468 h_inc = (src_w << 12) / XXX_DRW_W; |
2944 | 469 step_by = 1; |
2870 | 470 |
2944 | 471 while(h_inc >= (2 << 12)) { |
472 step_by++; | |
473 h_inc >>= 1; | |
2870 | 474 } |
475 | |
476 /* keep everything in 16.16 */ | |
3164 | 477 besr.base_addr = radeon_mem_base; |
3019 | 478 if(is_420) |
479 { | |
3164 | 480 uint32_t d1line,d2line,d3line; |
481 d1line = top*pitch; | |
482 d2line = src_h*pitch+(d1line>>1); | |
483 d3line = d2line+((src_h*pitch)>>2); | |
484 d1line += (left >> 16) & ~15; | |
485 d2line += (left >> 17) & ~15; | |
486 d3line += (left >> 17) & ~15; | |
487 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK); | |
488 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; | |
489 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; | |
490 if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) | |
491 { | |
492 uint32_t tmp; | |
493 tmp = besr.vid_buf1_base_adrs; | |
494 besr.vid_buf1_base_adrs = besr.vid_buf2_base_adrs; | |
495 besr.vid_buf2_base_adrs = tmp; | |
496 } | |
3019 | 497 } |
498 else | |
499 { | |
500 besr.vid_buf0_base_adrs = radeon_overlay_off; | |
3198 | 501 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; |
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502 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs; |
3019 | 503 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; |
504 } | |
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505 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size; |
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506 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size; |
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507 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size; |
2870 | 508 |
2951 | 509 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); |
2870 | 510 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 511 ((tmp << 12) & 0xf0000000); |
2870 | 512 |
2951 | 513 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); |
2870 | 514 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | |
2951 | 515 ((tmp << 12) & 0x70000000); |
516 tmp = (top & 0x0000ffff) + 0x00018000; | |
3122 | 517 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) |
518 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); | |
3019 | 519 |
520 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; | |
3122 | 521 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) |
522 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; | |
3019 | 523 |
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524 leftUV = (left >> 17) & 15; |
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525 left = (left >> 16) & 15; |
2944 | 526 besr.h_inc = h_inc | ((h_inc >> 1) << 16); |
527 besr.step_by = step_by | (step_by << 8); | |
3164 | 528 besr.y_x_start = (config->x_org+X_ADJUST) | (config->y_org << 16); |
529 besr.y_x_end = (config->x_org + config->dest_width+X_ADJUST) | ((config->y_org + config->dest_height) << 16); | |
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530 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); |
3122 | 531 if(is_420) |
532 { | |
533 src_h = (src_h + 1) >> 1; | |
534 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); | |
535 } | |
536 else besr.p23_blank_lines_at_top = 0; | |
2870 | 537 besr.vid_buf_pitch0_value = pitch; |
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538 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; |
3164 | 539 RTRACE(RVID_MSG"BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); |
540 RTRACE(RVID_MSG"BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); | |
541 RTRACE(RVID_MSG"BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" | |
2925 | 542 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); |
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543 besr.p1_x_start_end = (src_w+left-1)|(left<<16); |
3164 | 544 src_w>>=1; |
545 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); | |
546 besr.p3_x_start_end = besr.p2_x_start_end; | |
2870 | 547 return 0; |
548 } | |
549 | |
550 static void radeon_vid_frame_sel(int frame) | |
551 { | |
3066 | 552 uint32_t off0,off1,off2; |
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553 if(!radeon_double_buff) return; |
3066 | 554 if(frame%2) |
555 { | |
556 off0 = besr.vid_buf3_base_adrs; | |
557 off1 = besr.vid_buf4_base_adrs; | |
558 off2 = besr.vid_buf5_base_adrs; | |
559 } | |
560 else | |
561 { | |
562 off0 = besr.vid_buf0_base_adrs; | |
563 off1 = besr.vid_buf1_base_adrs; | |
564 off2 = besr.vid_buf2_base_adrs; | |
565 } | |
2917 | 566 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); |
567 while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); | |
3066 | 568 OUTREG(OV0_VID_BUF0_BASE_ADRS, off0); |
569 OUTREG(OV0_VID_BUF1_BASE_ADRS, off1); | |
570 OUTREG(OV0_VID_BUF2_BASE_ADRS, off2); | |
2917 | 571 OUTREG(OV0_REG_LOAD_CNTL, 0); |
2870 | 572 } |
573 | |
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574 static void radeon_vid_preset(void) |
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575 { |
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576 unsigned tmp; |
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577 tmp = INREG(OV0_COLOUR_CNTL); |
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578 besr.saturation = (tmp>>8)&0x1f; |
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579 besr.brightness = tmp & 0x7f; |
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580 } |
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581 |
2951 | 582 static int video_on = 0; |
583 | |
2870 | 584 static int radeon_vid_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) |
585 { | |
586 int frame; | |
587 | |
588 switch(cmd) | |
589 { | |
590 case MGA_VID_CONFIG: | |
591 RTRACE( "radeon_mmio_base = %p\n",radeon_mmio_base); | |
592 RTRACE( "radeon_mem_base = %08x\n",radeon_mem_base); | |
3164 | 593 RTRACE(RVID_MSG"Received configuration\n"); |
2870 | 594 |
595 if(copy_from_user(&radeon_config,(mga_vid_config_t*) arg,sizeof(mga_vid_config_t))) | |
596 { | |
3164 | 597 printk(RVID_MSG"failed copy from userspace\n"); |
3019 | 598 return -EFAULT; |
2870 | 599 } |
600 if(radeon_config.version != MGA_VID_VERSION){ | |
3164 | 601 printk(RVID_MSG"incompatible version! driver: %X requested: %X\n",MGA_VID_VERSION,radeon_config.version); |
3019 | 602 return -EFAULT; |
2870 | 603 } |
604 | |
605 if(radeon_config.frame_size==0 || radeon_config.frame_size>1024*768*2){ | |
3164 | 606 printk(RVID_MSG"illegal frame_size: %d\n",radeon_config.frame_size); |
3019 | 607 return -EFAULT; |
2870 | 608 } |
609 | |
610 if(radeon_config.num_frames<1 || radeon_config.num_frames>4){ | |
3164 | 611 printk(RVID_MSG"illegal num_frames: %d\n",radeon_config.num_frames); |
3019 | 612 return -EFAULT; |
2870 | 613 } |
614 | |
615 radeon_config.card_type = 0; | |
616 radeon_config.ram_size = radeon_ram_size; | |
3019 | 617 radeon_overlay_off = radeon_ram_size*0x100000 - radeon_config.frame_size*radeon_config.num_frames; |
618 radeon_overlay_off &= 0xffff0000; | |
619 if(radeon_overlay_off < 0){ | |
3164 | 620 printk(RVID_MSG"not enough video memory. Need: %u has: %u\n",radeon_config.frame_size*radeon_config.num_frames,radeon_ram_size*0x100000); |
3019 | 621 return -EFAULT; |
622 } | |
3164 | 623 RTRACE(RVID_MSG"using video overlay at offset %p\n",radeon_overlay_off); |
2870 | 624 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) |
625 { | |
3164 | 626 printk(RVID_MSG"failed copy to userspace\n"); |
3019 | 627 return -EFAULT; |
2870 | 628 } |
3164 | 629 printk(RVID_MSG"configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format)); |
2870 | 630 return radeon_vid_init_video(&radeon_config); |
631 break; | |
632 | |
633 case MGA_VID_ON: | |
3164 | 634 RTRACE(RVID_MSG"Video ON (ioctl)\n"); |
635 radeon_vid_display_video(); | |
2951 | 636 video_on = 1; |
2870 | 637 break; |
638 | |
639 case MGA_VID_OFF: | |
3164 | 640 RTRACE(RVID_MSG"Video OFF (ioctl)\n"); |
2951 | 641 if(video_on) radeon_vid_stop_video(); |
642 video_on = 0; | |
2870 | 643 break; |
644 | |
645 case MGA_VID_FSEL: | |
646 if(copy_from_user(&frame,(int *) arg,sizeof(int))) | |
647 { | |
3164 | 648 printk(RVID_MSG"FSEL failed copy from userspace\n"); |
2870 | 649 return(-EFAULT); |
650 } | |
651 radeon_vid_frame_sel(frame); | |
652 break; | |
653 | |
654 default: | |
3164 | 655 printk(RVID_MSG"Invalid ioctl\n"); |
2870 | 656 return (-EINVAL); |
657 } | |
658 | |
659 return 0; | |
660 } | |
661 | |
662 struct ati_card_id_s | |
663 { | |
3164 | 664 const int id; |
665 const char name[17]; | |
666 }; | |
667 | |
668 const struct ati_card_id_s ati_card_ids[]= | |
2870 | 669 { |
3164 | 670 #ifdef RAGE128 |
671 /* | |
672 This driver should be compatible with Rage128 (pro) chips. | |
673 (include adaptive deinterlacing!!!). | |
674 Moreover: the same logic can be used with Mach64 chips. | |
675 (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). | |
676 but they are incompatible by i/o ports. So if enthusiasts will want | |
677 then they can redefine OUTREG and INREG macros and redefine OV0_* | |
678 constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY | |
679 fourccs (422 and 420 formats only). | |
680 */ | |
681 /* Rage128 Pro GL */ | |
682 { PCI_DEVICE_ID_ATI_Rage128_PA, "R128Pro PA" }, | |
683 { PCI_DEVICE_ID_ATI_Rage128_PB, "R128Pro PB" }, | |
684 { PCI_DEVICE_ID_ATI_Rage128_PC, "R128Pro PC" }, | |
685 { PCI_DEVICE_ID_ATI_Rage128_PD, "R128Pro PD" }, | |
686 { PCI_DEVICE_ID_ATI_Rage128_PE, "R128Pro PE" }, | |
687 { PCI_DEVICE_ID_ATI_RAGE128_PF, "R128Pro PF" }, | |
688 /* Rage128 Pro VR */ | |
689 { PCI_DEVICE_ID_ATI_RAGE128_PG, "R128Pro PG" }, | |
690 { PCI_DEVICE_ID_ATI_RAGE128_PH, "R128Pro PH" }, | |
691 { PCI_DEVICE_ID_ATI_RAGE128_PI, "R128Pro PI" }, | |
692 { PCI_DEVICE_ID_ATI_RAGE128_PJ, "R128Pro PJ" }, | |
693 { PCI_DEVICE_ID_ATI_RAGE128_PK, "R128Pro PK" }, | |
694 { PCI_DEVICE_ID_ATI_RAGE128_PL, "R128Pro PL" }, | |
695 { PCI_DEVICE_ID_ATI_RAGE128_PM, "R128Pro PM" }, | |
696 { PCI_DEVICE_ID_ATI_RAGE128_PN, "R128Pro PN" }, | |
697 { PCI_DEVICE_ID_ATI_RAGE128_PO, "R128Pro PO" }, | |
698 { PCI_DEVICE_ID_ATI_RAGE128_PP, "R128Pro PP" }, | |
699 { PCI_DEVICE_ID_ATI_RAGE128_PQ, "R128Pro PQ" }, | |
700 { PCI_DEVICE_ID_ATI_RAGE128_PR, "R128Pro PR" }, | |
701 { PCI_DEVICE_ID_ATI_RAGE128_TR, "R128Pro TR" }, | |
702 { PCI_DEVICE_ID_ATI_RAGE128_PS, "R128Pro PS" }, | |
703 { PCI_DEVICE_ID_ATI_RAGE128_PT, "R128Pro PT" }, | |
704 { PCI_DEVICE_ID_ATI_RAGE128_PU, "R128Pro PU" }, | |
705 { PCI_DEVICE_ID_ATI_RAGE128_PV, "R128Pro PV" }, | |
706 { PCI_DEVICE_ID_ATI_RAGE128_PW, "R128Pro PW" }, | |
707 { PCI_DEVICE_ID_ATI_RAGE128_PX, "R128Pro PX" }, | |
708 /* Rage128 GL */ | |
709 { PCI_DEVICE_ID_ATI_RAGE128_RE, "R128 RE" }, | |
710 { PCI_DEVICE_ID_ATI_RAGE128_RF, "R128 RF" }, | |
711 { PCI_DEVICE_ID_ATI_RAGE128_RG, "R128 RG" }, | |
712 { PCI_DEVICE_ID_ATI_RAGE128_RH, "R128 RH" }, | |
713 { PCI_DEVICE_ID_ATI_RAGE128_RI, "R128 RI" }, | |
714 /* Rage128 VR */ | |
715 { PCI_DEVICE_ID_ATI_RAGE128_RK, "R128 RK" }, | |
716 { PCI_DEVICE_ID_ATI_RAGE128_RL, "R128 RL" }, | |
717 { PCI_DEVICE_ID_ATI_RAGE128_RM, "R128 RM" }, | |
718 { PCI_DEVICE_ID_ATI_RAGE128_RN, "R128 RN" }, | |
719 { PCI_DEVICE_ID_ATI_RAGE128_RO, "R128 RO" }, | |
720 /* Rage128 M3 */ | |
3198 | 721 { PCI_DEVICE_ID_ATI_RAGE128_LE, "R128 M3 LE" }, |
722 { PCI_DEVICE_ID_ATI_RAGE128_LF, "R128 M3 LF" }, | |
3164 | 723 /* Rage128 Pro Ultra */ |
3198 | 724 { PCI_DEVICE_ID_ATI_RAGE128_U1, "R128Pro U1" }, |
725 { PCI_DEVICE_ID_ATI_RAGE128_U2, "R128Pro U2" }, | |
726 { PCI_DEVICE_ID_ATI_RAGE128_U3, "R128Pro U3" } | |
3164 | 727 #else |
728 /* Radeons (indeed: Rage 256 Pro ;) */ | |
2870 | 729 { PCI_DEVICE_ID_RADEON_QD, "Radeon QD " }, |
730 { PCI_DEVICE_ID_RADEON_QE, "Radeon QE " }, | |
731 { PCI_DEVICE_ID_RADEON_QF, "Radeon QF " }, | |
732 { PCI_DEVICE_ID_RADEON_QG, "Radeon QG " }, | |
733 { PCI_DEVICE_ID_RADEON_QY, "Radeon VE QY " }, | |
734 { PCI_DEVICE_ID_RADEON_QZ, "Radeon VE QZ " }, | |
735 { PCI_DEVICE_ID_RADEON_LY, "Radeon M6 LY " }, | |
736 { PCI_DEVICE_ID_RADEON_LZ, "Radeon M6 LZ " }, | |
737 { PCI_DEVICE_ID_RADEON_LW, "Radeon M7 LW " }, | |
738 { PCI_DEVICE_ID_R200_QL, "Radeon2 8500 QL " }, | |
739 { PCI_DEVICE_ID_RV200_QW, "Radeon2 7500 QW " } | |
3164 | 740 #endif |
2870 | 741 }; |
742 | |
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743 static int detected_chip; |
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744 |
2870 | 745 static int radeon_vid_config_card(void) |
746 { | |
747 struct pci_dev *dev = NULL; | |
748 size_t i; | |
749 | |
750 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) | |
751 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) | |
752 break; | |
3122 | 753 if(!dev) |
2870 | 754 { |
3164 | 755 printk(RVID_MSG"No supported cards found\n"); |
2870 | 756 return FALSE; |
757 } | |
758 | |
759 radeon_mmio_base = ioremap_nocache(pci_resource_start (dev, 2),RADEON_REGSIZE); | |
760 radeon_mem_base = dev->resource[0].start; | |
761 | |
3164 | 762 RTRACE(RVID_MSG"MMIO at 0x%p\n", radeon_mmio_base); |
763 RTRACE(RVID_MSG"Frame Buffer at 0x%08x\n", radeon_mem_base); | |
2870 | 764 |
3122 | 765 /* video memory size */ |
766 radeon_ram_size = INREG(CONFIG_MEMSIZE); | |
767 | |
3164 | 768 /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ |
3122 | 769 radeon_ram_size &= CONFIG_MEMSIZE_MASK; |
770 radeon_ram_size /= 0x100000; | |
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771 detected_chip = i; |
3164 | 772 printk(RVID_MSG"Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size); |
2870 | 773 |
774 return TRUE; | |
775 } | |
776 | |
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777 #define PARAM_BRIGHTNESS "brightness=" |
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778 #define PARAM_SATURATION "saturation=" |
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779 #define PARAM_DOUBLE_BUFF "double_buff=" |
2870 | 780 |
781 static ssize_t radeon_vid_read(struct file *file, char *buf, size_t count, loff_t *ppos) | |
782 { | |
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783 unsigned len,saturation; |
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784 long brightness; |
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785 brightness = besr.brightness; |
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786 saturation = besr.saturation; |
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787 len = 0; |
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788 len += sprintf(&buf[len],"Chip: %s\n",ati_card_ids[detected_chip].name); |
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789 len += sprintf(&buf[len],"Memory: %p:%x\n",radeon_mem_base,radeon_ram_size*0x100000); |
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790 len += sprintf(&buf[len],"MMIO: %p\n",radeon_mmio_base); |
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791 len += sprintf(&buf[len],"Configurable stuff:\n"); |
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792 len += sprintf(&buf[len],PARAM_DOUBLE_BUFF"%s\n",radeon_double_buff?"on":"off"); |
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793 len += sprintf(&buf[len],PARAM_BRIGHTNESS"%i\n",brightness); |
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794 len += sprintf(&buf[len],PARAM_SATURATION"%u\n",saturation); |
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795 return len; |
2870 | 796 } |
797 | |
798 static ssize_t radeon_vid_write(struct file *file, const char *buf, size_t count, loff_t *ppos) | |
799 { | |
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800 if(memcmp(buf,PARAM_BRIGHTNESS,min(count,strlen(PARAM_BRIGHTNESS))) == 0) |
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801 { |
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802 long brightness; |
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803 brightness=simple_strtol(&buf[strlen(PARAM_BRIGHTNESS)],NULL,10); |
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804 if(brightness >= -64 && brightness <= 63) |
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805 OUTREG(OV0_COLOUR_CNTL, (brightness & 0x7f) | |
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806 (besr.saturation << 8) | |
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807 (besr.saturation << 16)); |
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808 } |
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809 else |
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810 if(memcmp(buf,PARAM_SATURATION,min(count,strlen(PARAM_SATURATION))) == 0) |
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811 { |
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812 long saturation; |
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813 saturation=simple_strtol(&buf[strlen(PARAM_SATURATION)],NULL,10); |
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814 if(saturation >= 0 && saturation <= 31) |
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815 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) | |
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816 (saturation << 8) | |
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817 (saturation << 16)); |
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818 } |
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819 else |
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820 if(memcmp(buf,PARAM_DOUBLE_BUFF,min(count,strlen(PARAM_DOUBLE_BUFF))) == 0) |
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821 { |
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822 if(memcmp(&buf[strlen(PARAM_DOUBLE_BUFF)],"on",2) == 0) radeon_double_buff = 1; |
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823 else radeon_double_buff = 0; |
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824 } |
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825 radeon_vid_preset(); |
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826 return count; |
2870 | 827 } |
828 | |
829 static int radeon_vid_mmap(struct file *file, struct vm_area_struct *vma) | |
830 { | |
831 | |
3164 | 832 RTRACE(RVID_MSG"mapping video memory into userspace\n"); |
3019 | 833 if(remap_page_range(vma->vm_start, radeon_mem_base + radeon_overlay_off, |
2870 | 834 vma->vm_end - vma->vm_start, vma->vm_page_prot)) |
835 { | |
3164 | 836 printk(RVID_MSG"error mapping video memory\n"); |
2870 | 837 return(-EAGAIN); |
838 } | |
839 | |
840 return(0); | |
841 } | |
842 | |
843 static int radeon_vid_release(struct inode *inode, struct file *file) | |
844 { | |
845 radeon_vid_in_use = 0; | |
846 radeon_vid_stop_video(); | |
847 | |
848 MOD_DEC_USE_COUNT; | |
849 return 0; | |
850 } | |
851 | |
852 static long long radeon_vid_lseek(struct file *file, long long offset, int origin) | |
853 { | |
854 return -ESPIPE; | |
855 } | |
856 | |
857 static int radeon_vid_open(struct inode *inode, struct file *file) | |
858 { | |
859 int minor = MINOR(inode->i_rdev); | |
860 | |
861 if(minor != 0) | |
862 return(-ENXIO); | |
863 | |
864 if(radeon_vid_in_use == 1) | |
865 return(-EBUSY); | |
866 | |
867 radeon_vid_in_use = 1; | |
868 MOD_INC_USE_COUNT; | |
869 return(0); | |
870 } | |
871 | |
872 #if LINUX_VERSION_CODE >= 0x020400 | |
873 static struct file_operations radeon_vid_fops = | |
874 { | |
875 llseek: radeon_vid_lseek, | |
876 read: radeon_vid_read, | |
877 write: radeon_vid_write, | |
878 ioctl: radeon_vid_ioctl, | |
879 mmap: radeon_vid_mmap, | |
880 open: radeon_vid_open, | |
881 release: radeon_vid_release | |
882 }; | |
883 #else | |
884 static struct file_operations radeon_vid_fops = | |
885 { | |
886 radeon_vid_lseek, | |
887 radeon_vid_read, | |
888 radeon_vid_write, | |
889 NULL, | |
890 NULL, | |
891 radeon_vid_ioctl, | |
892 radeon_vid_mmap, | |
893 radeon_vid_open, | |
894 NULL, | |
895 radeon_vid_release | |
896 }; | |
897 #endif | |
898 | |
899 /* | |
900 * Main Initialization Function | |
901 */ | |
902 | |
903 | |
904 static int radeon_vid_initialize(void) | |
905 { | |
906 radeon_vid_in_use = 0; | |
3164 | 907 #ifdef RAGE128 |
908 printk(RVID_MSG"Rage128/Rage128Pro video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
909 #else | |
910 printk(RVID_MSG"Radeon video overlay driver v"RADEON_VID_VERSION" (C) Nick Kurshev\n"); | |
911 #endif | |
2870 | 912 if(register_chrdev(RADEON_VID_MAJOR, "radeon_vid", &radeon_vid_fops)) |
913 { | |
3164 | 914 printk(RVID_MSG"unable to get major: %d\n", RADEON_VID_MAJOR); |
2870 | 915 return -EIO; |
916 } | |
917 | |
918 if (!radeon_vid_config_card()) | |
919 { | |
3164 | 920 printk(RVID_MSG"can't configure this card\n"); |
2870 | 921 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
922 return -EINVAL; | |
923 } | |
924 radeon_vid_save_state(); | |
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925 radeon_vid_preset(); |
2870 | 926 return(0); |
927 } | |
928 | |
929 int init_module(void) | |
930 { | |
931 return radeon_vid_initialize(); | |
932 } | |
933 | |
934 void cleanup_module(void) | |
935 { | |
936 radeon_vid_restore_state(); | |
937 if(radeon_mmio_base) | |
938 iounmap(radeon_mmio_base); | |
939 | |
3164 | 940 RTRACE(RVID_MSG"Cleaning up module\n"); |
2870 | 941 unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid"); |
942 } | |
943 |