Mercurial > mplayer.hg
annotate cpudetect.c @ 18911:89af7441989b
Modifies behavior of -edlout
Now it creates a new file and writes edit decision list (EDL) records to it
just as it did before but instead of making pas-2-seconds blocks for each
'i' keystroke lets the user hits 'i' to mark the start or end of a block.
author | reynaldo |
---|---|
date | Wed, 05 Jul 2006 22:47:44 +0000 |
parents | 682a16136d6c |
children | 33c40d61bf33 |
rev | line source |
---|---|
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
1 #include "config.h" |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
4 |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
5 CpuCaps gCpuCaps; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
12 #if defined(ARCH_X86) || defined(ARCH_X86_64) |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
13 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
14 #include <stdio.h> |
8123
9fc45fe0d444
*HUGE* set of compiler warning fixes, unused variables removal
arpi
parents:
6135
diff
changeset
|
15 #include <string.h> |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
18 #include <sys/param.h> |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
19 #include <sys/sysctl.h> |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
20 #include <machine/cpu.h> |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
21 #endif |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
22 |
15566 | 23 #if defined(__FreeBSD__) || defined(__DragonFly__) |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
24 #include <sys/types.h> |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
25 #include <sys/sysctl.h> |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
26 #endif |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
27 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
28 #ifdef __linux__ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
29 #include <signal.h> |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
30 #endif |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
36 #ifdef __AMIGAOS4__ |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
37 #include <proto/exec.h> |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
38 #endif |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
39 |
2272 | 40 //#define X86_FXSR_MAGIC |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
41 /* Thanks to the FreeBSD project for some of this cpuid code, and |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
42 * help understanding how to use it. Thanks to the Mesa |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
43 * team for SSE support detection and more cpu detect code. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
44 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
45 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
46 /* I believe this code works. However, it has only been used on a PII and PIII */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
47 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
48 static void check_os_katmai_support( void ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
49 |
2272 | 50 #if 1 |
51 // return TRUE if cpuid supported | |
17566
f580a7755ac5
Patch by Stefan Huehner / stefan % huehner ! org \
rathann
parents:
16943
diff
changeset
|
52 static int has_cpuid(void) |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
53 { |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
54 long a, c; |
2272 | 55 |
56 // code from libavcodec: | |
57 __asm__ __volatile__ ( | |
58 /* See if CPUID instruction is supported ... */ | |
59 /* ... Get copies of EFLAGS into eax and ecx */ | |
60 "pushf\n\t" | |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
61 "pop %0\n\t" |
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
62 "mov %0, %1\n\t" |
2272 | 63 |
64 /* ... Toggle the ID bit in one copy and store */ | |
65 /* to the EFLAGS reg */ | |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
66 "xor $0x200000, %0\n\t" |
2272 | 67 "push %0\n\t" |
68 "popf\n\t" | |
69 | |
70 /* ... Get the (hopefully modified) EFLAGS */ | |
71 "pushf\n\t" | |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
72 "pop %0\n\t" |
2272 | 73 : "=a" (a), "=c" (c) |
74 : | |
75 : "cc" | |
76 ); | |
77 | |
78 return (a!=c); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
79 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
80 #endif |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
81 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
82 static void |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
83 do_cpuid(unsigned int ax, unsigned int *p) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
84 { |
2272 | 85 #if 0 |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
86 __asm __volatile( |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
87 "cpuid;" |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
88 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
89 : "0" (ax) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
90 ); |
2272 | 91 #else |
92 // code from libavcodec: | |
93 __asm __volatile | |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
94 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 95 "cpuid\n\t" |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
96 "xchg %%"REG_b", %%"REG_S |
3403 | 97 : "=a" (p[0]), "=S" (p[1]), |
2272 | 98 "=c" (p[2]), "=d" (p[3]) |
99 : "0" (ax)); | |
100 #endif | |
101 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
102 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
103 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
104 void GetCpuCaps( CpuCaps *caps) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
105 { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
106 unsigned int regs[4]; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
107 unsigned int regs2[4]; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
108 |
8860 | 109 memset(caps, 0, sizeof(*caps)); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
110 caps->isX86=1; |
8860 | 111 caps->cl_size=32; /* default */ |
2288 | 112 if (!has_cpuid()) { |
6134 | 113 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 114 return; |
115 } | |
116 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 117 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 118 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 119 if (regs[0]>=0x00000001) |
2280 | 120 { |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
121 char *tmpstr, *ptmpstr; |
8860 | 122 unsigned cl_size; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
123 |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
124 do_cpuid(0x00000001, regs2); |
2301 | 125 |
2288 | 126 caps->cpuType=(regs2[0] >> 8)&0xf; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
127 caps->cpuModel=(regs2[0] >> 4)&0xf; |
16662
77e35d3153b4
according to Intel/AMD official documentations, CPU family should be displayed as
gpoirier
parents:
15566
diff
changeset
|
128 |
77e35d3153b4
according to Intel/AMD official documentations, CPU family should be displayed as
gpoirier
parents:
15566
diff
changeset
|
129 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
77e35d3153b4
according to Intel/AMD official documentations, CPU family should be displayed as
gpoirier
parents:
15566
diff
changeset
|
130 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 131 if(caps->cpuType==0xf){ |
16662
77e35d3153b4
according to Intel/AMD official documentations, CPU family should be displayed as
gpoirier
parents:
15566
diff
changeset
|
132 // use extended family (P4, IA64, K8) |
77e35d3153b4
according to Intel/AMD official documentations, CPU family should be displayed as
gpoirier
parents:
15566
diff
changeset
|
133 caps->cpuType=0xf+((regs2[0]>>20)&255); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
134 } |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
135 if(caps->cpuType==0xf || caps->cpuType==6) |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
136 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
137 |
3403 | 138 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 139 |
140 // general feature flags: | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
141 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 142 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
143 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
144 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 145 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 146 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
147 if(cl_size) caps->cl_size = cl_size; | |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
148 |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
149 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
18816
be4e5d19a5b3
Typo: use ptmpstr instead of tmpstr to strip leading spaces + add
gpoirier
parents:
18538
diff
changeset
|
150 while(*ptmpstr == ' ') // strip leading spaces |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
151 ptmpstr++; |
18816
be4e5d19a5b3
Typo: use ptmpstr instead of tmpstr to strip leading spaces + add
gpoirier
parents:
18538
diff
changeset
|
152 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
153 free(tmpstr); |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
154 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
155 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
10885
685c416f12b5
cpuspeed detection for X86 TSC capable CPUs (also added TSC detection, should best be verified by some people with TSC/nonTSC capable CPUs)
atmos4
parents:
10823
diff
changeset
|
156 |
2288 | 157 } |
158 do_cpuid(0x80000000, regs); | |
159 if (regs[0]>=0x80000001) { | |
6134 | 160 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 161 do_cpuid(0x80000001, regs2); |
3840 | 162 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
163 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 164 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
165 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
166 } | |
8860 | 167 if(regs[0]>=0x80000006) |
168 { | |
169 do_cpuid(0x80000006, regs2); | |
170 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
171 caps->cl_size = regs2[2] & 0xFF; | |
172 } | |
16943
fab832f37083
Do not show cache-line size message, I've never seen a case where it was useful
reimar
parents:
16662
diff
changeset
|
173 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 174 #if 0 |
5937 | 175 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 176 gCpuCaps.hasMMX, |
177 gCpuCaps.hasMMX2, | |
178 gCpuCaps.hasSSE, | |
179 gCpuCaps.hasSSE2, | |
180 gCpuCaps.has3DNow, | |
181 gCpuCaps.has3DNowExt ); | |
182 #endif | |
183 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
184 /* FIXME: Does SSE2 need more OS support, too? */ |
15566 | 185 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
186 if (caps->hasSSE) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
187 check_os_katmai_support(); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
188 if (!caps->hasSSE) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
189 caps->hasSSE2 = 0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
190 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
191 caps->hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
192 caps->hasSSE2 = 0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
193 #endif |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
194 // caps->has3DNow=1; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
195 // caps->hasMMX2 = 0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
196 // caps->hasMMX = 0; |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
197 |
4829 | 198 #ifndef HAVE_MMX |
6134 | 199 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 200 caps->hasMMX=0; |
201 #endif | |
202 #ifndef HAVE_MMX2 | |
6134 | 203 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 204 caps->hasMMX2=0; |
205 #endif | |
206 #ifndef HAVE_SSE | |
6134 | 207 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 208 caps->hasSSE=0; |
209 #endif | |
210 #ifndef HAVE_SSE2 | |
6134 | 211 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 212 caps->hasSSE2=0; |
213 #endif | |
214 #ifndef HAVE_3DNOW | |
6134 | 215 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 216 caps->has3DNow=0; |
217 #endif | |
218 #ifndef HAVE_3DNOWEX | |
6134 | 219 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 220 caps->has3DNowExt=0; |
221 #endif | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
222 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
223 |
2301 | 224 |
225 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
226 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
227 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
228 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
229 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
230 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
231 | |
232 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
233 #include "cputable.h" /* get cpuname and cpuvendors */ | |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
234 char vendor[13]; |
2303 | 235 char *retname; |
13628 | 236 int i; |
2301 | 237 |
18869 | 238 if (NULL==(retname=malloc(256))) { |
5937 | 239 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 240 exit(1); |
241 } | |
242 | |
3837 | 243 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
244 |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
245 do_cpuid(0x80000000,regs); |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
246 if (regs[0] >= 0x80000004) |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
247 { |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
248 // CPU has built-in namestring |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
249 retname[0] = '\0'; |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
250 for (i = 0x80000002; i <= 0x80000004; i++) |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
251 { |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
252 do_cpuid(i, regs); |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
253 strncat(retname, (char*)regs, 16); |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
254 } |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
255 return retname; |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
256 } |
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
257 |
2301 | 258 for(i=0; i<MAX_VENDORS; i++){ |
259 if(!strcmp(cpuvendors[i].string,vendor)){ | |
260 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 261 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 262 } else { |
13628 | 263 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 264 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
265 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
266 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
267 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
268 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
269 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
270 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 271 "to the MPlayer-Developers, so we can add it to the list!\n"); |
272 } | |
273 } | |
274 } | |
14478 | 275 retname[255] = 0; |
2301 | 276 |
277 //printf("Detected CPU: %s\n", retname); | |
278 return retname; | |
279 } | |
280 | |
281 #undef CPUID_EXTFAMILY | |
282 #undef CPUID_EXTMODEL | |
283 #undef CPUID_TYPE | |
284 #undef CPUID_FAMILY | |
285 #undef CPUID_MODEL | |
286 #undef CPUID_STEPPING | |
287 | |
288 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
289 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
290 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
291 { |
6134 | 292 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
293 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
294 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
295 * instructions are 3 bytes long. We must increment the instruction |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
296 * pointer manually to avoid repeated execution of the offending |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
297 * instruction. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
298 * |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
299 * If the SIGILL is caused by a divide-by-zero when unmasked |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
300 * exceptions aren't supported, the SIMD FPU status and control |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
301 * word will be restored at the end of the test, so we don't need |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
302 * to worry about doing it here. Besides, we may not be able to... |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
303 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
304 sc.eip += 3; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
305 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
306 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
307 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
308 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
309 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
310 { |
6134 | 311 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
312 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
313 if ( sc.fpstate->magic != 0xffff ) { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
314 /* Our signal context has the extended FPU state, so reset the |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
315 * divide-by-zero exception mask and clear the divide-by-zero |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
316 * exception bit. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
317 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
318 sc.fpstate->mxcsr |= 0x00000200; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
319 sc.fpstate->mxcsr &= 0xfffffffb; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
320 } else { |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
321 /* If we ever get here, we're completely hosed. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
322 */ |
6134 | 323 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
324 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
325 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
326 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
327 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
328 |
10440 | 329 #ifdef WIN32 |
330 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
331 { | |
332 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
333 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
334 ep->ContextRecord->Eip +=3; | |
335 gCpuCaps.hasSSE=0; | |
336 return EXCEPTION_CONTINUE_EXECUTION; | |
337 } | |
338 return EXCEPTION_CONTINUE_SEARCH; | |
339 } | |
340 #endif /* WIN32 */ | |
341 | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
342 /* If we're running on a processor that can do SSE, let's see if we |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
343 * are allowed to or not. This will catch 2.4.0 or later kernels that |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
344 * haven't been configured for a Pentium III but are running on one, |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
345 * and RedHat patched 2.2 kernels that have broken exception handling |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
346 * support for user space apps that do SSE. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
347 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
348 static void check_os_katmai_support( void ) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
349 { |
14455 | 350 #ifdef ARCH_X86_64 |
351 gCpuCaps.hasSSE=1; | |
352 gCpuCaps.hasSSE2=1; | |
15566 | 353 #elif defined(__FreeBSD__) || defined(__DragonFly__) |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
354 int has_sse=0, ret; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
355 size_t len=sizeof(has_sse); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
356 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
357 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
358 if (ret || !has_sse) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
359 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
360 |
12143 | 361 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
362 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
363 int has_sse, has_sse2, ret, mib[2]; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
364 size_t varlen; |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
365 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
366 mib[0] = CTL_MACHDEP; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
367 mib[1] = CPU_SSE; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
368 varlen = sizeof(has_sse); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
369 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
370 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
371 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
372 if (ret < 0 || !has_sse) { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
373 gCpuCaps.hasSSE=0; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
374 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
375 } else { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
376 gCpuCaps.hasSSE=1; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
377 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
378 } |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
379 |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
380 mib[1] = CPU_SSE2; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
381 varlen = sizeof(has_sse2); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
382 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
383 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
384 if (ret < 0 || !has_sse2) { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
385 gCpuCaps.hasSSE2=0; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
386 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
387 } else { |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
388 gCpuCaps.hasSSE2=1; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
389 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
390 } |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
391 #else |
8533
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
changeset
|
392 gCpuCaps.hasSSE = 0; |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
393 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
8123
diff
changeset
|
394 #endif |
10440 | 395 #elif defined(WIN32) |
396 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
397 if ( gCpuCaps.hasSSE ) { | |
398 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
399 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
400 __asm __volatile ("xorps %xmm0, %xmm0"); | |
401 SetUnhandledExceptionFilter(exc_fil); | |
402 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
403 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
404 } | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
405 #elif defined(__linux__) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
406 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
407 struct sigaction saved_sigill; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
408 struct sigaction saved_sigfpe; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
409 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
410 /* Save the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
411 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
412 sigaction( SIGILL, NULL, &saved_sigill ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
413 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
414 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
415 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
416 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
417 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
418 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
419 * supports the extended FPU save and restore required for SSE. If |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
420 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
421 * doesn't support Streaming SIMD Exceptions, even if the processor |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
422 * does. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
423 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
424 if ( gCpuCaps.hasSSE ) { |
6134 | 425 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
426 |
2272 | 427 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
428 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
429 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
430 if ( gCpuCaps.hasSSE ) { |
6134 | 431 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
432 } else { |
6134 | 433 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
434 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
435 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
436 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
437 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
438 * it supports unmasked SIMD FPU exceptions. If we unmask the |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
439 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
440 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
441 * as expected, we're okay but we need to clean up after it. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
442 * |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
443 * Are we being too stringent in our requirement that the OS support |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
444 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
445 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
446 * doesn't even support them. We at least know the user-space SSE |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
447 * support is good in kernels that do support unmasked exceptions, |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
448 * and therefore to be safe I'm going to leave this test in here. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
449 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
450 if ( gCpuCaps.hasSSE ) { |
6134 | 451 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
452 |
2272 | 453 // test_os_katmai_exception_support(); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
454 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
455 if ( gCpuCaps.hasSSE ) { |
6134 | 456 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
457 } else { |
6134 | 458 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
459 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
460 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
461 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
462 /* Restore the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
463 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
464 sigaction( SIGILL, &saved_sigill, NULL ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
465 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
466 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
467 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
468 * safe to go ahead and hook out the SSE code throughout Mesa. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
469 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
470 if ( gCpuCaps.hasSSE ) { |
6134 | 471 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
472 } else { |
6134 | 473 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
474 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
475 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
476 /* We can't use POSIX signal handling to test the availability of |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
477 * SSE, so we disable it by default. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
478 */ |
5937 | 479 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
480 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
481 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
482 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
483 /* Do nothing on other platforms for now. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
484 */ |
6134 | 485 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
486 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
487 #endif /* __linux__ */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
488 } |
13720
821f464b4d90
adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64
aurel
parents:
13628
diff
changeset
|
489 #else /* ARCH_X86 || ARCH_X86_64 */ |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
490 |
9003 | 491 #ifdef SYS_DARWIN |
492 #include <sys/sysctl.h> | |
493 #else | |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
494 #ifndef __AMIGAOS4__ |
9003 | 495 #include <signal.h> |
496 #include <setjmp.h> | |
497 | |
498 static sigjmp_buf jmpbuf; | |
499 static volatile sig_atomic_t canjump = 0; | |
500 | |
501 static void sigill_handler (int sig) | |
502 { | |
503 if (!canjump) { | |
504 signal (sig, SIG_DFL); | |
505 raise (sig); | |
506 } | |
507 | |
508 canjump = 0; | |
509 siglongjmp (jmpbuf, 1); | |
510 } | |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
511 #endif //__AMIGAOS4__ |
9003 | 512 #endif |
513 | |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
514 void GetCpuCaps( CpuCaps *caps) |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
515 { |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
516 caps->cpuType=0; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
517 caps->cpuModel=0; |
3403 | 518 caps->cpuStepping=0; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
519 caps->hasMMX=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
520 caps->hasMMX2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
521 caps->has3DNow=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
522 caps->has3DNowExt=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
523 caps->hasSSE=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
524 caps->hasSSE2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
525 caps->isX86=0; |
9003 | 526 caps->hasAltiVec = 0; |
527 #ifdef HAVE_ALTIVEC | |
528 #ifdef SYS_DARWIN | |
529 /* | |
530 rip-off from ffmpeg altivec detection code. | |
531 this code also appears on Apple's AltiVec pages. | |
532 */ | |
533 { | |
534 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
535 int has_vu = 0; | |
536 size_t len = sizeof(has_vu); | |
537 int err; | |
538 | |
539 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
540 | |
541 if (err == 0) | |
542 if (has_vu != 0) | |
543 caps->hasAltiVec = 1; | |
544 } | |
545 #else /* SYS_DARWIN */ | |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
546 #ifdef __AMIGAOS4__ |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
547 ULONG result = 0; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
548 |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
549 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
550 if (result == VECTORTYPE_ALTIVEC) |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
551 caps->hasAltiVec = 1; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
552 #else |
9003 | 553 /* no Darwin, do it the brute-force way */ |
554 /* this is borrowed from the libmpeg2 library */ | |
555 { | |
556 signal (SIGILL, sigill_handler); | |
557 if (sigsetjmp (jmpbuf, 1)) { | |
558 signal (SIGILL, SIG_DFL); | |
559 } else { | |
560 canjump = 1; | |
561 | |
562 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 563 "vand %%v0, %%v0, %%v0" |
9003 | 564 : |
565 : "r" (-1)); | |
566 | |
567 signal (SIGILL, SIG_DFL); | |
568 caps->hasAltiVec = 1; | |
569 } | |
570 } | |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
571 #endif //__AMIGAOS4__ |
9003 | 572 #endif /* SYS_DARWIN */ |
9324 | 573 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 574 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
575 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
576 #ifdef ARCH_IA64 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
577 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
578 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
579 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
580 #ifdef ARCH_SPARC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
581 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
582 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
583 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
584 #ifdef ARCH_ARMV4L |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
585 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
586 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
587 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
588 #ifdef ARCH_POWERPC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
589 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
590 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
591 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
592 #ifdef ARCH_ALPHA |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
593 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
594 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
595 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
596 #ifdef ARCH_SGI_MIPS |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
597 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
598 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
599 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
600 #ifdef ARCH_PA_RISC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
601 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
602 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
603 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
604 #ifdef ARCH_S390 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
605 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
606 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
607 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
608 #ifdef ARCH_S390X |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
609 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
610 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
611 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
612 #ifdef ARCH_VAX |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
613 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
614 #endif |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
615 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
616 #endif /* !ARCH_X86 */ |