Mercurial > mplayer.hg
annotate cpudetect.c @ 25434:8c4c1abcac50
Calculate and draw osd accurately.
author | ulion |
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date | Wed, 19 Dec 2007 09:34:28 +0000 |
parents | b6107034e981 |
children | a48a280fc0e1 |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
20577 | 12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
21848 | 23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
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36 #ifdef __AMIGAOS4__ |
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37 #include <proto/exec.h> |
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38 #endif |
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39 |
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40 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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41 * help understanding how to use it. Thanks to the Mesa |
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42 * team for SSE support detection and more cpu detect code. |
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43 */ |
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44 |
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45 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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46 |
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47 static void check_os_katmai_support( void ); |
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48 |
2272 | 49 #if 1 |
50 // return TRUE if cpuid supported | |
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51 static int has_cpuid(void) |
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52 { |
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53 long a, c; |
2272 | 54 |
55 // code from libavcodec: | |
56 __asm__ __volatile__ ( | |
57 /* See if CPUID instruction is supported ... */ | |
58 /* ... Get copies of EFLAGS into eax and ecx */ | |
59 "pushf\n\t" | |
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60 "pop %0\n\t" |
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61 "mov %0, %1\n\t" |
2272 | 62 |
63 /* ... Toggle the ID bit in one copy and store */ | |
64 /* to the EFLAGS reg */ | |
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65 "xor $0x200000, %0\n\t" |
2272 | 66 "push %0\n\t" |
67 "popf\n\t" | |
68 | |
69 /* ... Get the (hopefully modified) EFLAGS */ | |
70 "pushf\n\t" | |
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71 "pop %0\n\t" |
2272 | 72 : "=a" (a), "=c" (c) |
73 : | |
74 : "cc" | |
75 ); | |
76 | |
77 return (a!=c); | |
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78 } |
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79 #endif |
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80 |
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81 static void |
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82 do_cpuid(unsigned int ax, unsigned int *p) |
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83 { |
2272 | 84 #if 0 |
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85 __asm __volatile( |
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86 "cpuid;" |
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87 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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88 : "0" (ax) |
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89 ); |
2272 | 90 #else |
91 // code from libavcodec: | |
92 __asm __volatile | |
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93 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 94 "cpuid\n\t" |
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95 "xchg %%"REG_b", %%"REG_S |
3403 | 96 : "=a" (p[0]), "=S" (p[1]), |
2272 | 97 "=c" (p[2]), "=d" (p[3]) |
98 : "0" (ax)); | |
99 #endif | |
100 | |
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101 } |
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102 |
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103 void GetCpuCaps( CpuCaps *caps) |
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104 { |
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105 unsigned int regs[4]; |
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106 unsigned int regs2[4]; |
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107 |
8860 | 108 memset(caps, 0, sizeof(*caps)); |
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109 caps->isX86=1; |
8860 | 110 caps->cl_size=32; /* default */ |
2288 | 111 if (!has_cpuid()) { |
6134 | 112 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 113 return; |
114 } | |
115 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 116 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 117 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 118 if (regs[0]>=0x00000001) |
2280 | 119 { |
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120 char *tmpstr, *ptmpstr; |
8860 | 121 unsigned cl_size; |
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122 |
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123 do_cpuid(0x00000001, regs2); |
2301 | 124 |
2288 | 125 caps->cpuType=(regs2[0] >> 8)&0xf; |
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126 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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127 |
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128 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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129 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 130 if(caps->cpuType==0xf){ |
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131 // use extended family (P4, IA64, K8) |
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132 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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133 } |
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134 if(caps->cpuType==0xf || caps->cpuType==6) |
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135 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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136 |
3403 | 137 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 138 |
139 // general feature flags: | |
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140 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 141 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
142 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
143 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 144 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 145 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
146 if(cl_size) caps->cl_size = cl_size; | |
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147 |
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148 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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149 while(*ptmpstr == ' ') // strip leading spaces |
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150 ptmpstr++; |
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151 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
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152 free(tmpstr); |
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153 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
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154 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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155 |
2288 | 156 } |
157 do_cpuid(0x80000000, regs); | |
158 if (regs[0]>=0x80000001) { | |
6134 | 159 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 160 do_cpuid(0x80000001, regs2); |
3840 | 161 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
162 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 163 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
164 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
165 } | |
8860 | 166 if(regs[0]>=0x80000006) |
167 { | |
168 do_cpuid(0x80000006, regs2); | |
169 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
170 caps->cl_size = regs2[2] & 0xFF; | |
171 } | |
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172 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 173 #if 0 |
5937 | 174 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 175 gCpuCaps.hasMMX, |
176 gCpuCaps.hasMMX2, | |
177 gCpuCaps.hasSSE, | |
178 gCpuCaps.hasSSE2, | |
179 gCpuCaps.has3DNow, | |
180 gCpuCaps.has3DNowExt ); | |
181 #endif | |
182 | |
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183 /* FIXME: Does SSE2 need more OS support, too? */ |
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184 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) || defined(__APPLE__) || defined(__MINGW32__) |
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185 if (caps->hasSSE) |
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186 check_os_katmai_support(); |
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187 if (!caps->hasSSE) |
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188 caps->hasSSE2 = 0; |
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189 #else |
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190 caps->hasSSE=0; |
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191 caps->hasSSE2 = 0; |
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192 #endif |
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193 // caps->has3DNow=1; |
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194 // caps->hasMMX2 = 0; |
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195 // caps->hasMMX = 0; |
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196 |
4829 | 197 #ifndef HAVE_MMX |
6134 | 198 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 199 caps->hasMMX=0; |
200 #endif | |
201 #ifndef HAVE_MMX2 | |
6134 | 202 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 203 caps->hasMMX2=0; |
204 #endif | |
205 #ifndef HAVE_SSE | |
6134 | 206 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 207 caps->hasSSE=0; |
208 #endif | |
209 #ifndef HAVE_SSE2 | |
6134 | 210 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 211 caps->hasSSE2=0; |
212 #endif | |
213 #ifndef HAVE_3DNOW | |
6134 | 214 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 215 caps->has3DNow=0; |
216 #endif | |
217 #ifndef HAVE_3DNOWEX | |
6134 | 218 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 219 caps->has3DNowExt=0; |
220 #endif | |
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221 } |
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222 |
2301 | 223 |
224 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
225 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
226 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
227 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
228 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
229 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
230 | |
231 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
232 #include "cputable.h" /* get cpuname and cpuvendors */ | |
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233 char vendor[13]; |
2303 | 234 char *retname; |
13628 | 235 int i; |
2301 | 236 |
18869 | 237 if (NULL==(retname=malloc(256))) { |
5937 | 238 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 239 exit(1); |
240 } | |
241 | |
3837 | 242 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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243 |
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244 do_cpuid(0x80000000,regs); |
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245 if (regs[0] >= 0x80000004) |
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246 { |
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247 // CPU has built-in namestring |
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248 retname[0] = '\0'; |
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249 for (i = 0x80000002; i <= 0x80000004; i++) |
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250 { |
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251 do_cpuid(i, regs); |
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252 strncat(retname, (char*)regs, 16); |
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253 } |
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254 return retname; |
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255 } |
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256 |
2301 | 257 for(i=0; i<MAX_VENDORS; i++){ |
258 if(!strcmp(cpuvendors[i].string,vendor)){ | |
259 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 260 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 261 } else { |
13628 | 262 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 263 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
264 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
265 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
266 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
267 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
268 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
269 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 270 "to the MPlayer-Developers, so we can add it to the list!\n"); |
271 } | |
272 } | |
273 } | |
14478 | 274 retname[255] = 0; |
2301 | 275 |
276 //printf("Detected CPU: %s\n", retname); | |
277 return retname; | |
278 } | |
279 | |
280 #undef CPUID_EXTFAMILY | |
281 #undef CPUID_EXTMODEL | |
282 #undef CPUID_TYPE | |
283 #undef CPUID_FAMILY | |
284 #undef CPUID_MODEL | |
285 #undef CPUID_STEPPING | |
286 | |
287 | |
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288 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64) |
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289 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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290 { |
6134 | 291 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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292 |
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293 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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294 * instructions are 3 bytes long. We must increment the instruction |
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295 * pointer manually to avoid repeated execution of the offending |
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296 * instruction. |
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297 * |
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298 * If the SIGILL is caused by a divide-by-zero when unmasked |
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299 * exceptions aren't supported, the SIMD FPU status and control |
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300 * word will be restored at the end of the test, so we don't need |
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301 * to worry about doing it here. Besides, we may not be able to... |
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302 */ |
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303 sc.eip += 3; |
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304 |
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305 gCpuCaps.hasSSE=0; |
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306 } |
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307 #endif /* __linux__ && _POSIX_SOURCE */ |
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308 |
10440 | 309 #ifdef WIN32 |
310 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
311 { | |
312 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
313 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
314 ep->ContextRecord->Eip +=3; | |
315 gCpuCaps.hasSSE=0; | |
316 return EXCEPTION_CONTINUE_EXECUTION; | |
317 } | |
318 return EXCEPTION_CONTINUE_SEARCH; | |
319 } | |
320 #endif /* WIN32 */ | |
321 | |
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322 /* If we're running on a processor that can do SSE, let's see if we |
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323 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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324 * haven't been configured for a Pentium III but are running on one, |
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325 * and RedHat patched 2.2 kernels that have broken exception handling |
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326 * support for user space apps that do SSE. |
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327 */ |
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328 |
21848 | 329 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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330 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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331 #elif defined(__APPLE__) |
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332 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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333 #endif |
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334 |
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335 static void check_os_katmai_support( void ) |
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336 { |
14455 | 337 #ifdef ARCH_X86_64 |
338 gCpuCaps.hasSSE=1; | |
339 gCpuCaps.hasSSE2=1; | |
21848 | 340 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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341 int has_sse=0, ret; |
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342 size_t len=sizeof(has_sse); |
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343 |
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344 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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345 if (ret || !has_sse) |
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346 gCpuCaps.hasSSE=0; |
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347 |
12143 | 348 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
349 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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350 int has_sse, has_sse2, ret, mib[2]; |
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351 size_t varlen; |
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352 |
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353 mib[0] = CTL_MACHDEP; |
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354 mib[1] = CPU_SSE; |
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355 varlen = sizeof(has_sse); |
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356 |
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357 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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358 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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359 if (ret < 0 || !has_sse) { |
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arpi
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360 gCpuCaps.hasSSE=0; |
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361 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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362 } else { |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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363 gCpuCaps.hasSSE=1; |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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364 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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365 } |
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Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
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366 |
8533
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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367 mib[1] = CPU_SSE2; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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368 varlen = sizeof(has_sse2); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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369 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
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370 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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371 if (ret < 0 || !has_sse2) { |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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372 gCpuCaps.hasSSE2=0; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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373 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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diff
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374 } else { |
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
diff
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375 gCpuCaps.hasSSE2=1; |
9b73b801af55
Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
8401
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376 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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diff
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|
377 } |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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diff
changeset
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378 #else |
8533
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Ok, here is a better patch, which even adds a fix to compile it on older
arpi
parents:
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379 gCpuCaps.hasSSE = 0; |
8401
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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changeset
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380 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
1b2fc92980d9
Runtime SSE detection for NEtBSD, patch by Nick Hudson <skrll at netbsd.org>
atmos4
parents:
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changeset
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381 #endif |
10440 | 382 #elif defined(WIN32) |
383 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
384 if ( gCpuCaps.hasSSE ) { | |
385 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
386 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
387 __asm __volatile ("xorps %xmm0, %xmm0"); | |
388 SetUnhandledExceptionFilter(exc_fil); | |
389 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
390 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
391 } | |
2268
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arpi
parents:
diff
changeset
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392 #elif defined(__linux__) |
24439
680bc9411ecf
Do not check for X86_FXSR_MAGIC define, it is missing in newer
reimar
parents:
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changeset
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393 #if defined(_POSIX_SOURCE) |
2268
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arpi
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394 struct sigaction saved_sigill; |
72ff2179d396
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arpi
parents:
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395 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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396 /* Save the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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397 */ |
72ff2179d396
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arpi
parents:
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398 sigaction( SIGILL, NULL, &saved_sigill ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
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changeset
|
399 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
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400 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
72ff2179d396
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arpi
parents:
diff
changeset
|
401 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
402 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
403 * supports the extended FPU save and restore required for SSE. If |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
404 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
72ff2179d396
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arpi
parents:
diff
changeset
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405 * doesn't support Streaming SIMD Exceptions, even if the processor |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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406 * does. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
407 */ |
72ff2179d396
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arpi
parents:
diff
changeset
|
408 if ( gCpuCaps.hasSSE ) { |
6134 | 409 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
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arpi
parents:
diff
changeset
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410 |
2272 | 411 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
412 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
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arpi
parents:
diff
changeset
|
413 |
72ff2179d396
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arpi
parents:
diff
changeset
|
414 if ( gCpuCaps.hasSSE ) { |
6134 | 415 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
2268
72ff2179d396
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arpi
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diff
changeset
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416 } else { |
6134 | 417 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
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arpi
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418 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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419 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
420 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
421 /* Restore the original signal handlers. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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422 */ |
72ff2179d396
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arpi
parents:
diff
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423 sigaction( SIGILL, &saved_sigill, NULL ); |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
424 |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
425 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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426 * safe to go ahead and hook out the SSE code throughout Mesa. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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427 */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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428 if ( gCpuCaps.hasSSE ) { |
6134 | 429 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
2268
72ff2179d396
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arpi
parents:
diff
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430 } else { |
6134 | 431 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
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|
432 } |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
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433 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
434 /* We can't use POSIX signal handling to test the availability of |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
435 * SSE, so we disable it by default. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
436 */ |
5937 | 437 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
2268
72ff2179d396
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arpi
parents:
diff
changeset
|
438 gCpuCaps.hasSSE=0; |
24439
680bc9411ecf
Do not check for X86_FXSR_MAGIC define, it is missing in newer
reimar
parents:
24438
diff
changeset
|
439 #endif /* _POSIX_SOURCE */ |
2268
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
440 #else |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
441 /* Do nothing on other platforms for now. |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
442 */ |
6134 | 443 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
2268
72ff2179d396
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arpi
parents:
diff
changeset
|
444 gCpuCaps.hasSSE=0; |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
445 #endif /* __linux__ */ |
72ff2179d396
cpu detect code by Eric Anholt <eanholt@gladstone.uoregon.edu>
arpi
parents:
diff
changeset
|
446 } |
20577 | 447 #else /* ARCH_X86 */ |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
448 |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
449 #ifdef __APPLE__ |
9003 | 450 #include <sys/sysctl.h> |
25338
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
451 #elif __AMIGAOS4__ |
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
452 /* nothing */ |
dfba06821076
Ahem, fix breakage of last commit: The AltiVec detection code has three
diego
parents:
25330
diff
changeset
|
453 #else |
9003 | 454 #include <signal.h> |
455 #include <setjmp.h> | |
456 | |
457 static sigjmp_buf jmpbuf; | |
458 static volatile sig_atomic_t canjump = 0; | |
459 | |
460 static void sigill_handler (int sig) | |
461 { | |
462 if (!canjump) { | |
463 signal (sig, SIG_DFL); | |
464 raise (sig); | |
465 } | |
466 | |
467 canjump = 0; | |
468 siglongjmp (jmpbuf, 1); | |
469 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
470 #endif /* __APPLE__ */ |
9003 | 471 |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
472 void GetCpuCaps( CpuCaps *caps) |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
473 { |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
474 caps->cpuType=0; |
18538
739849dfb699
Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
gpoirier
parents:
17702
diff
changeset
|
475 caps->cpuModel=0; |
3403 | 476 caps->cpuStepping=0; |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
477 caps->hasMMX=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
478 caps->hasMMX2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
479 caps->has3DNow=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
480 caps->has3DNowExt=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
481 caps->hasSSE=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
482 caps->hasSSE2=0; |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
483 caps->isX86=0; |
9003 | 484 caps->hasAltiVec = 0; |
485 #ifdef HAVE_ALTIVEC | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
486 #ifdef __APPLE__ |
9003 | 487 /* |
488 rip-off from ffmpeg altivec detection code. | |
489 this code also appears on Apple's AltiVec pages. | |
490 */ | |
491 { | |
492 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
493 int has_vu = 0; | |
494 size_t len = sizeof(has_vu); | |
495 int err; | |
496 | |
497 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
498 | |
499 if (err == 0) | |
500 if (has_vu != 0) | |
501 caps->hasAltiVec = 1; | |
502 } | |
25339 | 503 #elif __AMIGAOS4__ |
17702
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
504 ULONG result = 0; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
505 |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
parents:
17566
diff
changeset
|
506 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
507 if (result == VECTORTYPE_ALTIVEC) |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
508 caps->hasAltiVec = 1; |
485f04e5a58c
add Amiga-style AltiVec detection, patch from andrea at amigasoft dot net
pacman
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17566
diff
changeset
|
509 #else |
9003 | 510 /* no Darwin, do it the brute-force way */ |
511 /* this is borrowed from the libmpeg2 library */ | |
512 { | |
513 signal (SIGILL, sigill_handler); | |
514 if (sigsetjmp (jmpbuf, 1)) { | |
515 signal (SIGILL, SIG_DFL); | |
516 } else { | |
517 canjump = 1; | |
518 | |
519 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 520 "vand %%v0, %%v0, %%v0" |
9003 | 521 : |
522 : "r" (-1)); | |
523 | |
524 signal (SIGILL, SIG_DFL); | |
525 caps->hasAltiVec = 1; | |
526 } | |
527 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
528 #endif /* __APPLE__ */ |
9324 | 529 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 530 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
531 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
532 #ifdef ARCH_IA64 |
909093c314e9
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gabucino
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10955
diff
changeset
|
533 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
534 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
535 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
536 #ifdef ARCH_SPARC |
909093c314e9
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gabucino
parents:
10955
diff
changeset
|
537 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
538 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
539 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
540 #ifdef ARCH_ARMV4L |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
541 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
542 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
543 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
544 #ifdef ARCH_POWERPC |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
545 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
546 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
547 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
548 #ifdef ARCH_ALPHA |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
549 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
909093c314e9
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550 #endif |
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551 |
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552 #ifdef ARCH_SGI_MIPS |
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553 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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554 #endif |
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555 |
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556 #ifdef ARCH_PA_RISC |
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557 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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558 #endif |
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559 |
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560 #ifdef ARCH_S390 |
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561 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
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562 #endif |
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563 |
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564 #ifdef ARCH_S390X |
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565 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
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566 #endif |
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567 |
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568 #ifdef ARCH_VAX |
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569 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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570 #endif |
25340 | 571 |
572 #ifdef ARCH_XTENSA | |
573 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" ); | |
574 #endif | |
3146
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575 } |
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576 #endif /* !ARCH_X86 */ |