Mercurial > mplayer.hg
annotate cpudetect.c @ 28215:8c9029514722
Simplify phony target declaration.
author | diego |
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date | Sun, 04 Jan 2009 23:27:03 +0000 |
parents | 138bd0e1d9d8 |
children | 107b2f961b9a |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
20577 | 12 #ifdef ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
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23 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
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32 #if defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 33 #include <windows.h> |
34 #endif | |
35 | |
26061 | 36 #ifdef __OS2__ |
37 #define INCL_DOS | |
38 #include <os2.h> | |
39 #endif | |
40 | |
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41 #ifdef __AMIGAOS4__ |
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42 #include <proto/exec.h> |
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43 #endif |
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44 |
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45 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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46 * help understanding how to use it. Thanks to the Mesa |
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47 * team for SSE support detection and more cpu detect code. |
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48 */ |
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49 |
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50 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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51 |
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52 static void check_os_katmai_support( void ); |
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53 |
2272 | 54 // return TRUE if cpuid supported |
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55 static int has_cpuid(void) |
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56 { |
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57 long a, c; |
2272 | 58 |
59 // code from libavcodec: | |
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60 #ifdef ARCH_X86_64 |
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61 #define PUSHF "pushfq\n\t" |
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62 #define POPF "popfq\n\t" |
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63 #else |
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64 #define PUSHF "pushfl\n\t" |
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65 #define POPF "popfl\n\t" |
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66 #endif |
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67 __asm__ volatile ( |
2272 | 68 /* See if CPUID instruction is supported ... */ |
69 /* ... Get copies of EFLAGS into eax and ecx */ | |
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70 PUSHF |
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71 "pop %0\n\t" |
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72 "mov %0, %1\n\t" |
2272 | 73 |
74 /* ... Toggle the ID bit in one copy and store */ | |
75 /* to the EFLAGS reg */ | |
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76 "xor $0x200000, %0\n\t" |
2272 | 77 "push %0\n\t" |
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78 POPF |
2272 | 79 |
80 /* ... Get the (hopefully modified) EFLAGS */ | |
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81 PUSHF |
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82 "pop %0\n\t" |
2272 | 83 : "=a" (a), "=c" (c) |
84 : | |
85 : "cc" | |
86 ); | |
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87 #undef PUSHF |
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88 #undef POPF |
2272 | 89 |
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90 return a != c; |
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91 } |
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92 |
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93 static void |
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94 do_cpuid(unsigned int ax, unsigned int *p) |
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95 { |
2272 | 96 #if 0 |
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97 __asm__ volatile( |
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98 "cpuid;" |
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99 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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100 : "0" (ax) |
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101 ); |
2272 | 102 #else |
103 // code from libavcodec: | |
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104 __asm__ volatile |
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105 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 106 "cpuid\n\t" |
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107 "xchg %%"REG_b", %%"REG_S |
3403 | 108 : "=a" (p[0]), "=S" (p[1]), |
2272 | 109 "=c" (p[2]), "=d" (p[3]) |
110 : "0" (ax)); | |
111 #endif | |
112 | |
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113 } |
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114 |
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115 void GetCpuCaps( CpuCaps *caps) |
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116 { |
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117 unsigned int regs[4]; |
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118 unsigned int regs2[4]; |
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119 |
8860 | 120 memset(caps, 0, sizeof(*caps)); |
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121 caps->isX86=1; |
8860 | 122 caps->cl_size=32; /* default */ |
2288 | 123 if (!has_cpuid()) { |
6134 | 124 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 125 return; |
126 } | |
127 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 128 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 129 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 130 if (regs[0]>=0x00000001) |
2280 | 131 { |
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132 char *tmpstr, *ptmpstr; |
8860 | 133 unsigned cl_size; |
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134 |
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135 do_cpuid(0x00000001, regs2); |
2301 | 136 |
2288 | 137 caps->cpuType=(regs2[0] >> 8)&0xf; |
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138 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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139 |
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140 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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141 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 142 if(caps->cpuType==0xf){ |
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143 // use extended family (P4, IA64, K8) |
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144 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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145 } |
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146 if(caps->cpuType==0xf || caps->cpuType==6) |
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147 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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148 |
3403 | 149 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 150 |
151 // general feature flags: | |
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152 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 153 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
154 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
155 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
28015 | 156 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 |
2288 | 157 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 158 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
159 if(cl_size) caps->cl_size = cl_size; | |
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160 |
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161 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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162 while(*ptmpstr == ' ') // strip leading spaces |
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163 ptmpstr++; |
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164 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
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165 free(tmpstr); |
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166 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
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167 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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168 |
2288 | 169 } |
170 do_cpuid(0x80000000, regs); | |
171 if (regs[0]>=0x80000001) { | |
6134 | 172 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 173 do_cpuid(0x80000001, regs2); |
3840 | 174 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
175 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 176 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
177 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
28015 | 178 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 |
2288 | 179 } |
8860 | 180 if(regs[0]>=0x80000006) |
181 { | |
182 do_cpuid(0x80000006, regs2); | |
183 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
184 caps->cl_size = regs2[2] & 0xFF; | |
185 } | |
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186 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 187 #if 0 |
5937 | 188 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 189 gCpuCaps.hasMMX, |
190 gCpuCaps.hasMMX2, | |
191 gCpuCaps.hasSSE, | |
192 gCpuCaps.hasSSE2, | |
193 gCpuCaps.has3DNow, | |
194 gCpuCaps.has3DNowExt ); | |
195 #endif | |
196 | |
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197 /* FIXME: Does SSE2 need more OS support, too? */ |
26060 | 198 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
199 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \ | |
26061 | 200 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \ |
201 || defined(__OS2__) | |
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202 if (caps->hasSSE) |
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203 check_os_katmai_support(); |
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204 if (!caps->hasSSE) |
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205 caps->hasSSE2 = 0; |
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206 #else |
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207 caps->hasSSE=0; |
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208 caps->hasSSE2 = 0; |
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209 #endif |
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210 // caps->has3DNow=1; |
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211 // caps->hasMMX2 = 0; |
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212 // caps->hasMMX = 0; |
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213 |
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214 #ifndef RUNTIME_CPUDETECT |
4829 | 215 #ifndef HAVE_MMX |
6134 | 216 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 217 caps->hasMMX=0; |
218 #endif | |
219 #ifndef HAVE_MMX2 | |
6134 | 220 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 221 caps->hasMMX2=0; |
222 #endif | |
223 #ifndef HAVE_SSE | |
6134 | 224 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 225 caps->hasSSE=0; |
226 #endif | |
227 #ifndef HAVE_SSE2 | |
6134 | 228 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 229 caps->hasSSE2=0; |
230 #endif | |
231 #ifndef HAVE_3DNOW | |
6134 | 232 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 233 caps->has3DNow=0; |
234 #endif | |
235 #ifndef HAVE_3DNOWEX | |
6134 | 236 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 237 caps->has3DNowExt=0; |
238 #endif | |
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239 #endif // RUNTIME_CPUDETECT |
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240 } |
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241 |
2301 | 242 |
243 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
244 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
245 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
246 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
247 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
248 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
249 | |
250 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
251 #include "cputable.h" /* get cpuname and cpuvendors */ | |
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252 char vendor[13]; |
2303 | 253 char *retname; |
13628 | 254 int i; |
2301 | 255 |
18869 | 256 if (NULL==(retname=malloc(256))) { |
5937 | 257 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 258 exit(1); |
259 } | |
260 | |
3837 | 261 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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262 |
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263 do_cpuid(0x80000000,regs); |
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264 if (regs[0] >= 0x80000004) |
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265 { |
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266 // CPU has built-in namestring |
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267 retname[0] = '\0'; |
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268 for (i = 0x80000002; i <= 0x80000004; i++) |
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269 { |
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270 do_cpuid(i, regs); |
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271 strncat(retname, (char*)regs, 16); |
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272 } |
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273 return retname; |
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274 } |
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275 |
2301 | 276 for(i=0; i<MAX_VENDORS; i++){ |
277 if(!strcmp(cpuvendors[i].string,vendor)){ | |
278 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 279 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 280 } else { |
13628 | 281 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 282 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
283 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
284 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
285 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
286 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
287 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
288 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 289 "to the MPlayer-Developers, so we can add it to the list!\n"); |
290 } | |
291 } | |
292 } | |
14478 | 293 retname[255] = 0; |
2301 | 294 |
295 //printf("Detected CPU: %s\n", retname); | |
296 return retname; | |
297 } | |
298 | |
299 #undef CPUID_EXTFAMILY | |
300 #undef CPUID_EXTMODEL | |
301 #undef CPUID_TYPE | |
302 #undef CPUID_FAMILY | |
303 #undef CPUID_MODEL | |
304 #undef CPUID_STEPPING | |
305 | |
306 | |
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307 #if defined(__linux__) && defined(_POSIX_SOURCE) && !defined(ARCH_X86_64) |
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308 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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309 { |
6134 | 310 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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311 |
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312 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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313 * instructions are 3 bytes long. We must increment the instruction |
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314 * pointer manually to avoid repeated execution of the offending |
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315 * instruction. |
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316 * |
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317 * If the SIGILL is caused by a divide-by-zero when unmasked |
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318 * exceptions aren't supported, the SIMD FPU status and control |
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319 * word will be restored at the end of the test, so we don't need |
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320 * to worry about doing it here. Besides, we may not be able to... |
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321 */ |
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322 sc.eip += 3; |
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323 |
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324 gCpuCaps.hasSSE=0; |
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325 } |
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326 #endif /* __linux__ && _POSIX_SOURCE */ |
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327 |
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328 #if defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 329 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
330 { | |
331 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
332 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
333 ep->ContextRecord->Eip +=3; | |
334 gCpuCaps.hasSSE=0; | |
335 return EXCEPTION_CONTINUE_EXECUTION; | |
336 } | |
337 return EXCEPTION_CONTINUE_SEARCH; | |
338 } | |
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339 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 340 |
26061 | 341 #ifdef __OS2__ |
342 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
343 PEXCEPTIONREGISTRATIONRECORD p2, | |
344 PCONTEXTRECORD p3, | |
345 PVOID p4 ) | |
346 { | |
347 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
348 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
349 | |
350 p3->ctx_RegEip += 3; | |
351 gCpuCaps.hasSSE = 0; | |
352 | |
353 return XCPT_CONTINUE_EXECUTION; | |
354 } | |
355 return XCPT_CONTINUE_SEARCH; | |
356 } | |
357 #endif | |
358 | |
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359 /* If we're running on a processor that can do SSE, let's see if we |
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360 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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361 * haven't been configured for a Pentium III but are running on one, |
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362 * and RedHat patched 2.2 kernels that have broken exception handling |
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363 * support for user space apps that do SSE. |
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364 */ |
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365 |
21848 | 366 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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367 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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368 #elif defined(__APPLE__) |
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369 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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370 #endif |
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371 |
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372 static void check_os_katmai_support( void ) |
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373 { |
14455 | 374 #ifdef ARCH_X86_64 |
375 gCpuCaps.hasSSE=1; | |
376 gCpuCaps.hasSSE2=1; | |
21848 | 377 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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378 int has_sse=0, ret; |
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379 size_t len=sizeof(has_sse); |
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380 |
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381 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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382 if (ret || !has_sse) |
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383 gCpuCaps.hasSSE=0; |
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384 |
12143 | 385 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
386 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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387 int has_sse, has_sse2, ret, mib[2]; |
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388 size_t varlen; |
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389 |
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390 mib[0] = CTL_MACHDEP; |
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391 mib[1] = CPU_SSE; |
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392 varlen = sizeof(has_sse); |
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393 |
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394 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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395 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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396 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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397 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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398 |
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399 mib[1] = CPU_SSE2; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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400 varlen = sizeof(has_sse2); |
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401 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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402 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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403 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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404 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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405 #else |
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406 gCpuCaps.hasSSE = 0; |
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407 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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408 #endif |
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409 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 410 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
411 if ( gCpuCaps.hasSSE ) { | |
412 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
413 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
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414 __asm__ volatile ("xorps %xmm0, %xmm0"); |
10440 | 415 SetUnhandledExceptionFilter(exc_fil); |
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416 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
10440 | 417 } |
26061 | 418 #elif defined(__OS2__) |
419 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
420 if ( gCpuCaps.hasSSE ) { | |
421 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
422 DosSetExceptionHandler( &RegRec ); | |
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423 __asm__ volatile ("xorps %xmm0, %xmm0"); |
26061 | 424 DosUnsetExceptionHandler( &RegRec ); |
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425 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
26061 | 426 } |
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427 #elif defined(__linux__) |
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428 #if defined(_POSIX_SOURCE) |
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429 struct sigaction saved_sigill; |
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430 |
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431 /* Save the original signal handlers. |
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432 */ |
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433 sigaction( SIGILL, NULL, &saved_sigill ); |
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434 |
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435 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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436 |
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437 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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438 * supports the extended FPU save and restore required for SSE. If |
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439 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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440 * doesn't support Streaming SIMD Exceptions, even if the processor |
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441 * does. |
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442 */ |
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443 if ( gCpuCaps.hasSSE ) { |
6134 | 444 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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445 |
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446 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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447 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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448 |
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449 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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450 } |
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451 |
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452 /* Restore the original signal handlers. |
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453 */ |
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454 sigaction( SIGILL, &saved_sigill, NULL ); |
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455 |
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456 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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457 * safe to go ahead and hook out the SSE code throughout Mesa. |
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458 */ |
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459 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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460 #else |
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461 /* We can't use POSIX signal handling to test the availability of |
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462 * SSE, so we disable it by default. |
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463 */ |
5937 | 464 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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465 gCpuCaps.hasSSE=0; |
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466 #endif /* _POSIX_SOURCE */ |
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467 #else |
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468 /* Do nothing on other platforms for now. |
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469 */ |
6134 | 470 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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471 gCpuCaps.hasSSE=0; |
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472 #endif /* __linux__ */ |
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473 } |
20577 | 474 #else /* ARCH_X86 */ |
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475 |
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476 #ifdef __APPLE__ |
9003 | 477 #include <sys/sysctl.h> |
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478 #elif __AMIGAOS4__ |
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479 /* nothing */ |
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480 #else |
9003 | 481 #include <signal.h> |
482 #include <setjmp.h> | |
483 | |
484 static sigjmp_buf jmpbuf; | |
485 static volatile sig_atomic_t canjump = 0; | |
486 | |
487 static void sigill_handler (int sig) | |
488 { | |
489 if (!canjump) { | |
490 signal (sig, SIG_DFL); | |
491 raise (sig); | |
492 } | |
493 | |
494 canjump = 0; | |
495 siglongjmp (jmpbuf, 1); | |
496 } | |
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497 #endif /* __APPLE__ */ |
9003 | 498 |
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499 void GetCpuCaps( CpuCaps *caps) |
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500 { |
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501 caps->cpuType=0; |
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502 caps->cpuModel=0; |
3403 | 503 caps->cpuStepping=0; |
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504 caps->hasMMX=0; |
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505 caps->hasMMX2=0; |
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506 caps->has3DNow=0; |
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507 caps->has3DNowExt=0; |
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508 caps->hasSSE=0; |
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509 caps->hasSSE2=0; |
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510 caps->hasSSSE3=0; |
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511 caps->hasSSE4a=0; |
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512 caps->isX86=0; |
9003 | 513 caps->hasAltiVec = 0; |
514 #ifdef HAVE_ALTIVEC | |
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515 #ifdef __APPLE__ |
9003 | 516 /* |
517 rip-off from ffmpeg altivec detection code. | |
518 this code also appears on Apple's AltiVec pages. | |
519 */ | |
520 { | |
521 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
522 int has_vu = 0; | |
523 size_t len = sizeof(has_vu); | |
524 int err; | |
525 | |
526 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
527 | |
528 if (err == 0) | |
529 if (has_vu != 0) | |
530 caps->hasAltiVec = 1; | |
531 } | |
25339 | 532 #elif __AMIGAOS4__ |
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533 ULONG result = 0; |
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534 |
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535 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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536 if (result == VECTORTYPE_ALTIVEC) |
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537 caps->hasAltiVec = 1; |
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538 #else |
9003 | 539 /* no Darwin, do it the brute-force way */ |
540 /* this is borrowed from the libmpeg2 library */ | |
541 { | |
542 signal (SIGILL, sigill_handler); | |
543 if (sigsetjmp (jmpbuf, 1)) { | |
544 signal (SIGILL, SIG_DFL); | |
545 } else { | |
546 canjump = 1; | |
547 | |
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548 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 549 "vand %%v0, %%v0, %%v0" |
9003 | 550 : |
551 : "r" (-1)); | |
552 | |
553 signal (SIGILL, SIG_DFL); | |
554 caps->hasAltiVec = 1; | |
555 } | |
556 } | |
25329
676e2ace8a46
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557 #endif /* __APPLE__ */ |
9324 | 558 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 559 #endif /* HAVE_ALTIVEC */ |
11962
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560 |
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561 #ifdef ARCH_IA64 |
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562 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
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563 #endif |
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564 |
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565 #ifdef ARCH_SPARC |
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566 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
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567 #endif |
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568 |
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569 #ifdef ARCH_ARMV4L |
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570 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
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571 #endif |
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572 |
28161 | 573 #ifdef ARCH_PPC |
11962
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574 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
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575 #endif |
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576 |
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577 #ifdef ARCH_ALPHA |
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578 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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579 #endif |
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580 |
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581 #ifdef ARCH_SGI_MIPS |
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582 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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583 #endif |
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584 |
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585 #ifdef ARCH_PA_RISC |
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586 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
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587 #endif |
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|
588 |
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|
589 #ifdef ARCH_S390 |
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590 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
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591 #endif |
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592 |
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|
593 #ifdef ARCH_S390X |
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594 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
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595 #endif |
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|
596 |
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|
597 #ifdef ARCH_VAX |
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598 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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599 #endif |
25340 | 600 |
601 #ifdef ARCH_XTENSA | |
602 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" ); | |
603 #endif | |
3146
3164eaa93396
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|
604 } |
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non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
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|
605 #endif /* !ARCH_X86 */ |