Mercurial > mplayer.hg
annotate cpudetect.c @ 17403:9150653ba6d4
typos
author | diego |
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date | Mon, 16 Jan 2006 03:46:58 +0000 |
parents | fab832f37083 |
children | f580a7755ac5 |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #if defined(ARCH_X86) || defined(ARCH_X86_64) |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #endif |
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22 |
15566 | 23 #if defined(__FreeBSD__) || defined(__DragonFly__) |
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24 #include <sys/types.h> |
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25 #include <sys/sysctl.h> |
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26 #endif |
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27 |
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28 #ifdef __linux__ |
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29 #include <signal.h> |
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30 #endif |
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31 |
10440 | 32 #ifdef WIN32 |
33 #include <windows.h> | |
34 #endif | |
35 | |
2272 | 36 //#define X86_FXSR_MAGIC |
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37 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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38 * help understanding how to use it. Thanks to the Mesa |
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39 * team for SSE support detection and more cpu detect code. |
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40 */ |
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41 |
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42 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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43 |
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44 static void check_os_katmai_support( void ); |
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45 |
2272 | 46 #if 1 |
47 // return TRUE if cpuid supported | |
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48 static int has_cpuid() |
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49 { |
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50 long a, c; |
2272 | 51 |
52 // code from libavcodec: | |
53 __asm__ __volatile__ ( | |
54 /* See if CPUID instruction is supported ... */ | |
55 /* ... Get copies of EFLAGS into eax and ecx */ | |
56 "pushf\n\t" | |
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57 "pop %0\n\t" |
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58 "mov %0, %1\n\t" |
2272 | 59 |
60 /* ... Toggle the ID bit in one copy and store */ | |
61 /* to the EFLAGS reg */ | |
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62 "xor $0x200000, %0\n\t" |
2272 | 63 "push %0\n\t" |
64 "popf\n\t" | |
65 | |
66 /* ... Get the (hopefully modified) EFLAGS */ | |
67 "pushf\n\t" | |
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68 "pop %0\n\t" |
2272 | 69 : "=a" (a), "=c" (c) |
70 : | |
71 : "cc" | |
72 ); | |
73 | |
74 return (a!=c); | |
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75 } |
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76 #endif |
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77 |
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78 static void |
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79 do_cpuid(unsigned int ax, unsigned int *p) |
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80 { |
2272 | 81 #if 0 |
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82 __asm __volatile( |
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83 "cpuid;" |
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84 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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85 : "0" (ax) |
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86 ); |
2272 | 87 #else |
88 // code from libavcodec: | |
89 __asm __volatile | |
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90 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 91 "cpuid\n\t" |
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92 "xchg %%"REG_b", %%"REG_S |
3403 | 93 : "=a" (p[0]), "=S" (p[1]), |
2272 | 94 "=c" (p[2]), "=d" (p[3]) |
95 : "0" (ax)); | |
96 #endif | |
97 | |
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98 } |
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99 |
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100 void GetCpuCaps( CpuCaps *caps) |
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101 { |
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102 unsigned int regs[4]; |
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103 unsigned int regs2[4]; |
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104 |
8860 | 105 memset(caps, 0, sizeof(*caps)); |
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106 caps->isX86=1; |
8860 | 107 caps->cl_size=32; /* default */ |
2288 | 108 if (!has_cpuid()) { |
6134 | 109 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 110 return; |
111 } | |
112 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 113 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 114 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 115 if (regs[0]>=0x00000001) |
2280 | 116 { |
2303 | 117 char *tmpstr; |
8860 | 118 unsigned cl_size; |
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119 |
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120 do_cpuid(0x00000001, regs2); |
2301 | 121 |
2288 | 122 caps->cpuType=(regs2[0] >> 8)&0xf; |
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123 |
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124 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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125 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 126 if(caps->cpuType==0xf){ |
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127 // use extended family (P4, IA64, K8) |
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128 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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129 } |
3403 | 130 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 131 |
132 // general feature flags: | |
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133 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 134 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
135 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
136 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
2288 | 137 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 138 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
139 if(cl_size) caps->cl_size = cl_size; | |
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140 |
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141 tmpstr=GetCpuFriendlyName(regs, regs2); |
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142 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ",tmpstr); |
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143 free(tmpstr); |
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144 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Stepping: %d)\n", |
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145 caps->cpuType, caps->cpuStepping); |
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146 |
2288 | 147 } |
148 do_cpuid(0x80000000, regs); | |
149 if (regs[0]>=0x80000001) { | |
6134 | 150 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 151 do_cpuid(0x80000001, regs2); |
3840 | 152 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
153 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 154 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
155 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
156 } | |
8860 | 157 if(regs[0]>=0x80000006) |
158 { | |
159 do_cpuid(0x80000006, regs2); | |
160 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
161 caps->cl_size = regs2[2] & 0xFF; | |
162 } | |
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163 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 164 #if 0 |
5937 | 165 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 166 gCpuCaps.hasMMX, |
167 gCpuCaps.hasMMX2, | |
168 gCpuCaps.hasSSE, | |
169 gCpuCaps.hasSSE2, | |
170 gCpuCaps.has3DNow, | |
171 gCpuCaps.has3DNowExt ); | |
172 #endif | |
173 | |
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174 /* FIXME: Does SSE2 need more OS support, too? */ |
15566 | 175 #if defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) || defined(__CYGWIN__) || defined(__OpenBSD__) || defined(__DragonFly__) |
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176 if (caps->hasSSE) |
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177 check_os_katmai_support(); |
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178 if (!caps->hasSSE) |
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179 caps->hasSSE2 = 0; |
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180 #else |
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181 caps->hasSSE=0; |
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182 caps->hasSSE2 = 0; |
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183 #endif |
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184 // caps->has3DNow=1; |
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185 // caps->hasMMX2 = 0; |
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186 // caps->hasMMX = 0; |
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187 |
4829 | 188 #ifndef HAVE_MMX |
6134 | 189 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 190 caps->hasMMX=0; |
191 #endif | |
192 #ifndef HAVE_MMX2 | |
6134 | 193 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 194 caps->hasMMX2=0; |
195 #endif | |
196 #ifndef HAVE_SSE | |
6134 | 197 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 198 caps->hasSSE=0; |
199 #endif | |
200 #ifndef HAVE_SSE2 | |
6134 | 201 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 202 caps->hasSSE2=0; |
203 #endif | |
204 #ifndef HAVE_3DNOW | |
6134 | 205 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 206 caps->has3DNow=0; |
207 #endif | |
208 #ifndef HAVE_3DNOWEX | |
6134 | 209 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 210 caps->has3DNowExt=0; |
211 #endif | |
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212 } |
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213 |
2301 | 214 |
215 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
216 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
217 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
218 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
219 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
220 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
221 | |
222 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
223 #include "cputable.h" /* get cpuname and cpuvendors */ | |
13628 | 224 char vendor[17]; |
2303 | 225 char *retname; |
13628 | 226 int i; |
2301 | 227 |
2417 | 228 if (NULL==(retname=(char*)malloc(256))) { |
5937 | 229 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 230 exit(1); |
231 } | |
232 | |
3837 | 233 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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234 |
2301 | 235 for(i=0; i<MAX_VENDORS; i++){ |
236 if(!strcmp(cpuvendors[i].string,vendor)){ | |
237 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 238 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 239 } else { |
13628 | 240 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 241 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
242 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
243 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
244 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
245 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
246 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
247 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 248 "to the MPlayer-Developers, so we can add it to the list!\n"); |
249 } | |
250 } | |
251 } | |
14478 | 252 retname[255] = 0; |
2301 | 253 |
254 //printf("Detected CPU: %s\n", retname); | |
255 return retname; | |
256 } | |
257 | |
258 #undef CPUID_EXTFAMILY | |
259 #undef CPUID_EXTMODEL | |
260 #undef CPUID_TYPE | |
261 #undef CPUID_FAMILY | |
262 #undef CPUID_MODEL | |
263 #undef CPUID_STEPPING | |
264 | |
265 | |
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266 #if defined(__linux__) && defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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267 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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268 { |
6134 | 269 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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270 |
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271 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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272 * instructions are 3 bytes long. We must increment the instruction |
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273 * pointer manually to avoid repeated execution of the offending |
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274 * instruction. |
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275 * |
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276 * If the SIGILL is caused by a divide-by-zero when unmasked |
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277 * exceptions aren't supported, the SIMD FPU status and control |
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278 * word will be restored at the end of the test, so we don't need |
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279 * to worry about doing it here. Besides, we may not be able to... |
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280 */ |
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281 sc.eip += 3; |
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282 |
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283 gCpuCaps.hasSSE=0; |
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284 } |
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285 |
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286 static void sigfpe_handler_sse( int signal, struct sigcontext sc ) |
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287 { |
6134 | 288 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " ); |
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289 |
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290 if ( sc.fpstate->magic != 0xffff ) { |
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291 /* Our signal context has the extended FPU state, so reset the |
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292 * divide-by-zero exception mask and clear the divide-by-zero |
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293 * exception bit. |
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294 */ |
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295 sc.fpstate->mxcsr |= 0x00000200; |
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296 sc.fpstate->mxcsr &= 0xfffffffb; |
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297 } else { |
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298 /* If we ever get here, we're completely hosed. |
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299 */ |
6134 | 300 mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" ); |
301 mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" ); | |
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302 } |
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303 } |
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304 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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305 |
10440 | 306 #ifdef WIN32 |
307 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) | |
308 { | |
309 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
310 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
311 ep->ContextRecord->Eip +=3; | |
312 gCpuCaps.hasSSE=0; | |
313 return EXCEPTION_CONTINUE_EXECUTION; | |
314 } | |
315 return EXCEPTION_CONTINUE_SEARCH; | |
316 } | |
317 #endif /* WIN32 */ | |
318 | |
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319 /* If we're running on a processor that can do SSE, let's see if we |
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320 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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321 * haven't been configured for a Pentium III but are running on one, |
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322 * and RedHat patched 2.2 kernels that have broken exception handling |
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323 * support for user space apps that do SSE. |
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324 */ |
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325 static void check_os_katmai_support( void ) |
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326 { |
14455 | 327 #ifdef ARCH_X86_64 |
328 gCpuCaps.hasSSE=1; | |
329 gCpuCaps.hasSSE2=1; | |
15566 | 330 #elif defined(__FreeBSD__) || defined(__DragonFly__) |
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331 int has_sse=0, ret; |
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332 size_t len=sizeof(has_sse); |
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333 |
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334 ret = sysctlbyname("hw.instruction_sse", &has_sse, &len, NULL, 0); |
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335 if (ret || !has_sse) |
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336 gCpuCaps.hasSSE=0; |
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337 |
12143 | 338 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
339 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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340 int has_sse, has_sse2, ret, mib[2]; |
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341 size_t varlen; |
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342 |
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343 mib[0] = CTL_MACHDEP; |
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344 mib[1] = CPU_SSE; |
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345 varlen = sizeof(has_sse); |
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346 |
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347 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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348 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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349 if (ret < 0 || !has_sse) { |
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350 gCpuCaps.hasSSE=0; |
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351 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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352 } else { |
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353 gCpuCaps.hasSSE=1; |
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354 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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355 } |
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356 |
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357 mib[1] = CPU_SSE2; |
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358 varlen = sizeof(has_sse2); |
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359 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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360 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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361 if (ret < 0 || !has_sse2) { |
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362 gCpuCaps.hasSSE2=0; |
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363 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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364 } else { |
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365 gCpuCaps.hasSSE2=1; |
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366 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes!\n" ); |
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367 } |
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368 #else |
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369 gCpuCaps.hasSSE = 0; |
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370 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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371 #endif |
10440 | 372 #elif defined(WIN32) |
373 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; | |
374 if ( gCpuCaps.hasSSE ) { | |
375 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
376 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
377 __asm __volatile ("xorps %xmm0, %xmm0"); | |
378 SetUnhandledExceptionFilter(exc_fil); | |
379 if ( gCpuCaps.hasSSE ) mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); | |
380 else mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); | |
381 } | |
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382 #elif defined(__linux__) |
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383 #if defined(_POSIX_SOURCE) && defined(X86_FXSR_MAGIC) |
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384 struct sigaction saved_sigill; |
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385 struct sigaction saved_sigfpe; |
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386 |
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387 /* Save the original signal handlers. |
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388 */ |
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389 sigaction( SIGILL, NULL, &saved_sigill ); |
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390 sigaction( SIGFPE, NULL, &saved_sigfpe ); |
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391 |
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392 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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393 signal( SIGFPE, (void (*)(int))sigfpe_handler_sse ); |
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394 |
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395 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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396 * supports the extended FPU save and restore required for SSE. If |
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397 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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398 * doesn't support Streaming SIMD Exceptions, even if the processor |
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399 * does. |
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400 */ |
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401 if ( gCpuCaps.hasSSE ) { |
6134 | 402 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
2268
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403 |
2272 | 404 // __asm __volatile ("xorps %%xmm0, %%xmm0"); |
405 __asm __volatile ("xorps %xmm0, %xmm0"); | |
2268
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406 |
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407 if ( gCpuCaps.hasSSE ) { |
6134 | 408 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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409 } else { |
6134 | 410 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
2268
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411 } |
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412 } |
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413 |
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414 /* Emulate test for OSXMMEXCPT in CR4. The OS will set this bit if |
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415 * it supports unmasked SIMD FPU exceptions. If we unmask the |
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416 * exceptions, do a SIMD divide-by-zero and get a SIGILL, the OS |
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417 * doesn't support unmasked SIMD FPU exceptions. If we get a SIGFPE |
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418 * as expected, we're okay but we need to clean up after it. |
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419 * |
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420 * Are we being too stringent in our requirement that the OS support |
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421 * unmasked exceptions? Certain RedHat 2.2 kernels enable SSE by |
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422 * setting CR4.OSFXSR but don't support unmasked exceptions. Win98 |
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423 * doesn't even support them. We at least know the user-space SSE |
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424 * support is good in kernels that do support unmasked exceptions, |
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425 * and therefore to be safe I'm going to leave this test in here. |
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426 */ |
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427 if ( gCpuCaps.hasSSE ) { |
6134 | 428 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE unmasked exceptions... " ); |
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429 |
2272 | 430 // test_os_katmai_exception_support(); |
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431 |
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432 if ( gCpuCaps.hasSSE ) { |
6134 | 433 mp_msg(MSGT_CPUDETECT,MSGL_V, "yes.\n" ); |
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434 } else { |
6134 | 435 mp_msg(MSGT_CPUDETECT,MSGL_V, "no!\n" ); |
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436 } |
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437 } |
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438 |
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439 /* Restore the original signal handlers. |
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440 */ |
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441 sigaction( SIGILL, &saved_sigill, NULL ); |
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442 sigaction( SIGFPE, &saved_sigfpe, NULL ); |
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443 |
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444 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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445 * safe to go ahead and hook out the SSE code throughout Mesa. |
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446 */ |
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447 if ( gCpuCaps.hasSSE ) { |
6134 | 448 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE passed.\n" ); |
2268
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449 } else { |
6134 | 450 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE failed!\n" ); |
2268
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451 } |
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452 #else |
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453 /* We can't use POSIX signal handling to test the availability of |
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454 * SSE, so we disable it by default. |
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455 */ |
5937 | 456 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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457 gCpuCaps.hasSSE=0; |
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458 #endif /* _POSIX_SOURCE && X86_FXSR_MAGIC */ |
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459 #else |
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460 /* Do nothing on other platforms for now. |
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461 */ |
6134 | 462 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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463 gCpuCaps.hasSSE=0; |
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464 #endif /* __linux__ */ |
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465 } |
13720
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466 #else /* ARCH_X86 || ARCH_X86_64 */ |
3146
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467 |
9003 | 468 #ifdef SYS_DARWIN |
469 #include <sys/sysctl.h> | |
470 #else | |
471 #include <signal.h> | |
472 #include <setjmp.h> | |
473 | |
474 static sigjmp_buf jmpbuf; | |
475 static volatile sig_atomic_t canjump = 0; | |
476 | |
477 static void sigill_handler (int sig) | |
478 { | |
479 if (!canjump) { | |
480 signal (sig, SIG_DFL); | |
481 raise (sig); | |
482 } | |
483 | |
484 canjump = 0; | |
485 siglongjmp (jmpbuf, 1); | |
486 } | |
487 #endif | |
488 | |
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489 void GetCpuCaps( CpuCaps *caps) |
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490 { |
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491 caps->cpuType=0; |
3403 | 492 caps->cpuStepping=0; |
3146
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493 caps->hasMMX=0; |
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494 caps->hasMMX2=0; |
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495 caps->has3DNow=0; |
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496 caps->has3DNowExt=0; |
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497 caps->hasSSE=0; |
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498 caps->hasSSE2=0; |
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499 caps->isX86=0; |
9003 | 500 caps->hasAltiVec = 0; |
501 #ifdef HAVE_ALTIVEC | |
502 #ifdef SYS_DARWIN | |
503 /* | |
504 rip-off from ffmpeg altivec detection code. | |
505 this code also appears on Apple's AltiVec pages. | |
506 */ | |
507 { | |
508 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
509 int has_vu = 0; | |
510 size_t len = sizeof(has_vu); | |
511 int err; | |
512 | |
513 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
514 | |
515 if (err == 0) | |
516 if (has_vu != 0) | |
517 caps->hasAltiVec = 1; | |
518 } | |
519 #else /* SYS_DARWIN */ | |
520 /* no Darwin, do it the brute-force way */ | |
521 /* this is borrowed from the libmpeg2 library */ | |
522 { | |
523 signal (SIGILL, sigill_handler); | |
524 if (sigsetjmp (jmpbuf, 1)) { | |
525 signal (SIGILL, SIG_DFL); | |
526 } else { | |
527 canjump = 1; | |
528 | |
529 asm volatile ("mtspr 256, %0\n\t" | |
9122 | 530 "vand %%v0, %%v0, %%v0" |
9003 | 531 : |
532 : "r" (-1)); | |
533 | |
534 signal (SIGILL, SIG_DFL); | |
535 caps->hasAltiVec = 1; | |
536 } | |
537 } | |
538 #endif /* SYS_DARWIN */ | |
9324 | 539 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 540 #endif /* HAVE_ALTIVEC */ |
11962
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541 |
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542 #ifdef ARCH_IA64 |
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543 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
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544 #endif |
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545 |
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546 #ifdef ARCH_SPARC |
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547 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
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548 #endif |
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549 |
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550 #ifdef ARCH_ARMV4L |
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551 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
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552 #endif |
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553 |
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554 #ifdef ARCH_POWERPC |
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555 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
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556 #endif |
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557 |
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558 #ifdef ARCH_ALPHA |
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559 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
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560 #endif |
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|
561 |
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562 #ifdef ARCH_SGI_MIPS |
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563 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
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564 #endif |
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|
565 |
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|
566 #ifdef ARCH_PA_RISC |
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567 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
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changeset
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568 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
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changeset
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569 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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570 #ifdef ARCH_S390 |
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571 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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572 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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changeset
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573 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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574 #ifdef ARCH_S390X |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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575 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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576 #endif |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
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diff
changeset
|
577 |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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578 #ifdef ARCH_VAX |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
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579 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
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architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
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580 #endif |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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2417
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changeset
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581 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
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diff
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582 #endif /* !ARCH_X86 */ |